CN105453273A - 具有匹配阈值电压的集成电路及其制造方法 - Google Patents

具有匹配阈值电压的集成电路及其制造方法 Download PDF

Info

Publication number
CN105453273A
CN105453273A CN201480043093.4A CN201480043093A CN105453273A CN 105453273 A CN105453273 A CN 105453273A CN 201480043093 A CN201480043093 A CN 201480043093A CN 105453273 A CN105453273 A CN 105453273A
Authority
CN
China
Prior art keywords
grid
barrier layer
contact
depression
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480043093.4A
Other languages
English (en)
Other versions
CN105453273B (zh
Inventor
曹建军
罗伯特·比奇
亚历山大·利道
阿兰娜·纳卡塔
罗伯特·斯特里特马特
赵广元
马艳萍
周春华
塞沙德里·科卢里
刘芳昌
蒋明坤
曹佳丽
阿古斯·裘哈尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Efficient Power Conversion Corp
Original Assignee
Efficient Power Conversion Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Efficient Power Conversion Corp filed Critical Efficient Power Conversion Corp
Publication of CN105453273A publication Critical patent/CN105453273A/zh
Application granted granted Critical
Publication of CN105453273B publication Critical patent/CN105453273B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种集成电路具有衬底、形成于所述衬底上的缓冲层、形成于所述缓冲层上的阻挡层以及隔离区，其将增强型设备与耗尽型设备隔离开。集成电路进一步包括沉积在一个栅极接触凹陷中的所述增强型设备的第一栅极触点和沉积在另一个栅极接触凹陷中的所述耗尽型设备的第二栅极触点。

Description

具有匹配阈值电压的集成电路及其制造方法
本发明的背景
发明的领域
本发明总地涉及集成电路和设备，并且具体地，涉及匹配增强型和耗尽型设备的阈值电压以及减小氮化镓(GaN)设备的输出电容。
相关技术的说明
GaN半导体设备由于它们的高频率转换、携带大电流和支持高电压的能力越来越受欢迎。这些设备的开发一般针对高功率/高频率应用。为这些类型的应用制造的设备是基于呈现高电子迁移率并且不同地被称为异质结场效应晶体管(HFET)、高电子迁移率晶体管(HEMT)或调制掺杂场效应晶体管(MODFET)的通用设备结构。这些类型的设备在高频率操作时，例如100kHz-100GHz，典型地可以承受高电压，例如30V-2000V。
GaNHEMT设备包括具有至少两个氮化物层的氮化物半导体。在半导体或缓冲层上形成的不同材料使得层间具有不同的能带间隙。相邻氮化物层中的不同材料还会引起极化，其导致两个层的接合点附近尤其是在具有狭窄能带间隙的层中形成导电二维电子气(2DEG)区域。
引起极化的氮化物层典型地包括靠近GaN层的AlGaN阻挡层以包括该2DEG，其允许电荷流经该设备。该阻挡层可掺杂或不掺杂。由于该2DEG区在零栅极偏置电压时存在于栅极下方，大部分的氮化物设备是常开(on)的或是耗尽型设备。若位于栅极下方的该2DEG区在施加的零栅极偏置电压下被耗尽(即被移除)，该设备可为增强型设备。由于它们提供的增加的安全性，并且由于它们更容易用简单、低成本驱动电路控制，增强型设备是常闭(OFF)的并且是所期望的。为了传导电流，增强型设备需要在栅极施加正向偏置电压。
在某些集成电路设计中，高电子迁移率晶体管(HEMT)或赝配高电子迁移率晶体管((p-)HEMT)被分为具有负值阈值电压VTh的耗尽型晶体管与具有正值阈值电压VTh的增强型晶体管。在这样的设计中，增强型和耗尽型设备的阈值电压VTh的绝对值相等是所期望的。例如，若增强型的阈值电压VTh为正1.5伏，则耗尽型设备的阈值电压VTh应为负1.5伏。
本发明提供了实现具有相同绝对值的增强型和耗尽型设备的方法。
发明内容
下面描述的实施例通过提供具有增强型设备和耗尽型设备的集成电路解决了上面讨论的问题和其他问题，该集成电路包括隔离两个设备的隔离区和较薄区或栅极下面氮化铝镓(AlGaN)阻挡层中的栅极接触凹陷，其可以用于调制增强型和耗尽型设备的阈值电压VTh，以使该阈值电压的绝对值近似相等。
尤其是，本文公开了集成电路，具有衬底；至少一个缓冲层，形成于衬底之上；阻挡层，形成于至少一个缓冲层之上；以及隔离区，形成用于将第一晶体管设备的阻挡层的第一部分与第二晶体管设备的阻挡层的第二部分隔离开，阻挡层的第一部分和第二部分的每个都具有各自的栅极接触凹陷。集成电路进一步包括至少部分沉积在第一晶体管设备的阻挡层的第一部分的栅极接触凹陷中的第一栅极触点；以及至少部分沉积在第二晶体管设备的阻挡层的第二部分的栅极接触凹陷中的第二栅极触点。在示例性的实施例中，第一晶体管设备和第二晶体管设备分别是增强型设备和耗尽型设备。
示例性实施例的一个目的是提供具有较低栅-漏电容(Cgd)和较低输出电容(Coss)的氮化镓功率设备。根据示例性的实施例，较薄AlGaN阻挡层的栅极接触凹陷延伸到栅极触点外面向漏极延伸。在此实施例中，由于在漏极侧面栅极角落的阻挡层是较薄的，所以该设备具有较低的2DEG密度，并且因此减小了栅-漏电容(Cgd)和输出电容(Coss)。
附图说明
上面指出的以及其他特征、对象和本公开的优点将从下面阐述的详细说明当连同附图时变得更加明显，其中相同的参考字符相应地始终确定，并且其中：
图1例示了根据本发明的示例性实施例的、具有增强型和耗尽型设备的集成电路具有匹配的阈值电压VTh。
图2例示了根据本发明的替代实施例的、集成电路100的增强型设备。
图3例示了根据本发明的替代实施例的、集成电路100的耗尽型设备。
图4是根据本发明的示例性实施例的、仅在栅极下面具有较薄阻挡层的设备和具有延伸到栅极外面向漏极延伸的较薄阻挡层的另一个设备的输出电容(Coss)的图示比较。
图5A-5F是根据本发明的示例性实施例的、例示了形成增强型设备和耗尽型设备具有匹配的阈值电压VTh的集成电路的制造工艺。
示例性的具体实施方式
在下面的详细说明中，对某些实施例进行了编号。这些实施例描述得足够详细以使本领域技术人员能够实践它们。将理解的是，可以采用其他实施例并且可以进行多种结构、逻辑和电学变化。在下面的详细说明中公开的特征的组合在广义上对实践教导并不是必需的，并且而是仅教导描述本教导的特别典型的示例。
图1例示了根据本发明的示例性实施例的、集成电路的第一实施例。如所示，集成电路100包括增强型设备101和耗尽型设备201。集成电路100形成于衬底302上，所述衬底302由硅(Si)、碳化硅(SiC)、蓝宝石或用于半导体制造的任何其他合适的材料形成。然后，一个或多个缓冲层303形成于衬底302上。缓冲层303可以包括氮化铝(AlN)、氮化镓(GaN)、氮化铝镓等等。在示例性实施例中，缓冲层中的一个(即与阻挡层304最近的缓冲层)是沟道层，其首选地由氮化镓(GaN)组成。应理解，沟道层可以视为缓冲层中的一个或视为缓冲层和阻挡层之间的单独的层。而且，由氮化铝镓(AlGaN)或氮化铟铝镓(InAlGaN)形成的阻挡层304可以形成于缓冲层303之上，其在一些实施例中可以包括位于AlGaN下面的氮化铝(AlN)隔离层和位于氮化铝镓(未示出)上面的氮化镓(GaN)保护层。如上面指出的，二维电子气(2DEG)区(未用参考数字标记)形成于缓冲层303和阻挡层304之间的接口处。例如，如果缓冲层303包括由GaN形成的沟道层，则该2DEG区形成于GaN层和阻挡层304之间的接口处。
如进一步所示，增强型设备101包括源极102、栅极103和漏极105，以及覆盖该设备的介电薄膜107和可选的场板106。同样地，耗尽型设备201包括源极202、栅极203和漏极205，并且也包括介电薄膜207和可选的场板206。隔离区301形成于阻挡层304中，以将增强型设备101和耗尽型设备201的阻挡层分成第一和第二部分。应领会，虽然隔离区301被例示为图1的阻挡层304中的蚀刻出的窗口，但如本领域技术人员将理解的，在替代的实施例中，隔离区301可以通过离子注入形成。
为了调制增强型设备101的阈值电压VTh，阻挡层304包括栅极103下面的较薄部分104(即栅极触点部分104)，相比之下，阻挡层304的各部分未沉积在栅极103之下。栅极103下面的阻挡层的较薄部分104增加了正阈值电压VTh的值。如图1所示，栅极103延长了栅极接触凹陷104的整个宽度。类似地，为了调制耗尽型设备201的阈值电压VTh，阻挡层304包括栅极203下面的较薄部分204(即栅极触点部分204)，相比之下，阻挡层204的各部分未沉积在栅极203之下。栅极203下面的阻挡层的较薄部分204减小了负阈值电压VTh的值。如图1所示，栅极203延长了栅极接触凹陷204的整个宽度。
在图1例示的集成电路100的示例性实施例中，AlGaN阻挡层凹陷或位于栅极103、203之下的较薄阻挡层(即栅极接触凹陷)104、204可以分别用于调制增强型设备101和耗尽型设备201的阈值电压VTh，以使阈值电压的绝对值近似相等。尤其是，在制造期间，各自设备的栅极接触凹陷的厚度可以调节，以使阈值电压的绝对值近似相等。
图2例示了根据本发明的替代实施例的、集成电路100的增强型设备。类似地，图3例示了根据本发明的替代实施例的、集成电路100的耗尽型设备。
如图2和3的这些实施例所示，增强型设备1001和耗尽型设备2001的凹陷的阻挡层1004、2004延伸出或超过栅极1003、2003的侧面/边缘，向漏极1005、2005延伸。这个配置进一步减小了输出电容Coss、栅-漏电容Cgd和漏源泄漏并提高了漏到源的击穿电压。
注意到，图2和图3中例示的增强型设备1001和耗尽型设备2001的每个都分别另外与图1中示出的这些设备相同。具体地，图2中示出的增强型设备1001包括源极1002、栅极1003和漏极1005、覆盖该设备的介电薄膜1007和可选择的场板1006。类似地，图3中示出的耗尽型设备2001包括源极2002、栅极2003和漏极2005、覆盖该设备的介电薄膜2007和可选择的场板2006。
图4用示意图例示了图2和3的实施例中示出的、通过将较薄AlGaN阻挡层延伸到栅极外面并向漏极延伸，输出电容的减小程度。如所示，当漏-源电压(Vds)相对低时，图2和3中实施例化的设备的输出电容Coss较低。
图5A-5F例示了根据本发明的示例性实施例的、制造具有增强型设备101和耗尽型设备201的集成电路100的方法。
开始，如图5A中所示，在衬底302上生成EPI。如上面指出的，衬底由硅(Si)、碳化硅(SiC)、蓝宝石或任何其他合适的材料形成。然后一个或多个缓冲层形成于衬底302的顶面上。缓冲层303可以包括AlN、AlGaN和GaN。然后AlGaN阻挡层304可以形成于缓冲层303之上。在一个实施例中，可以在AlGaN阻挡层304下面提供AlN隔离层并且在在AlGaN阻挡层304上面提供GaN保护层。如本领域技术人员将理解的，EPI结构的每个层可以利用传统沉积技术沉积或形成于衬底302上。
然后，如图5B所示，光刻胶(未示出)被用于该结构上，并且阻挡层304的各部分被部分蚀刻。此蚀刻导致阻挡层304具有两个区104、204，其比阻挡层304的其余部分要更薄(即更小的厚度)。
形成阻挡层304的这些较薄部分以后，在该顶面上生成pGaN层，其被图案化和蚀刻以形成图5C中所示的增强型设备栅极103。在示例中示出的，较薄层104延伸到栅极103外面，类似于图3中例示的实施例。
然后，参考图5D，介电层107沉积在栅极103、较薄部分104、较薄部分204和阻挡层304的其余部分上。介电层107被图案化以去除源极和漏极触点的该区域(即创造触点开窗口108)。
如图5E中所示，在触点开窗口108形成以后，沉积欧姆接触层。在示例性的实施例中，接触层典型地包括Ti、Al和保护层。图5E例示了接触层被图案化和蚀刻以分别形成增强型和耗尽型设备的源极触点102、202，漏极触点105、205和场板106、206。在接触层金属的蚀刻期间，由于通过阻挡层蚀刻以将该层分成第一和第二部分，在两个设备之间可以形成隔离层301。虽然在图5E中例示的示例性方法例示了蚀刻以形成隔离层301的步骤，如上面指出的，在替代的实施例中，如本领域技术人员将理解的，隔离层301可以通过离子注入形成。
最后，如图5F所示，该结构被图案化和蚀刻以在耗尽型设备的介电薄膜107中形成开口。肖特基金属被沉积到此开口中并抬高以形成耗尽型设备的栅极203。
上面的说明和附图仅仅考虑为例示具体实施例，其实现了本文中描述的特征和优点。可以对具体的工艺条件进行修改和替代。因此，本发明的实施例不能考虑为被前述说明和附图限制。

Claims (17)

1.一种集成电路，包括：
衬底；
至少一个缓冲层，形成于所述衬底上；
GaN沟道层，形成于所述至少一个缓冲层上；
阻挡层，形成于所述GaN沟道层上；以及
隔离区，其将第一晶体管设备的所述阻挡层的第一部分与第二晶体管设备的所述阻挡层的第二部分隔离开，所述阻挡层的所述第一部分和所述第二部分的每个都具有各自的栅极接触凹陷；
第一栅极触点，至少部分沉积在所述第一晶体管设备的所述阻挡层的所述第一部分的所述栅极接触凹陷中；以及
第二栅极触点，至少部分沉积在所述第二晶体管设备的所述阻挡层的所述第二部分的所述栅极接触凹陷中。
2.根据权利要求1所述的集成电路，其中所述第一栅极触点延长了所述第一晶体管设备的所述阻挡层的所述第一部分的所述栅极接触凹陷的整个宽度。
3.根据权利要求1所述的集成电路，其中所述第二栅极触点延长了所述第二晶体管设备的所述阻挡层的所述第二部分的所述栅极接触凹陷的整个宽度。
4.根据权利要求1所述的集成电路，进一步包括：
所述阻挡层的所述第一部分上的第一源极和漏极触点；和
所述阻挡层的所述第二部分上的第二源极和漏极触点。
5.根据权利要求4所述的集成电路，进一步包括介电层，其沉积在所述第一栅极触点和所述第二栅极触点和所述阻挡层的所述第一部分和所述第二部分上。
6.根据权利要求5所述的集成电路，进一步包括第一场板和第二场板，其沉积在所述阻挡层的所述第一部分和所述第二部分上。
7.根据权利要求6所述的集成电路，其中所述第一晶体管设备是增强型设备并且所述第二晶体管设备是耗尽型设备。
8.根据权利要求7所述的集成电路，其中所述增强型设备的阈值电压的绝对值近似等于所述耗尽型设备的阈值电压的绝对值。
9.根据权利要求7所述的集成电路，其中所述第一栅极触点延长了所述第一晶体管设备的所述阻挡层的所述第一部分的所述栅极接触凹陷的整个宽度，并且其中所述第二栅极触点延长了所述第二晶体管设备的所述阻挡层的所述第二部分的所述栅极接触凹陷的整个宽度。
10.根据权利要求7所述的集成电路，其中各自的所述栅极接触凹陷的每个都包括未被各自的所述第一栅极触点和所述第二栅极触点覆盖的部分。
11.根据权利要求1所述的集成电路，其中所述阻挡层具有第一厚度并且所述阻挡层的所述栅极接触凹陷具有小于所述第一厚度的第二厚度。
12.一种制造集成电路的方法，所述方法包括：
在衬底层上形成至少一个缓冲层；
在所述至少一个缓冲层上形成阻挡层；
在所述阻挡层上形成光刻胶；
蚀刻所述阻挡层以形成第一栅极接触凹陷和第二栅极接触凹陷；
在所述第一栅极接触凹陷和所述第二栅极接触凹陷的一个中形成第一栅极触点；
在所述阻挡层上沉积介电层；
蚀刻所述介电层和所述阻挡层以在所述介电层中形成多个接触开口；以及
在所述第一栅极接触凹陷和所述第二栅极接触凹陷之间的所述阻挡层中形成隔离区。
13.根据权利要求12所述的方法，进一步包括：
蚀刻所述第一栅极接触凹陷和所述第二栅极接触凹陷的一者上的所述介电层；以及
沉积肖特基金属以在所述第一栅极接触凹陷和所述第二栅极接触凹陷的另一者中形成第二栅极触点。
14.根据权利要求13所述的方法，进一步包括在多个所述接触开口中沉积欧姆接触层，以形成第一晶体管设备和第二晶体管设备的各自的源极和漏极触点。
15.根据权利要求14所述的方法，其中所述第一晶体管设备是增强型设备并且所述第二晶体管设备是耗尽型设备。
16.根据权利要求15所述的方法，其中蚀刻所述阻挡层以形成第一栅极接触凹陷和第二栅极接触凹陷的所述步骤包括形成具有一厚度的第一栅极接触凹陷和第二栅极接触凹陷的每一者，使得所述增强型设备的阈值电压的绝对值近似等于所述耗尽型设备的阈值电压的绝对值。
17.根据权利要求16所述的方法，其中在所述第一栅极接触凹陷和所述第二栅极接触凹陷的一者中形成所述第一栅极触点的所述步骤包括仅部分地在所述栅极接触凹陷中形成所述第一栅极触点。
CN201480043093.4A 2013-07-30 2014-07-30 具有匹配阈值电压的集成电路及其制造方法 Active CN105453273B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361859803P 2013-07-30 2013-07-30
US61/859,803 2013-07-30
PCT/US2014/048828 WO2015017513A2 (en) 2013-07-30 2014-07-30 Integrated circuit with matching threshold voltages and method for making same

Publications (2)

Publication Number Publication Date
CN105453273A true CN105453273A (zh) 2016-03-30
CN105453273B CN105453273B (zh) 2018-11-02

Family

ID=52426842

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480043093.4A Active CN105453273B (zh) 2013-07-30 2014-07-30 具有匹配阈值电压的集成电路及其制造方法

Country Status (7)

Country Link
US (2) US9214399B2 (zh)
JP (1) JP6835581B2 (zh)
KR (1) KR102249390B1 (zh)
CN (1) CN105453273B (zh)
DE (1) DE112014003545T5 (zh)
TW (1) TWI615977B (zh)
WO (1) WO2015017513A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110429028A (zh) * 2019-08-01 2019-11-08 福建省福联集成电路有限公司 一种晶体管器件增强型和耗尽型栅极集成制作方法及器件

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171911B2 (en) * 2013-07-08 2015-10-27 Efficient Power Conversion Corporation Isolation structure in gallium nitride devices and integrated circuits
WO2016157718A1 (ja) * 2015-04-02 2016-10-06 パナソニック株式会社 窒化物半導体装置
FR3051072B1 (fr) 2016-05-04 2018-06-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif electronique de puissance a structure d'interconnexion electrique plane
DE102016123934A1 (de) * 2016-12-09 2018-06-14 United Monolithic Semiconductors Gmbh Verfahren zur Herstellung eines Transistors
TWI660465B (zh) 2017-07-28 2019-05-21 新唐科技股份有限公司 半導體元件及其製造方法
WO2024092544A1 (en) * 2022-11-02 2024-05-10 Innoscience (Zhuhai) Technology Co., Ltd. Nitride-based semiconductor device and method for manufacturing thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514605A (en) * 1994-08-24 1996-05-07 Nec Corporation Fabrication process for compound semiconductor device
US20110309372A1 (en) * 2010-06-21 2011-12-22 Velox Semiconductor Corporation Enhancement-mode hfet circuit arrangement having high power and a high threshold voltage
US20120091513A1 (en) * 2009-05-19 2012-04-19 Murata Manufacturing Co., Ltd. Semiconductor switch device and method of manufacturing semiconductor switch device

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3476841D1 (en) * 1983-11-29 1989-03-30 Fujitsu Ltd Compound semiconductor device and method of producing it
JP2658171B2 (ja) * 1988-05-12 1997-09-30 富士通株式会社 電界効果トランジスタの製造方法
US5100831A (en) * 1990-02-16 1992-03-31 Sumitomo Electric Industries, Ltd. Method for fabricating semiconductor device
EP0690506B1 (fr) * 1994-06-29 1999-09-08 Laboratoires D'electronique Philips S.A.S. Procédé de réalisation d'un dispositif semiconducteur comprenant au moins deux transistors à effet de champ ayant des tensions de pincement différentes
JPH11204496A (ja) * 1998-01-19 1999-07-30 Toshiba Corp エッチング方法及び成膜方法
JP4186032B2 (ja) * 2000-06-29 2008-11-26 日本電気株式会社 半導体装置
US6703638B2 (en) * 2001-05-21 2004-03-09 Tyco Electronics Corporation Enhancement and depletion-mode phemt device having two ingap etch-stop layers
US6563197B1 (en) * 2001-11-20 2003-05-13 International Rectifier Corporation MOSgated device termination with guard rings under field plate
US7449728B2 (en) * 2003-11-24 2008-11-11 Tri Quint Semiconductor, Inc. Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
JP4230370B2 (ja) * 2004-01-16 2009-02-25 ユーディナデバイス株式会社 半導体装置及びその製造方法
US7550783B2 (en) * 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
JP2007005406A (ja) * 2005-06-21 2007-01-11 Matsushita Electric Ind Co Ltd ヘテロ接合バイポーラトランジスタ及び製造方法
JP2008010468A (ja) * 2006-06-27 2008-01-17 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7973304B2 (en) * 2007-02-06 2011-07-05 International Rectifier Corporation III-nitride semiconductor device
JP5512287B2 (ja) 2007-02-22 2014-06-04 フォルシュングスフェアブント ベルリン エー ファウ 半導体素子およびその製造方法
JP5431652B2 (ja) * 2007-04-02 2014-03-05 ルネサスエレクトロニクス株式会社 半導体装置
JP2008263146A (ja) * 2007-04-13 2008-10-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20100006895A1 (en) * 2008-01-10 2010-01-14 Jianjun Cao Iii-nitride semiconductor device
JP2009224605A (ja) * 2008-03-17 2009-10-01 Panasonic Corp 半導体装置およびその製造方法
JP5520073B2 (ja) * 2010-02-09 2014-06-11 ルネサスエレクトロニクス株式会社 半導体装置
US20110248283A1 (en) * 2010-04-07 2011-10-13 Jianjun Cao Via structure of a semiconductor device and method for fabricating the same
US9076853B2 (en) * 2011-03-18 2015-07-07 International Rectifie Corporation High voltage rectifier and switching circuits
US9024357B2 (en) * 2011-04-15 2015-05-05 Stmicroelectronics S.R.L. Method for manufacturing a HEMT transistor and corresponding HEMT transistor
TWI508281B (zh) * 2011-08-01 2015-11-11 Murata Manufacturing Co Field effect transistor
JP2013077635A (ja) * 2011-09-29 2013-04-25 Sumitomo Electric Ind Ltd 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514605A (en) * 1994-08-24 1996-05-07 Nec Corporation Fabrication process for compound semiconductor device
US20120091513A1 (en) * 2009-05-19 2012-04-19 Murata Manufacturing Co., Ltd. Semiconductor switch device and method of manufacturing semiconductor switch device
US20110309372A1 (en) * 2010-06-21 2011-12-22 Velox Semiconductor Corporation Enhancement-mode hfet circuit arrangement having high power and a high threshold voltage

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110429028A (zh) * 2019-08-01 2019-11-08 福建省福联集成电路有限公司 一种晶体管器件增强型和耗尽型栅极集成制作方法及器件
CN110429028B (zh) * 2019-08-01 2021-11-19 福建省福联集成电路有限公司 一种晶体管器件增强型和耗尽型栅极集成制作方法及器件

Also Published As

Publication number Publication date
KR20160038035A (ko) 2016-04-06
US9583480B2 (en) 2017-02-28
US20150034962A1 (en) 2015-02-05
JP2016529712A (ja) 2016-09-23
KR102249390B1 (ko) 2021-05-10
US20160111416A1 (en) 2016-04-21
DE112014003545T5 (de) 2016-05-04
US9214399B2 (en) 2015-12-15
JP6835581B2 (ja) 2021-02-24
WO2015017513A2 (en) 2015-02-05
TW201513364A (zh) 2015-04-01
TWI615977B (zh) 2018-02-21
CN105453273B (zh) 2018-11-02
WO2015017513A3 (en) 2015-11-05

Similar Documents

Publication Publication Date Title
CN105453273A (zh) 具有匹配阈值电压的集成电路及其制造方法
JP5652880B2 (ja) Ｈｅｍｔ装置及びその製造方法
TWI499054B (zh) 補償式閘極金屬絕緣體半導體場效電晶體及其製造方法
US8900939B2 (en) Transistor with enhanced channel charge inducing material layer and threshold voltage control
US7763910B2 (en) Semiconductor device and manufacturing method
US10475913B2 (en) Epitaxial structure of N-face AlGaN/GaN, active device, and method for fabricating the same with integration and polarity inversion
Wei et al. Enhancement-mode GaN double-channel MOS-HEMT with low on-resistance and robust gate recess
US20150255547A1 (en) III-Nitride High Electron Mobility Transistor Structures and Methods for Fabrication of Same
CN104332498A (zh) 一种斜场板功率器件及斜场板功率器件的制备方法
US20190296139A1 (en) Transistor and Method for Manufacturing the Same
CN105453216A (zh) 用于增强模式氮化镓晶体管的具有自对准凸出部的栅极
US11538908B2 (en) Semiconductor device
WO2020107754A1 (zh) 一种提高GaN增强型MOSFET阈值电压的外延层结构及器件制备
JP2023040154A (ja) 半導体装置
US8946778B2 (en) Active area shaping of III-nitride devices utilizing steps of source-side and drain-side field plates
US10283598B2 (en) III-V heterojunction field effect transistor
US10312095B1 (en) Recessed solid state apparatuses
US9214528B2 (en) Method to fabricate self-aligned isolation in gallium nitride devices and integrated circuits
JP7308593B2 (ja) 窒化物半導体装置
US9318592B2 (en) Active area shaping of III-nitride devices utilizing a source-side field plate and a wider drain-side field plate
TWI538208B (zh) 用於氮化鎵電晶體之離子植入及自行對準閘極結構
US20220140096A1 (en) Transistor devices and methods of forming transistor devices

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant