CN105428245B - 像素结构及其制备方法、阵列基板和显示装置 - Google Patents
像素结构及其制备方法、阵列基板和显示装置 Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 79
- 239000002184 metal Substances 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 62
- 238000005516 engineering process Methods 0.000 claims abstract description 28
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 53
- 239000010409 thin film Substances 0.000 claims description 27
- 239000010408 film Substances 0.000 claims description 24
- 238000002161 passivation Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 15
- 239000007769 metal material Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 12
- 210000001624 hip Anatomy 0.000 claims description 12
- 239000012528 membrane Substances 0.000 claims description 6
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 13
- 238000000059 patterning Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000011161 development Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical class [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 description 1
- 230000002968 anti-fracture Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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Abstract
本发明属于显示技术领域,涉及像素结构及其制备方法、阵列基板和显示装置。该像素结构的制备方法包括形成绝缘层以及形成嵌于所述绝缘层的内部的金属层的步骤,包括:形成透明介质层,并采用背曝光工艺和剥离工艺对所述透明介质层进行处理,形成包括所述绝缘层的图形以及嵌于所述绝缘层的内部的所述金属层的图形;所述绝缘层中开设有用于嵌入所述金属层的槽孔,所述槽孔的形状与所述金属层的形状相适,且所述槽孔的面积等于所述金属层的面积、所述槽孔的深度等于所述金属层的厚度。该像素结构的制备方法结合了背曝光工艺和剥离工艺,能有效避免形成绝缘层以及形成嵌于绝缘层的内部的金属层时二者之间的段差,而且工艺简单,能有效提高生产效率。
Description
技术领域
本发明属于显示技术领域,具体涉及一种像素结构及其制备方法、阵列基板和显示装置。
背景技术
随着显示技术的发展,液晶显示装置(Liquid Crystal Display,简称LCD)和OLED显示装置(Organic Light Emission Display,即有机电致发光)成为目前的主流显示装置。液晶显示装置是目前平板显示装置中应用最广泛的一种,其主要构成部件是液晶面板,液晶面板主要包括彩膜基板、阵列基板以及设置于二者之间的液晶。
阵列基板是LCD显示装置中的重要部分,其中包括薄膜晶体管(Thin FilmTransistor,简称TFT)以及与薄膜晶体管相连的像素电极,通过控制薄膜晶体管的开闭来控制像素电极产生相应的电场,从而实现对液晶的驱动控制,实现图像显示。事实上,薄膜晶体管也是OLED显示装置中重要的控制元件。
如图1所示,薄膜晶体管通常包括依次设置的栅极4、栅极绝缘层2、有源层6、源极7A和漏极7B等层结构。在薄膜晶体管的制备过程中,由于栅极4的厚度(通常为左右)的原因,在栅极绝缘层2沉积在栅极4之上的时候,栅极4与栅极绝缘层2搭接处形成相对段差,使得栅极绝缘层2容易发生断裂,从而导致栅极4暴露造成不良。针对上述问题,目前常用的解决方式是,增加栅极绝缘层2的厚度预防断裂,但这种方式并不能从根本上解决上述问题,而且还可能造成工艺时间增长、进一步引发后续工艺问题的风险。
可见,提供一种制备工艺简单、结构可靠的像素结构成为目前显示领域亟待解决的技术问题。
发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不足,提供一种像素结构及其制备方法、阵列基板和显示装置,该像素结构的制备方法结合了背曝光工艺和剥离工艺,能有效避免形成绝缘层以及形成嵌于所述绝缘层的内部的金属层时二者之间的段差,而且工艺简单,能有效提高生产效率。
解决本发明技术问题所采用的技术方案是该像素结构的制备方法,包括形成绝缘层以及形成嵌于所述绝缘层的内部的金属层的步骤,包括:形成透明介质层,并采用背曝光工艺和剥离工艺对所述透明介质层进行处理,形成包括所述绝缘层的图形以及嵌于所述绝缘层的内部的所述金属层的图形;
其中,所述绝缘层中开设有用于嵌入所述金属层的槽孔,所述槽孔的形状与所述金属层的形状相适,且所述槽孔的面积等于所述金属层的面积、所述槽孔的深度等于所述金属层的厚度。
优选的是,所述透明介质层为光刻胶层,所述像素结构的制备方法具体包括步骤:
依次形成绝缘薄膜层和所述光刻胶层;
采用背曝光工艺去除所述光刻胶层对应着形成所述金属层的区域部分的光刻胶材料,形成介质沟槽;
采用刻蚀工艺去除所述绝缘薄膜层对应着所述介质沟槽区域的绝缘材料,形成包括所述槽孔的所述绝缘层的图形,所述槽孔用于容置所述金属层;
在所述光刻胶层远离所述绝缘薄膜层的一侧形成金属薄膜层;
以及,采用剥离工艺去除所述光刻胶层以及与其接触的所述金属材料,保留所述槽孔以内的金属材料,形成嵌于所述绝缘层中的所述金属层。
优选的是,在背曝光工艺中,所述绝缘薄膜层相对所述光刻胶层更靠近曝光光源;
以及,对于形成的所述介质沟槽,在垂直于所述绝缘层所在平面的方向,所述介质沟槽的截面形状为相对边不等长的四边形形状;且,在平行于所述绝缘层所在平面的方向,所述介质沟槽靠近所述绝缘层的面积大于其远离所述绝缘层的面积,所述介质沟槽远离所述绝缘层的面积大于等于所述金属层的面积。
优选的是,在垂直于所述绝缘层所在平面的方向,所述介质沟槽的截面形状为梯形形状,其中:
在背曝光工艺中,采用普通掩模板,所述介质沟槽的截面形状形成两腰为直线的梯形形状;
或者,在背曝光工艺中,采用半透膜掩模板,所述介质沟槽的截面形状形成两腰为外凸的弧线的梯形形状。
优选的是,所述曝光光源的中心对应着将形成所述介质沟槽的中心,在垂直于所述绝缘层所在平面的方向,所述介质沟槽的截面形状为两腰为直线的等腰梯形形状或两腰为外凸的弧线的等腰梯形形状。
优选的是,所述像素结构包括底栅型薄膜晶体管,其中,所述绝缘层为栅极绝缘层,所述金属层为栅极层,所述栅极绝缘层的上方还依次设置有源层以及源漏极层。
优选的是,所述栅极绝缘层与所述有源层之间还设置有辅助栅极绝缘层,所述辅助栅极绝缘层采用与所述栅极绝缘层相同的材料形成、且完全覆盖于所述栅极绝缘层以及所述栅极层的上方。
优选的是,所述像素结构包括薄膜晶体管以及位于所述薄膜晶体管下方的像素电极和钝化层,其中,所述绝缘层为所述钝化层,所述金属层为所述像素电极层。
优选的是,所述像素结构设置于基板的上方,所述基板为透明板状结构。
一种像素结构,包括绝缘层以及嵌于所述绝缘层的内部的金属层,所述绝缘层中开设有用于嵌入所述金属层的槽孔,所述槽孔的形状与所述金属层的形状相适,且所述槽孔的面积等于所述金属层的面积、所述槽孔的深度等于所述金属层的厚度。
优选的是,所述像素结构包括底栅型薄膜晶体管,其中,所述绝缘层为栅极绝缘层,所述金属层为栅极层,所述栅极绝缘层的上方还依次设置有源层以及源漏极层。
优选的是,所述栅极绝缘层与所述有源层之间还设置有辅助栅极绝缘层,所述辅助栅极绝缘层采用与所述栅极绝缘层相同的材料形成、且完全覆盖所述栅极绝缘层以及所述栅极层的上方。
优选的是,所述像素结构包括薄膜晶体管以及位于所述薄膜晶体管下方的像素电极和钝化层,其中,所述绝缘层为所述钝化层,所述金属层为所述像素电极层。
优选的是,所述像素结构设置于基板的上方,所述基板为透明板状结构。
一种阵列基板,包括上述的像素结构。
一种显示装置,包括上述的阵列基板。
本发明的有益效果是:
该像素结构的制备方法中,不需要增加额外的掩模板和构图工艺,通过采用背曝光工艺实现了绝缘层以及形成嵌于所述绝缘层的内部的金属层的制备,有效解决了栅极绝缘层在沉积在栅极上时易发生断裂的问题,避免了栅极绝缘层断裂的风险,该像素结构的制备方法简单易行,制程简单,具有普及性,易运用于实际生产之中,实现规模化生产;
同时,通过形成具有截面形状为倒梯形形状的介质沟槽的光刻胶层的技术,并配合剥离工艺,使得栅极层不需要进行曝光、显影和刻蚀工艺就可以形成图形,减少了工艺步骤,节约了成本,提高了生产效率。
附图说明
图1为现有技术中像素结构的结构示意图;
图2为本发明实施例1中像素结构的结构示意图;
图3为本发明实施例1中像素结构的流程示意图;
图4A至图4G为形成图2中像素结构的制备流程对应的结构示意图,其中:
图4A为形成绝缘薄膜层和光刻胶层的结构示意图;
图4B为在图4A的基础上进行背曝光工艺的示意图;
图4C为在图4B的基础上形成包括介质沟槽的光刻胶层的结构示意图;
图4D为在图4C的基础上形成包括槽孔的绝缘层的结构示意图;
图4E为在图4D的基础上形成金属薄膜层的结构示意图;
图4F为在图4E的基础上形成包括栅极的结构示意图;
图4G为在图4F的基础上最终形成的像素结构的结构示意图;
图5A为本发明实施例2中进行背曝光工艺的示意图;
图5B为在图5A的基础上形成包括介质沟槽的光刻胶层的结构示意图;
图中:
1-基板;2-栅极绝缘层;20-栅极绝缘薄膜层;21-槽孔;3-光刻胶层;31-介质沟槽;4-栅极;40-栅极金属薄膜层;5-辅助栅极绝缘层;6-有源层;7A-源极;7B-漏极;8-钝化层;9-像素电极。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明像素结构及其制备方法、阵列基板和显示装置作进一步详细描述。
本发明的技术构思在于:发明人经过对曝光工艺形成的众多产品的性能分析发现,在曝光工艺中,由于光的散射作用,在作为光刻介质的光刻胶层中,经曝光步骤和显影步骤形成的光刻胶开口,在靠近光源的一侧的光刻胶的开口面积比远离光源的另一侧的开口面积要大,从而造成光刻胶在相对于光线透射方向上光刻胶开口形成长短边的问题。
本发明中,将在像素结构中需通过两次独立的构图工艺来形成、且可能形成段差的两个层结构,利用上述曝光工艺形成光刻胶开口为长短边的现象,将其中的一个层结构嵌入在利用具有长短边的光刻胶开口遮挡之下的层结构中,这样,仅需通过曝光工艺和剥离工艺的结合就能形成两个层结构,从而相对现有技术中像素结构的制备工艺节省一次构图工艺。
实施例1:
本实施例提供一种像素结构及其相应的制备方法,该制备方法简单,制备得到的像素结构良率高、性能好。
一种像素结构的制备方法,包括形成绝缘层以及形成嵌于绝缘层的内部的金属层的步骤,包括:形成透明介质层,并采用背曝光工艺和剥离工艺对透明介质层进行处理,形成包括绝缘层的图形以及嵌于绝缘层的内部的金属层的图形;其中,绝缘层中开设有用于嵌入金属层的槽孔,槽孔的形状与金属层的形状相适,且槽孔的面积等于金属层的面积、槽孔的深度等于金属层的厚度。
与上述制备方法相应的一种像素结构,包括绝缘层以及嵌于绝缘层的内部的金属层,绝缘层中开设有用于嵌入金属层的槽孔,槽孔的形状与金属层的形状相适,且槽孔的面积等于金属层的面积、槽孔的深度等于金属层的厚度。
在本实施例中,像素结构包括底栅型薄膜晶体管,其中,绝缘层为栅极绝缘层,金属层为栅极层,栅极绝缘层的上方还依次设置有源层以及源漏极层。像素结构设置于基板的上方,基板为透明板状结构,一般情况下基板1优选采用玻璃基板。
如图2所示,薄膜晶体管包括栅极4、栅极绝缘层2、有源层6、辅助栅极绝缘层5、源极7A和漏极7B;在上述薄膜晶体管的基础上,还包括钝化层8、像素电极9,从而形成像素结构。以下将以形成底栅型薄膜晶体管中的栅极绝缘层和嵌入栅极绝缘层中的栅极作为示例详细说明制备过程。
优选的是,透明介质层为光刻胶层。如图3所示,该像素结构的制备方法具体包括步骤:
步骤S1):依次形成绝缘薄膜层和光刻胶层。
在该步骤中,如图4A所示,在基板1上方,通过沉积后涂覆方式分别依次形成绝缘薄膜层和光刻胶层3。这里的绝缘薄膜层为栅极绝缘薄膜层20,通常情况下采用硅氧化物、硅氮化物、铪氧化物、硅氮氧化物、铝氧化物形成;光刻胶层3相对栅极绝缘薄膜层20更远离基板1。
该像素结构设置于基板的上方,基板1为透明板状结构,一般情况下基板1优选采用玻璃基板。
步骤S2):采用背曝光工艺去除光刻胶层对应着形成金属层的区域部分的光刻胶材料,形成介质沟槽。
在该步骤中,在背曝光工艺中,绝缘薄膜层相对光刻胶层3更靠近曝光光源进行曝光,以及对曝光后的光刻胶层3进行显影形成介质沟槽31。对于形成的介质沟槽31,在垂直于绝缘层所在平面的方向,介质沟槽31的截面形状为相对边不等长的四边形形状;且,在平行于绝缘层所在平面的方向,介质沟槽31靠近绝缘层的面积大于其远离绝缘层的面积,介质沟槽31远离绝缘层的面积大于等于金属层的面积。也即,此时的介质沟槽31形成如图4C所示的上小下大的截面形状。
在垂直于绝缘层所在平面的方向,介质沟槽31的截面形状为梯形形状,在背曝光工艺中,采用普通掩模板,介质沟槽31的截面形状可以形成两腰为直线的梯形形状。进一步优选的是,曝光光源的中心对应着将形成介质沟槽31的中心,介质沟槽31为截面形状为两腰为直线的等腰梯形形状。
为了实现背曝光工艺,这里先将完成步骤S1)之后的基板1翻转,如图4B所示,使得基板1和绝缘薄膜层相对光刻胶层3更靠近曝光光源。此时,由于曝光时掩模板透光区域的中心光照最强,而在透光区域由中心向边缘逐步过渡的区域光强越来越弱,因此光刻胶层3接收到的光照如图4B所示的类似圆台体形状;在经过进一步的显影工艺以后,光刻胶层3边缘将会形成等腰梯形的形状,将图4B翻转,如图4C所示。
步骤S3):采用刻蚀工艺去除绝缘薄膜层对应着介质沟槽区域的绝缘材料,形成包括槽孔的绝缘层的图形,槽孔用于容置金属层。
在该步骤中,如图4D所示,针对绝缘材料的性质采用相应的刻蚀方式(比如对于栅极绝绝缘薄膜层采用干刻工艺)进行刻蚀,透过介质沟槽31的区域,在绝缘薄膜层中形成用于容置金属层的槽孔21,由于槽孔21旁光刻胶层3的阻挡作用,槽孔21内刻蚀主要以物理轰击作用为主,从而保证槽孔21基本可以保持矩形截面形状。
步骤S4):在光刻胶层远离绝缘薄膜层的一侧形成金属薄膜层。
在该步骤中,如图4E所示,通过溅射在形成有介质沟槽31的光刻胶层3上方形成金属薄膜层。这里具体为沉积栅极金属薄膜层40,在重力作用下,由于位于其下方的光刻胶层3存在介质沟槽31的原因,栅极金属薄膜层40在沉积过程中将发生断裂现象,一部分位于光刻胶层3的上方,一部分落入介质沟槽31且置入栅极绝缘层2内的槽孔21,且槽孔21内的栅极金属薄膜将与其余部分分离,最终形成栅极4。
步骤S5):采用剥离工艺去除光刻胶层以及与其接触的金属材料,保留槽孔以内的金属材料,形成嵌于绝缘层中的金属层。
在步骤S4)中实际上已经形成了栅极4的图形,在该步骤中,仅需对光刻胶层3以及位于其上的金属材料进行剥离工艺即可,而不需要进行栅极金属薄膜层40的曝光、显影和刻蚀工艺,最终形成如图4F所示的栅极4置入栅极绝缘层2的图形,大大提高了生产效率。
可知,由于光刻胶层3相对于形成栅极金属薄膜层40,具有倒梯形的介质沟槽31,从而可以在进行栅极绝缘薄膜层20的刻蚀工艺后先不进行光刻胶去除而直接沉积栅极金属薄膜层40;由于介质沟槽31的存在,沉积的栅极金属材料将可以埋入栅极绝缘层2中的槽孔21内,实现栅极绝缘层2包裹栅极金属材料的目的,无需进行对栅极金属薄膜层40的曝光、显影和刻蚀工艺,而仅需要进行光刻胶材料的剥离工艺即可实现多余栅极金属材料的去除,极大简化了工艺。
这里应该理解的是,参考图4E,由于光刻胶层3中介质沟槽31的截面形状为梯形形状,因此在栅极金属材料沉积至光刻胶层3上方之后,介质沟槽31内的栅极金属材料和介质沟槽31侧壁的光刻胶材料存在一定的间隙(如图4E中的距离A),因此,在剥离工艺中表面需去除的栅极金属材料和光刻胶材料不会连接在一起,从而达到彻底地、同步去除的目的。
步骤S6)接着继续进行薄膜晶体管中后续层结构的制备。
在本实施例的薄膜晶体管中,栅极绝缘层2与有源层6之间还设置有辅助栅极绝缘层5,辅助栅极绝缘层5采用与栅极绝缘层2相同的材料形成、且完全覆盖栅极绝缘层2以及栅极4的上方,从而获得更佳的栅极绝缘效果,保证栅极4相对有源层6、源极7A和漏极7B的独立性。
图4E所示为一种较理想的沉积效果,图4E中形成栅极4的栅极金属薄膜正好完全位于槽孔21内而在介质沟槽31内无多余堆积。这里应该理解的是,在设置辅助栅极绝缘层5后,即使由于工艺控制的参数设置不精细而导致出现栅极金属薄膜除了在位于槽孔21内沉积、还在介质沟槽31内出现多余堆积的情况,只要保证辅助栅极绝缘层5完全覆盖在栅极4的上方,即可通过辅助栅极绝缘层5彻底保证栅极4相对有源层6、源极7A和漏极7B的独立性,从而低了对沉积工艺的要求。
此时,辅助栅极绝缘层5的构图工艺仅需包括成膜工艺即可,并不涉及其他工艺步骤,因此基本不会增加工艺难度。进一步的,若对薄膜晶体管的厚度有限定,则可以只对辅助栅极绝缘层5的厚度进行减薄,而保持栅极绝缘层2的厚度不变。这样,就不需要为了获得较轻薄的阵列基板厚度而减小栅极绝缘层厚度,避免为减小栅极绝缘层整体层可能增加断裂的危险系数,而出现背景技术部分采用的刻意增加栅极绝缘层2的厚度的方式,保证了实现薄型显示面板的可能。
容易理解的是,本实施例的像素结构的制备方法,还包括形成有源层6、源极7A和漏极7B等的步骤;以及,在薄膜晶体管的上方形成钝化层8、像素电极9等的步骤,这里不再详述。最终形成的像素结构如图4G所示。
本实施例的像素结构的制备方法中,通过对透明介质也即光刻胶材料进行背曝光工艺,使得光刻胶层3形成截面形状为倒梯形的结构,进而在进行栅极金属薄膜层40沉积后,只需要进行剥离(Strip)工艺就可以把不需要的槽孔21以外的栅极金属材料和光刻胶材料一起去除,而不需要额外增加形成栅极4的图形的构图工艺的一系列曝光、显影和刻蚀工艺,极大地简化了像素结构的制备工艺。
若采用现有的半导体制备工艺,虽然同样能实现将栅极4内嵌于栅极绝缘层2中的效果,但是,根据目前的半导体制备工艺,将栅极4嵌于栅极绝缘层2内部需采用两次构图工艺,其中一次构图工艺实现包括槽孔21的栅极绝缘层2的图形的制备,另一次构图工艺实现栅极4的图形的制备,不仅会加大成本,同时也使得工艺越加复杂,得不偿失。
本实施例的像素结构及其相应的像素结构的制备方法中,仅需采用一次构图工艺即可将栅极嵌入到栅极绝缘层中,不仅能减小薄膜晶体管中栅极造成的段差,在减小段差的同时避免了栅极绝缘层在与栅极搭接处易发生断裂的风险,更好地保护栅极4;并且,节省了栅极金属材料刻蚀的工艺,工艺简单,减少了成本,提高了效率,还提高了形成的像素结构的良率。
实施例2:
本实施例提供一种像素结构及其相应的制备方法,该制备方法简单,制备得到的像素结构良率高、性能好。
本实施例同样以形成底栅型薄膜晶体管中的栅极绝缘层2和嵌入栅极绝缘层2中的栅极4作为示例详细说明制备过程。与实施例1相比,该像素结构的制备方法的不同点在于,在形成光刻胶层3的介质沟槽31时,在背曝光工艺中,采用半透膜掩模板,形成两腰为外凸的弧线的梯形形状。
进一步优选的是,曝光光源的中心对应着将形成介质沟槽31的中心,介质沟槽31的截面形状为两腰为外凸的弧线的等腰梯形形状。
本实施例中像素结构的制备方法在进行背曝光工艺时,采用的掩模板为如图5A所示半透膜掩模板,即将在实施例1中普通掩模板的全透膜的边缘位置处采用半透膜来替代,从而可以保证光刻胶层3形成的介质沟槽31的倒梯形截面形状的边缘不再是尖锐的直线线条,而是得到如图5B所示的保持比较陡的坡度的弧形线条,在不会影响到栅极4的图形的形成过程的前提下,可以有效避免光刻胶层3在介质沟槽31开口处发生坍塌的风险。
本实施例的像素结构及其相应的像素结构的制备方法中,仅需采用一次构图工艺即可将栅极嵌入到栅极绝缘层中,不仅能减小薄膜晶体管中栅极造成的段差,而且能有效解决栅极绝缘层易发生断裂的问题,工艺简单,形成的像素结构良率高。
实施例3:
本实施例提供一种像素结构及其相应的制备方法,该制备方法简单,制备得到的像素结构良率高、性能好。
与实施例1、2相比,该像素结构的制备方法的不同点在于,本实施例以形成底栅型薄膜晶体管下方的钝化层8和嵌入钝化层8中的像素电极9作为示例详细说明制备过程。
本实施例的像素结构中,像素结构包括薄膜晶体管以及位于薄膜晶体管下方的像素电极9和钝化层8。这里,绝缘层为钝化层8,金属层为像素电极9层。根据光直线传播的原理,为保证背曝光工艺的有效性,此时先制备形成钝化层8以及像素电极9,然后再在像素电极9的上方制备形成薄膜晶体管,即:采用该像素结构的制备方法先制备得到钝化层8、像素电极9,钝化层8、像素电极9位于薄膜晶体管的下方。
通过实施例1、2与实施例3可见,本发明中的像素结构的制备方法中,其中对于绝缘层以及嵌于绝缘层的内部的金属层,既可以为栅极绝缘层2以及栅极4的组合,同样也可以为钝化层8与像素电极9的组合。容易理解的是,只要能保证透过透明基板进行背曝光以及剥离工艺的条件,本发明的像素结构的制备方法还可以应用到类似上述两种结构组合以外的半导体器件的层结构制备中,这里不做限定。
实施例1-3的像素结构的制备方法中,不需要增加额外的掩模板和构图工艺,通过采用背曝光工艺实现了栅极嵌于栅极绝缘层、像素电极嵌于钝化层的目的,有效解决了栅极绝缘层在沉积在栅极上时易发生断裂的问题,避免了栅极绝缘层断裂的风险,该像素结构的制备方法简单易行,制程简单,具有普及性,易运用于实际生产之中,实现规模化生产;
同时,通过形成具有截面形状为倒梯形形状的介质沟槽的光刻胶层的技术,并配合剥离工艺,使得栅极层不需要进行曝光、显影和刻蚀工艺就可以形成图形,减少了工艺步骤,节约了成本,提高了生产效率。
实施例4:
本实施例提供一种阵列基板,该阵列基板包括实施例1-3任一项的像素结构。
该阵列基板包括多个成矩阵排列的像素结构。通过采用上述的包括背曝光工艺的像素结构的制备方法制备形成像素结构,该阵列基板具有更简单的制备工艺,具有更高的产品良率,
实施例5:
本实施例提供一种显示装置,该显示装置采用实施例4的阵列基板。
显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
该显示装置具有更佳的显示效果,产品寿命更长。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (13)
1.一种像素结构的制备方法,其特征在于,包括形成绝缘层以及形成嵌于所述绝缘层的内部的金属层的步骤,包括:形成透明介质层,并采用背曝光工艺和剥离工艺对所述透明介质层进行处理,形成包括所述绝缘层的图形以及嵌于所述绝缘层的内部的所述金属层的图形;
其中,所述绝缘层中开设有用于嵌入所述金属层的槽孔,所述槽孔的形状与所述金属层的形状相适,且所述槽孔的面积等于所述金属层的面积、所述槽孔的深度等于所述金属层的厚度;
其中,所述透明介质层为光刻胶层,所述绝缘层和所述金属层的制备方法包括步骤:
依次形成绝缘薄膜层和所述光刻胶层;
采用背曝光工艺去除所述光刻胶层对应着形成所述金属层的区域部分的光刻胶材料,形成介质沟槽;
采用刻蚀工艺去除所述绝缘薄膜层对应着所述介质沟槽区域的绝缘材料,形成包括所述槽孔的所述绝缘层的图形,所述槽孔用于容置所述金属层;
在所述光刻胶层远离所述绝缘薄膜层的一侧形成金属薄膜层;
以及,采用剥离工艺去除所述光刻胶层以及与其接触的金属材料,保留所述槽孔以内的金属材料,形成嵌于所述绝缘层中的所述金属层。
2.根据权利要求1所述的像素结构的制备方法,其特征在于,在背曝光工艺中,所述绝缘薄膜层相对所述光刻胶层更靠近曝光光源;
以及,对于形成的所述介质沟槽,在垂直于所述绝缘层所在平面的方向,所述介质沟槽的截面形状为相对边不等长的四边形形状;且,在平行于所述绝缘层所在平面的方向,所述介质沟槽靠近所述绝缘层的面积大于其远离所述绝缘层的面积,所述介质沟槽远离所述绝缘层的面积大于等于所述金属层的面积。
3.根据权利要求2所述的像素结构的制备方法,其特征在于,在垂直于所述绝缘层所在平面的方向,所述介质沟槽的截面形状为梯形形状,其中:
在背曝光工艺中,采用普通掩模板,所述介质沟槽的截面形状形成两腰为直线的梯形形状;
或者,在背曝光工艺中,采用半透膜掩模板,所述介质沟槽的截面形状形成两腰为外凸的弧线的梯形形状。
4.根据权利要求2所述的像素结构的制备方法,其特征在于,所述曝光光源的中心对应着将形成所述介质沟槽的中心,在垂直于所述绝缘层所在平面的方向,所述介质沟槽的截面形状为两腰为直线的等腰梯形形状或两腰为外凸的弧线的等腰梯形形状。
5.根据权利要求1所述的像素结构的制备方法,其特征在于,所述像素结构包括底栅型薄膜晶体管,其中,所述绝缘层为栅极绝缘层,所述金属层为栅极层,所述栅极绝缘层的上方还依次设置有源层以及源漏极层。
6.根据权利要求5所述的像素结构的制备方法,其特征在于,所述栅极绝缘层与所述有源层之间还设置有辅助栅极绝缘层,所述辅助栅极绝缘层采用与所述栅极绝缘层相同的材料形成、且完全覆盖于所述栅极绝缘层以及所述栅极层的上方。
7.根据权利要求1所述的像素结构的制备方法,其特征在于,所述像素结构包括薄膜晶体管以及位于所述薄膜晶体管下方的像素电极和钝化层,其中,所述绝缘层为所述钝化层,所述金属层为所述像素电极层。
8.根据权利要求1-7任一项所述的像素结构的制备方法,其特征在于,所述像素结构设置于基板的上方,所述基板为透明板状结构。
9.一种像素结构,其特征在于,包括绝缘层以及嵌于所述绝缘层的内部的金属层,所述绝缘层中开设有用于嵌入所述金属层的槽孔,所述槽孔的形状与所述金属层的形状相适,且所述槽孔的面积等于所述金属层的面积、所述槽孔的深度等于所述金属层的厚度,所述金属层由相同的材料形成;
其中,所述像素结构包括底栅型薄膜晶体管,其中,所述绝缘层为栅极绝缘层,所述金属层为栅极层,所述栅极绝缘层的上方还依次设置有源层以及源漏极层;
所述栅极绝缘层与所述有源层之间还设置有辅助栅极绝缘层,所述辅助栅极绝缘层采用与所述栅极绝缘层相同的材料形成、且完全覆盖所述栅极绝缘层以及所述栅极层的上方。
10.根据权利要求9所述的像素结构,其特征在于,所述像素结构包括薄膜晶体管以及位于所述薄膜晶体管下方的像素电极和钝化层,其中,所述绝缘层为所述钝化层,所述金属层为所述像素电极层。
11.根据权利要求9-10任一项所述的像素结构,其特征在于,所述像素结构设置于基板的上方,所述基板为透明板状结构。
12.一种阵列基板,其特征在于,包括权利要求9-11任一项所述的像素结构。
13.一种显示装置,其特征在于,包括权利要求12所述的阵列基板。
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CN109037243B (zh) * | 2018-08-01 | 2022-01-11 | 京东方科技集团股份有限公司 | 用于显示装置的基板及其制作方法、显示装置 |
CN113009733B (zh) * | 2019-12-20 | 2023-06-20 | 京东方科技集团股份有限公司 | 像素结构及其制备方法、显示装置 |
CN111785737A (zh) * | 2020-07-15 | 2020-10-16 | Tcl华星光电技术有限公司 | 阵列基板、其制作方法及显示面板 |
CN112802871B (zh) * | 2020-12-30 | 2024-08-06 | 奕瑞影像科技(太仓)有限公司 | 有机光电平板探测器 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1870216A (zh) * | 2005-05-23 | 2006-11-29 | 广辉电子股份有限公司 | 薄膜晶体管阵列衬底及其金属层的制作方法 |
WO2015016362A1 (ja) * | 2013-08-02 | 2015-02-05 | 日立化成株式会社 | 感光性樹脂組成物 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6400440B1 (en) * | 1999-06-23 | 2002-06-04 | International Business Machines Corporation | Passive liquid crystal display having pre-tilt control structure and light absorbent material at a center |
KR100892087B1 (ko) * | 2002-10-28 | 2009-04-06 | 엘지디스플레이 주식회사 | 횡전계방식 액정표시장치용 어레이기판과 그 제조방법 |
US7211881B2 (en) * | 2004-03-24 | 2007-05-01 | Hewlett-Packard Development Company, L.P. | Structure for containing desiccant |
TWI272725B (en) * | 2005-04-15 | 2007-02-01 | Quanta Display Inc | Method of fabricating TFT array substrate and metal layer thereof |
CN1933128A (zh) * | 2006-10-17 | 2007-03-21 | 友达光电股份有限公司 | 薄膜晶体管结构及液晶显示器用基板制备方法 |
US7501348B2 (en) * | 2007-04-10 | 2009-03-10 | National Chiao Tung University | Method for forming a semiconductor structure having nanometer line-width |
US20110058132A1 (en) * | 2009-09-10 | 2011-03-10 | Himax Display, Inc. | Display device and manufacturing method thereof |
JP5952998B2 (ja) * | 2010-07-26 | 2016-07-13 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
CN102645690A (zh) | 2011-05-19 | 2012-08-22 | 京东方科技集团股份有限公司 | 一种彩色滤光片及其制造方法 |
US8455312B2 (en) * | 2011-09-12 | 2013-06-04 | Cindy X. Qiu | Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits |
KR101624814B1 (ko) * | 2011-12-15 | 2016-05-26 | 인텔 코포레이션 | 단일 노광-자기 정렬된 이중, 삼중 및 사중 패터닝을 위한 방법 |
CN103811558B (zh) * | 2012-11-06 | 2018-10-30 | 北京京东方光电科技有限公司 | 一种薄膜晶体管及其制作方法、阵列基板和显示装置 |
CN104040693B (zh) * | 2012-12-04 | 2017-12-12 | 深圳市柔宇科技有限公司 | 一种金属氧化物tft器件及制造方法 |
CN103928497B (zh) * | 2014-04-01 | 2016-07-13 | 京东方科技集团股份有限公司 | Oled显示器件及其制作方法、显示装置 |
CN105428245B (zh) * | 2016-01-26 | 2019-03-01 | 京东方科技集团股份有限公司 | 像素结构及其制备方法、阵列基板和显示装置 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1870216A (zh) * | 2005-05-23 | 2006-11-29 | 广辉电子股份有限公司 | 薄膜晶体管阵列衬底及其金属层的制作方法 |
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