CN105378846B - Dram子阵列级刷新 - Google Patents

Dram子阵列级刷新 Download PDF

Info

Publication number
CN105378846B
CN105378846B CN201480038159.0A CN201480038159A CN105378846B CN 105378846 B CN105378846 B CN 105378846B CN 201480038159 A CN201480038159 A CN 201480038159A CN 105378846 B CN105378846 B CN 105378846B
Authority
CN
China
Prior art keywords
dram
refresh
row
subarray
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201480038159.0A
Other languages
English (en)
Chinese (zh)
Other versions
CN105378846A (zh
Inventor
X·董
J·徐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105378846A publication Critical patent/CN105378846A/zh
Application granted granted Critical
Publication of CN105378846B publication Critical patent/CN105378846B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
CN201480038159.0A 2013-07-05 2014-05-23 Dram子阵列级刷新 Active CN105378846B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361843110P 2013-07-05 2013-07-05
US61/843,110 2013-07-05
US14/088,098 US8982654B2 (en) 2013-07-05 2013-11-22 DRAM sub-array level refresh
US14/088,098 2013-11-22
PCT/US2014/039385 WO2015002704A1 (en) 2013-07-05 2014-05-23 Dram sub-array level refresh

Publications (2)

Publication Number Publication Date
CN105378846A CN105378846A (zh) 2016-03-02
CN105378846B true CN105378846B (zh) 2018-08-31

Family

ID=52132725

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480038159.0A Active CN105378846B (zh) 2013-07-05 2014-05-23 Dram子阵列级刷新

Country Status (6)

Country Link
US (1) US8982654B2 (https=)
EP (1) EP3017452B1 (https=)
JP (1) JP6227774B2 (https=)
KR (1) KR101799357B1 (https=)
CN (1) CN105378846B (https=)
WO (1) WO2015002704A1 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524771B2 (en) 2013-07-12 2016-12-20 Qualcomm Incorporated DRAM sub-array level autonomic refresh memory controller optimization
US9721640B2 (en) 2015-12-09 2017-08-01 Intel Corporation Performance of additional refresh operations during self-refresh mode
US9659626B1 (en) 2015-12-26 2017-05-23 Intel Corporation Memory refresh operation with page open
US9514800B1 (en) * 2016-03-26 2016-12-06 Bo Liu DRAM and self-refresh method
US9824742B1 (en) 2016-04-28 2017-11-21 Qualcomm Incorporated DRAM access in self-refresh state
CN110556139B (zh) * 2018-05-31 2021-06-18 联发科技股份有限公司 用以控制存储器的电路及相关的方法
US10535393B1 (en) * 2018-07-21 2020-01-14 Advanced Micro Devices, Inc. Configuring dynamic random access memory refreshes for systems having multiple ranks of memory
US10991414B2 (en) * 2019-04-12 2021-04-27 Western Digital Technologies, Inc. Granular refresh rate control for memory devices based on bit position
US10991413B2 (en) * 2019-07-03 2021-04-27 Micron Technology, Inc. Memory with programmable die refresh stagger
US20210064368A1 (en) * 2019-08-28 2021-03-04 Micron Technology, Inc. Command tracking
CN111158585B (zh) * 2019-11-27 2023-08-01 核芯互联科技(青岛)有限公司 一种内存控制器刷新优化方法、装置、设备和存储介质
US11139016B1 (en) * 2020-04-07 2021-10-05 Micron Technology, Inc. Read refresh operation
US20250140300A1 (en) * 2022-02-04 2025-05-01 Google Llc Traffic Aware Adaptive Precharge Scheduler For Efficient Refresh Management In Dram Memory Controllers
KR20240067516A (ko) * 2022-11-09 2024-05-17 삼성전자주식회사 메모리 장치 및 그의 동작 방법
US12406716B2 (en) 2023-12-05 2025-09-02 Nxp Usa, Inc. Refresh operations in embedded dynamic random access memories (DRAMs)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102656638A (zh) * 2009-12-16 2012-09-05 美光科技公司 用于减小半导体存储器装置中阵列干扰的影响的技术

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344157A (en) * 1978-06-26 1982-08-10 Texas Instruments Incorporated On-chip refresh address generator for dynamic memory
US5313428A (en) * 1987-11-12 1994-05-17 Sharp Kabushiki Kaisha Field memory self-refreshing device utilizing a refresh clock signal selected from two separate clock signals
US5307320A (en) 1992-09-23 1994-04-26 Intel Corporation High integration DRAM controller
KR950014089B1 (ko) * 1993-11-08 1995-11-21 현대전자산업주식회사 동기식 디램의 히든 셀프 리프레쉬 방법 및 장치
JPH09306165A (ja) * 1996-05-16 1997-11-28 Hitachi Commun Syst Inc Ｄｒａｍリフレッシュ制御回路
US5818777A (en) * 1997-03-07 1998-10-06 Micron Technology, Inc. Circuit for implementing and method for initiating a self-refresh mode
US6697909B1 (en) 2000-09-12 2004-02-24 International Business Machines Corporation Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory
JP2002216473A (ja) * 2001-01-16 2002-08-02 Matsushita Electric Ind Co Ltd 半導体メモリ装置
US6560155B1 (en) * 2001-10-24 2003-05-06 Micron Technology, Inc. System and method for power saving memory refresh for dynamic random access memory devices after an extended interval
US6721224B2 (en) * 2002-08-26 2004-04-13 Mosel Vitelic, Inc. Memory refresh methods and circuits
US7088632B2 (en) 2004-05-26 2006-08-08 Freescale Semiconductor, Inc. Automatic hidden refresh in a dram and method therefor
JP2006107245A (ja) * 2004-10-07 2006-04-20 Canon Inc メモリコントローラ
US7313047B2 (en) 2006-02-23 2007-12-25 Hynix Semiconductor Inc. Dynamic semiconductor memory with improved refresh mechanism
JP4117323B2 (ja) * 2006-04-18 2008-07-16 エルピーダメモリ株式会社 半導体記憶装置
JP5428687B2 (ja) * 2009-09-14 2014-02-26 株式会社リコー メモリ制御装置
JP2011192343A (ja) * 2010-03-12 2011-09-29 Elpida Memory Inc 半導体装置及びそのリフレッシュ制御方法並びにコンピュータシステム
KR101861647B1 (ko) * 2011-05-24 2018-05-28 삼성전자주식회사 메모리 시스템 및 그 리프레시 제어 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102656638A (zh) * 2009-12-16 2012-09-05 美光科技公司 用于减小半导体存储器装置中阵列干扰的影响的技术

Also Published As

Publication number Publication date
CN105378846A (zh) 2016-03-02
US8982654B2 (en) 2015-03-17
KR20160030212A (ko) 2016-03-16
US20150009769A1 (en) 2015-01-08
JP2016526749A (ja) 2016-09-05
EP3017452B1 (en) 2017-08-16
JP6227774B2 (ja) 2017-11-08
KR101799357B1 (ko) 2017-11-20
EP3017452A1 (en) 2016-05-11
WO2015002704A1 (en) 2015-01-08

Similar Documents

Publication Publication Date Title
CN105378846B (zh) Dram子阵列级刷新
CN105378847B (zh) Dram子阵列级自动刷新存储器控制器优化
KR102435915B1 (ko) 사용자 정의 동작 및 관련 방법 및 시스템을 갖는 반도체 디바이스
US20250272190A1 (en) Semiconductor device with modified access and associated methods and systems
US9490001B2 (en) Semiconductor memory device that controls refresh period, memory system and operating method thereof
KR20220041948A (ko) 수정된 명령과 관련 방법 및 시스템을 갖는 반도체 디바이스
CN104505117B (zh) 一种动态存储器刷新方法与刷新控制器
CN114388024B (zh) 具有经改进命令/地址总线利用的存储器
US20240127901A1 (en) Temperature-based error masking during mbist operation
Ahn et al. Adaptive self refresh scheme for battery operated high-density mobile DRAM applications
CN114121098B (zh) 用于存储器装置的行清除特征及相关联方法及系统
KR100429348B1 (ko) 용이하게 특성을 평가할 수 있는 반도체 기억 장치
US7752410B1 (en) System and method for accessing data in a multicycle operations cache
Lee et al. 15.4 A 16nm 168Mb Embedded STT-MRAM with 0.0249 µm 2 Bit-Cell, Dual-Port Access, and 51.2 Gb/s Read Throughput for Automotive and Edge AI Applications
CN120032677A (zh) 存储装置及其操作方法
TW201331951A (zh) 具有可重組態解碼之具能量效率記憶體

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant