CN105374777A - 倒装芯片封装件及其制造方法 - Google Patents
倒装芯片封装件及其制造方法 Download PDFInfo
- Publication number
- CN105374777A CN105374777A CN201510232774.1A CN201510232774A CN105374777A CN 105374777 A CN105374777 A CN 105374777A CN 201510232774 A CN201510232774 A CN 201510232774A CN 105374777 A CN105374777 A CN 105374777A
- Authority
- CN
- China
- Prior art keywords
- substrate
- pad
- bottom filling
- inner layers
- flip chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 229910000679 solder Inorganic materials 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims description 75
- 238000000034 method Methods 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 description 7
- 239000000945 filler Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract
公开了一种倒装芯片封装件及其制造方法。根据本发明的实施例的倒装芯片封装件包括:基板;多个焊盘,形成在基板上;阻焊剂,按照暴露焊盘的方式覆盖基板;芯片,按照使芯片与焊盘电连接的方式安装在基板上;多个凸块,按照使凸块置于焊盘与芯片之间的方式分别形成在所述多个焊盘上;底部填料,在基板与芯片之间流动并填充在基板与芯片之间;开口,按照在所述多个凸块之间提供底部填料的流动空间的方式位于多个凸块之间。
Description
本申请要求于2014年8月20日在韩国知识产权局提交的第10-2014-0108376号韩国专利申请的权益,该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本发明涉及一种倒装芯片封装件及制造该倒装芯片封装件的方法。
背景技术
随着对移动电子产品的需求急剧增加,安装在电子产品中的组件需要越来越小并且越来越轻。对于半导体封装件中更小并且更轻的组件已经使用倒装芯片工艺。
在倒装芯片工艺中,填充剂置于半导体芯片与基板之间。填充剂减小半导体芯片与基板之间的热膨胀系数的差异并保护焊料凸块,从而增强半导体封装件的可靠性。
当使用填充剂填充时,基板上的半导体芯片的高度越低并且焊料凸块之间的间隙越窄,填充剂流动的越不均匀,从而可能造成在填充剂中捕获有空气的空隙。
在第10-2013-0058401号韩国专利公开(半导体封装件(ASEMICONDUCTORPACKAGE);于2013年6月4日公开)中披露了本发明的相关技术。
发明内容
本发明提供一种可防止底部填充空隙的倒装芯片封装件及其制造方法。
本发明的一方面提供一种可通过去除多个凸块之间的阻焊剂使底部填料在多个凸块之间更快地流动的倒装芯片封装件。
所述倒装芯片封装件可包括基板、多个焊盘、阻焊剂、安装在基板上的芯片、凸块以及填充在基板与芯片之间的底部填料,阻焊剂可包括按照在多个凸块之间提供底部填料的流动空间的方式的开口。
在开口内可形成内部材料层,底部填料对内部材料层的润湿性可比底部填料对阻焊剂的润湿性大。内部材料层可由金属制成,并可形成为与焊盘分开。内部材料层可形成为与用于使至少两个焊盘彼此连接的连接部分开。内部材料层可通过阻焊剂覆盖,然后通过开口暴露。
开口可沿着底部填料的流动方向延伸,并可按照间断的形式形成。开口的一端可延伸到基板的分配有底部填料的区域,开口的另一端可延伸到芯片的外部区域。
本发明的另一方面提供一种制造倒装芯片封装件的方法,所述方法可通过去除多个凸块之间的阻焊剂来增大底部填料在多个凸块之间的流动速度。
制造倒装芯片封装件的方法可包括:在基板上形成多个焊盘;形成阻焊剂;去除阻焊剂的多个部分以暴露焊盘;形成开口;安装芯片;以及用底部填料填充。
形成焊盘的步骤可包括按照使内部材料层布置在多个焊盘之间的方式在基板上形成内部材料层,阻焊剂可覆盖焊盘和内部材料层,内部材料层可通过开口暴露,底部填料对内部材料层的润湿性可比底部填料对阻焊剂的润湿性大。
附图说明
图1是示出根据本发明的实施例的倒装芯片封装件的俯视图。
图2是根据本发明的实施例的沿着A-A'截面示出的倒装芯片封装件的剖视图。
图3示出了常见的在凸块之间流动的底部填料。
图4是示出根据本发明的另一实施例的倒装芯片封装件的俯视图。
图5是根据本发明的另一实施例的沿着B-B'截面示出的倒装芯片封装件的剖视图。
图6是示出根据本发明的实施例的制造倒装芯片封装件的方法的流程图。
图7、图8、图9、图10、图11和图12示出了根据本发明的实施例的制造倒装芯片封装件的方法的各个步骤。
图13是示出根据本发明的另一实施例的制造倒装芯片封装件的方法的流程图。
图14、图15、图16、图17和图18示出了根据本发明的另一实施例的制造倒装芯片封装件的方法的各个步骤。
具体实施方式
在下文中,将参照附图详细地描述根据本发明的倒装芯片封装件及其制造方法的特定实施例。在参照附图描述本发明时,将为任何同样的或对应的元件指定相同的标号,并且将不提供对同样的元件或对应的元件的冗余描述。
诸如“第一”和“第二”的术语可以仅用于将一个元件与另一个同样的或对应的元件区分开,而上述元件不应该受上述术语的限制。
当一个元件被描述为“结合到”另一元件时,它不仅仅指这些元件之间的物理的、直接的接触,而且还应该包括将另一元件置于这些元件之间并且这些元件中的每个与所述另一元件接触的可能性。
图1是示出根据本发明的实施例的倒装芯片封装件的俯视图。图2是根据本发明的实施例的沿着A-A′截面示出的倒装芯片封装件的剖视图。图3示出了常见的在凸块之间流动的底部填料。
参照图1和图2,根据本发明的实施例的倒装芯片封装件可包括基板110、焊盘120、阻焊剂130、芯片140、凸块150和底部填料160,阻焊剂130可包括开口A。
基板110是在它的上表面上形成有电路的电路板,基板110可以以多层形成。
焊盘120按照这样的方式形成在基板110上:焊盘120与所述电路电连接,以与芯片140接触。焊盘120可设置成多个,多个焊盘120可布置在纵向和横向两个方向上。
至少两个焊盘120可通过连接部121连接。在多个焊盘120之中,至少两个具有相同功能的焊盘120可通过置于两个焊盘120之间的连接部121彼此电连接。
阻焊剂130是保护电路的抗蚀剂。虽然阻焊剂130保护电路,但阻焊剂130按照暴露焊盘120的方式形成在基板110上。换言之,阻焊剂130覆盖基板110的除了焊盘120之外的整个上表面。
安装在基板110上的芯片140可包括半导体芯片。芯片140具有形成在其上的用于与芯片140的电路连接的芯片焊盘,芯片焊盘与基板110的焊盘120接触,用于芯片140与基板110之间的电连接。
凸块150是连接基板110的焊盘120与芯片焊盘的连接器,并且置于基板110的焊盘120与芯片140之间。凸块150可设置成多个,多个凸块150可分别形成在多个焊盘120上。凸块150可以是焊料。
底部填料160是填充在基板110与芯片140之间的填充剂。底部填料160(其可以是环氧树脂)流进基板110与芯片140之间,以填充在基板110与芯片140之间。
底部填料160被分配到基板110的一侧,然后底部填料160流到基板110的另一侧。分配有底部填料160的区域可以是芯片140的外部。所分配的底部填料160在多个凸块150之间穿过以从基板110的一侧移动到基板110的另一侧。
通常,如图3所示,在多个凸块150之间穿过的底部填料160具有凹面形状,因此,底部填料160在穿过多个凸块150时减速。具体地讲,底部填料160的穿过两个凸块150之间的中间的部分的流动速度明显变慢,底部填料160的这种不均匀的流动速度会造成空隙。
再参照图1和图2,本发明的开口A是去除了阻焊剂130的位于多个凸块150之间的部分的区域。可通过开口A扩大位于多个凸块150之间的底部填料160的流动空间。
可通过下面的等式来获得使底部填料160填充所需的时间(t)。
这里,L是芯片140在底部填料160的移动方向上的长度,h是底部填料160的流动空间的高度,θ是润湿角,μ是底部填料160的粘度,ν是底部填料160的表面张力。
如上所述,在本发明中,通过开口A增大了底部填料160在多个凸块150之间流动的流动空间的高度,因此在上面的等式中,h值变大,t值变小。
底部填料160填充得越快,即底部填料160流动得越快,空隙出现的机会越小。因此,在本发明中,底部填料160在多个凸块150之间的流动速度因开口A而增大,并且底部填料160的整体流动速度变得均匀,从而减少了空隙的出现。
开口A的宽度可比多个焊盘120之间的内部距离小。如果开口A过宽,则会暴露电路。
如图2所示,开口A可沿底部填料160的流动方向延伸。此外,开口A可沿底部填料160的流动方向连续地形成。
虽然开口A形成为沿底部填料160的流动方向延伸,但底部填料160可以不是连续的。在这种情况下,开口A可通过避开连接部121来形成。此外,如果必要的话,连接部121可通过开口A暴露。
开口A的一端可延伸到分配有底部填料160的区域。在这种情况下,开口A的一端到芯片140的一侧之间的距离可以是100μm或更大。
此外,开口A的另一端可延伸至芯片140的外部区域。在这种情况下,底部填料160可均匀地填充在比芯片140的区域更大的区域中。此外,在这种情况下,从开口A的另一端到芯片140的所述一侧的距离可大于或等于从芯片140的所述一侧到芯片140的另一侧的距离。
图4是示出根据本发明的另一实施例的倒装芯片封装件的俯视图,图5是根据本发明的另一实施例的沿着B-B′截面示出的倒装芯片封装件的剖视图。
参照图4和图5,根据本发明的另一实施例的倒装芯片封装件可包括基板110、焊盘120、阻焊剂130、芯片140、凸块150和底部填料160,并且倒装芯片封装件还可包括内部材料层B。这里,已经在上面描述了基板110、焊盘120、阻焊剂130、芯片140、凸块150和底部填料160,因此在此将不进行冗余描述。
内部材料层B形成在通过将阻焊剂130的一部分去除而形成的开口A内,内部材料层B可比阻焊剂130薄。
底部填料160对内部材料层B的润湿性比底部填料160对阻焊剂130的润湿性和对基板110的润湿性大。
这里,“润湿性”指的是底部填料160的分散程度。换言之,底部填料160在内部材料层B上比在阻焊剂130或基板110上流动得好。具体地讲,在上面的等式中润湿角θ变小,使得t值更小。
因此,通过在开口A内形成内部材料层B,提供了允许底部填料160在凸块150之间流动的空间,并且由于内部材料层B,增大了底部填料160的润湿性,加快了底部填料160的流动速度,从而减少了空隙的出现。
内部材料层B可以由与焊盘120的金属相同的例如铜的金属制成。底部填料160在金属性表面上会快速流动。
开口A和内部材料层B可以沿底部填料160的流动方向延伸,并可形成为连续的或间断的。
内部材料层B可形成为与焊盘120分开。具体地讲,在内部材料层B为金属性的情况下,为了防止内部材料层B与焊盘120进行不必要的接触,内部材料层B可形成为与焊盘120分开。在这种情况下,内部材料层B可比多个焊盘120之间的内部距离窄。
内部材料层B可通过避开连接部121来形成。即,内部材料层B可形成为与焊盘120的连接部121分开。在这种情况下,内部材料层B可不连续地形成。
同时,内部材料层B可形成为与焊盘120的特定的连接部接触。即,只要内部材料层B与特定的连接部的电连接不影响焊盘120的整体的电连接,内部材料层B就可形成为与特定的连接部接触。
在内部材料层B形成为与开口A的长度对应的情况下,内部材料层B的一端可以延伸至分配有底部填料160的区域。在这种情况下,内部材料层B的一端到芯片140的一侧之间的距离可以是100μm或更大。此外,内部材料层B的另一端可延伸至芯片140的外部区域。
内部材料层B与焊盘120一起可通过阻焊剂130覆盖,然后可通过去除阻焊剂130的一部分来形成开口A而暴露。在这种情况下,由于内部材料层B与焊盘120通过同一工艺暴露,因此不需要另外的工艺使内部材料层B暴露,使得能够简化制造工艺。
图6是示出根据本发明的实施例的制造倒装芯片封装件的方法的流程图。图7、图8、图9、图10、图11和图12示出了根据本发明的实施例的制造倒装芯片封装件的方法的各个步骤。
参照图6,根据本发明的实施例的制造倒装芯片封装件的方法可包括形成焊盘(S110)、形成阻焊剂(S120)、去除阻焊剂以暴露焊盘(S130)、形成开口(S140)、安装芯片(S150)和用底部填料填充(S160)。
参照图7,在形成焊盘120的步骤(S110)中,在基板110上形成构造为用于与电路电连接的焊盘。可与电路同时地形成焊盘120。设置多个焊盘120,在对应于安装芯片140的位置处形成焊盘120。
形成焊盘120的步骤(S110)可包括形成用于使至少两个焊盘120彼此连接的连接部121。连接部121置于一个焊盘120与另一焊盘120之间以使多个焊盘120彼此电连接。
参照图8,在形成阻焊剂130的步骤(S120)中,在基板110上形成阻焊剂130以覆盖电路和焊盘120。
参照图9,在去除阻焊剂130以暴露焊盘120的步骤(S130)中,按照通过阻焊剂130覆盖电路而暴露焊盘120的方式去除阻焊剂130的一部分。
在形成开口A的步骤(S140)中,通过去除阻焊剂130的布置在多个焊盘120之间的部分来形成开口A。可在多个焊盘120之间形成开口A,可通过开口A暴露基板110。
同时,如图9所示,形成开口A的步骤(S140)可与去除阻焊剂130的一部分以暴露焊盘120的步骤同时进行。例如,可通过光刻工艺同时地去除阻焊剂130的对应于焊盘120和开口A的部分。
开口A可比多个焊盘120之间的内部距离窄。如果开口A过宽,则会暴露电路。
参照图10,在安装芯片140的步骤(S150)中,在基板上安装其上形成有多个凸块150的芯片140,多个凸块150分别地与多个焊盘120接触。基板110和芯片140通过焊盘120和凸块150彼此电连接。
参照图11和图12,在用底部填料160填充的步骤(S160)中,使底部填料160流动到多个凸块150之间,底部填料160填充在基板110与芯片140之间。这里,与没有开口时相比,可通过开口A提供允许底部填料160流动的更大的空间,因此可在多个凸块150之间提供更快流动的底部填料160。因此,底部填料160可按照均匀的速度流动,从而防止产生空隙。
用底部填料160填充的步骤(S160)可包括将底部填料160分配到基板110的一侧(见图11)以及使底部填料160流动到基板110的另一侧(见图12)。
在将底部填料160分配到基板110的一侧的步骤中,将底部填料160分配在芯片140的外部区域中。在使底部填料160流动到基板110的另一侧的步骤中,底部填料160通过毛细现象移动到基板110的另一侧。底部填料160在多个凸块150之间穿过,以填充在芯片140与基板110之间。
开口A可沿着底部填料160的流动方向延伸。可沿着底部填料160的流动方向连续地形成开口A。
虽然开口A沿着底部填料160的流动方向延伸,但是底部填料160可以不是连续的。在这种情况下,可通过避开连接部121来形成开口A。此外,如果必要的话,可通过开口A暴露连接部121。
开口A的一端可延伸至分配有底部填料160的区域。在这种情况下,开口A的所述一端到芯片140的所述一侧之间的距离可以是100μm或更大。
此外,开口A的另一端可延伸至芯片140的外部区域。在这种情况下,从开口A的所述另一端到芯片140的所述一侧的距离可大于或等于从芯片140的所述一侧到芯片140的另一侧的距离。
图13是示出根据本发明的另一实施例的制造倒装芯片封装件的方法的流程图。图14、图15、图16、图17和图18示出了根据本发明的另一实施例的制造倒装芯片封装件的方法的各个步骤。
参照图13,根据本发明的另一实施例的制造倒装芯片封装件的方法可包括形成焊盘和内部材料层(S210)、形成阻焊剂(S220)、去除阻焊剂以暴露焊盘(S230)、形成开口以暴露内部材料层(S240)、安装芯片(S250)以及用底部填料填充(S260)。
参照图14,在形成焊盘120和内部材料层B(S210)的步骤中,在基板110上形成焊盘120和内部材料层B。在本实施例中,内部材料层B可与焊盘120同时形成,并且可布置在多个焊盘120之间。上文已经描述了焊盘120和内部材料层B,因此在此将不进行冗余描述。
底部填料160对内部材料层B的润湿性比底部填料160对阻焊剂130的润湿性和对基板110的润湿性大。
内部材料层B可形成为与焊盘120分开。具体地讲,在内部材料层B是金属性的情况下,为了防止内部材料层B与焊盘120不必要的接触,内部材料层B可形成为与焊盘120分开。在这种情况下,内部材料层B可比多个焊盘120之间的内部距离窄。
可通过避开连接部121来形成内部材料层B。即,内部材料层B可形成为与焊盘120的连接部121分开。在这种情况下,内部材料层B可不连续地形成。
参照图15,在形成阻焊剂130的步骤(S220)中,在基板110上形成阻焊剂130以覆盖焊盘120和内部材料层B。阻焊剂130覆盖基板110的整个表面。
参照图16,在去除阻焊剂130以暴露焊盘120的步骤(S230)中,按照使焊盘120暴露的方式来去除阻焊剂130的对应于焊盘120的部分。这在上面已经进行了描述,因此在此将不进行冗余的描述。
在形成开口A以暴露内部材料层B的步骤(S240)中,按照使内部材料层B暴露的方式来去除阻焊剂130的一部分。形成开口A的步骤(S240)可与去除阻焊剂130以暴露焊盘120的步骤(S230)同时执行。
参照图17,在安装芯片140的步骤(S250)中,在基板110上安装其中形成有多个凸块150的芯片140。这在上面已经进行了描述,因此在此将不进行冗余的描述。
参照图18,在用底部填料160填充的步骤(S260)中,使底部填料160流动到多个凸块150之间,底部填料160填充在基板110与芯片140之间。这里,可通过开口A提供允许底部填料160流动的更大的空间,并且通过内部材料层B改善了润湿性,从而允许底部填料160更快地流动并防止产生空隙。
开口A和内部材料层B可沿着底部填料160的流动方向延伸,并可沿着底部填料160的流动方向形成为连续的或间断的。
在内部材料层B形成为对应于开口A的长度的情况下,内部材料层B的一端可延伸到分配有底部填料160的区域。在这种情况下,内部材料层B的一端到芯片140的一侧之间的距离可以是100μm或更大。此外,内部材料层B的另一端可延伸至芯片140的外部区域。
如上所述,根据本发明的特定实施例的倒装芯片封装件及其制造方法可允许底部填料在凸块之间更快地流动,从而防止产生空隙。
虽然已经描述了本发明的特定实施例,但本发明所属技术领域的普通技术人员将理解的是,在不脱离应由权利要求限定的本发明的范围和技术理念的情况下,能够对本发明进行非常多的变换和修改。还将理解的是,除了以上描述的实施例之外,许多其它的实施例也包括在本发明的权利要求中。
Claims (20)
1.一种倒装芯片封装件,包括:
基板;
多个焊盘,形成在基板上;
阻焊剂,按照使焊盘暴露的方式覆盖基板;
芯片,按照与焊盘电连接的方式安装在基板上;
多个凸块,按照使凸块置于焊盘与芯片之间的方式分别形成在所述多个焊盘上;
底部填料,在基板与芯片之间流动并填充在基板与芯片之间,
其中,阻焊剂包括按照在所述多个凸块之间提供底部填料的流动空间的方式位于所述多个凸块之间的开口。
2.根据权利要求1所述的倒装芯片封装件,所述倒装芯片封装件还包括形成在开口内的内部材料层,
其中,底部填料对内部材料层的润湿性比底部填料对阻焊剂的润湿性大。
3.根据权利要求2所述的倒装芯片封装件,其中,内部材料层由金属制成。
4.根据权利要求2所述的倒装芯片封装件,其中,内部材料层形成为与焊盘分开。
5.根据权利要求2所述的倒装芯片封装件,所述倒装芯片封装件还包括使至少两个焊盘彼此连接的连接部,
其中,内部材料层形成为与连接部分开。
6.根据权利要求2所述的倒装芯片封装件,其中,内部材料层通过阻焊剂覆盖,然后通过开口暴露。
7.根据权利要求1所述的倒装芯片封装件,其中,底部填料被分配到基板的一侧,然后流到基板的另一侧。
8.根据权利要求1所述的倒装芯片封装件,其中,开口沿着底部填料的流动方向延伸。
9.根据权利要求8所述的倒装芯片封装件,其中,开口按照间断的形式形成。
10.根据权利要求7所述的倒装芯片封装件,其中,开口的一端延伸到基板的分配有底部填料的区域。
11.根据权利要求10所述的倒装芯片封装件,其中,开口的另一端延伸到芯片的外部区域。
12.一种制造倒装芯片封装件的方法,包括:
在基板上形成多个焊盘;
在基板上形成阻焊剂以覆盖焊盘;
去除阻焊剂的多个部分以暴露焊盘;
通过去除阻焊剂的布置在多个焊盘之间的部分,形成开口;
按照使多个凸块分别与焊盘接触的方式在基板上安装形成有所述多个凸块的芯片;
通过使底部填料在所述多个凸块之间流动来利用底部填料填充基板与芯片之间的空间。
13.根据权利要求12所述的方法,其中,在基板上形成所述多个焊盘的步骤包括:按照使内部材料层布置在多个焊盘之间的方式在基板上形成内部材料层,
其中,阻焊剂覆盖焊盘和内部材料层,
其中,通过开口使内部材料层暴露,
底部填料对内部材料层的润湿性比底部填料对阻焊剂的润湿性大。
14.根据权利要求13所述的方法,其中,内部材料层由金属制成。
15.根据权利要求13所述的方法,其中,内部材料层形成为与焊盘分开。
16.根据权利要求13所述的方法,其中,在基板上形成所述多个焊盘的步骤还包括:在基板上形成用于使至少两个焊盘彼此连接的连接部,
其中,内部材料层形成为与连接部分开。
17.根据权利要求12所述的方法,其中,利用底部填料填充基板与芯片之间的空间的步骤包括:
将底部填料分配到基板的一侧;
使底部填料流动到基板的另一侧。
18.根据权利要求17所述的方法,其中,开口沿着底部填料的流动方向延伸。
19.根据权利要求18所述的方法,其中,开口的一端延伸到基板的分配有底部填料的区域。
20.根据权利要求19所述的方法,其中,开口的另一端延伸到芯片的外部区域。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116994962A (zh) * | 2023-09-25 | 2023-11-03 | 四川遂宁市利普芯微电子有限公司 | 一种芯片封装方法和封装结构 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9786517B2 (en) * | 2013-09-09 | 2017-10-10 | Intel Corporation | Ablation method and recipe for wafer level underfill material patterning and removal |
CN106783784A (zh) * | 2017-01-24 | 2017-05-31 | 东莞市阿甘半导体有限公司 | 芯片封装电极结构以及使用该电极的芯片封装结构 |
JP7086702B2 (ja) * | 2018-05-08 | 2022-06-20 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体装置 |
JP2023062213A (ja) * | 2020-03-23 | 2023-05-08 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置およびその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5903056A (en) * | 1997-04-21 | 1999-05-11 | Lucent Technologies Inc. | Conductive polymer film bonding technique |
US20040188123A1 (en) * | 2003-03-18 | 2004-09-30 | Peterson Darin L. | Microelectronic component assemblies having exposed contacts |
KR20080029261A (ko) * | 2006-09-28 | 2008-04-03 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 칩 스케일 패키지 |
CN101661890A (zh) * | 2008-08-26 | 2010-03-03 | 欣兴电子股份有限公司 | 倒装片封装方法和倒装片封装结构 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5920126A (en) * | 1997-10-02 | 1999-07-06 | Fujitsu Limited | Semiconductor device including a flip-chip substrate |
US6324069B1 (en) * | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
US7331502B2 (en) * | 2001-03-19 | 2008-02-19 | Sumitomo Bakelite Company, Ltd. | Method of manufacturing electronic part and electronic part obtained by the method |
JP2003077946A (ja) * | 2001-08-31 | 2003-03-14 | Hitachi Ltd | 半導体装置の製造方法 |
US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
JP2006216720A (ja) * | 2005-02-02 | 2006-08-17 | Sharp Corp | 半導体装置及びその製造方法 |
WO2007015683A1 (en) * | 2005-08-04 | 2007-02-08 | Infineon Technologies Ag | An integrated circuit package and a method for forming an integrated circuit package |
JP2007059767A (ja) * | 2005-08-26 | 2007-03-08 | Shinko Electric Ind Co Ltd | アンダーフィル材を用いて電子部品を搭載した基板及びその製造方法 |
US7399658B2 (en) * | 2005-10-21 | 2008-07-15 | Stats Chippac Ltd. | Pre-molded leadframe and method therefor |
US8288266B2 (en) * | 2006-08-08 | 2012-10-16 | Endicott Interconnect Technologies, Inc. | Circuitized substrate assembly |
JP5211493B2 (ja) * | 2007-01-30 | 2013-06-12 | 富士通セミコンダクター株式会社 | 配線基板及び半導体装置 |
JP2008258522A (ja) * | 2007-04-09 | 2008-10-23 | Renesas Technology Corp | 半導体装置の製造方法 |
KR101019151B1 (ko) * | 2008-06-02 | 2011-03-04 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP2010147153A (ja) * | 2008-12-17 | 2010-07-01 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
KR101450727B1 (ko) * | 2010-05-20 | 2014-10-16 | 주식회사 엘지화학 | 언더-필용 댐을 포함하는 인쇄 회로 기판 및 이의 제조 방법 |
-
2014
- 2014-08-20 KR KR1020140108376A patent/KR20160022603A/ko not_active Application Discontinuation
-
2015
- 2015-04-03 US US14/678,674 patent/US20160056119A1/en not_active Abandoned
- 2015-05-08 CN CN201510232774.1A patent/CN105374777A/zh active Pending
-
2016
- 2016-05-05 US US15/147,254 patent/US9583368B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5903056A (en) * | 1997-04-21 | 1999-05-11 | Lucent Technologies Inc. | Conductive polymer film bonding technique |
US20040188123A1 (en) * | 2003-03-18 | 2004-09-30 | Peterson Darin L. | Microelectronic component assemblies having exposed contacts |
KR20080029261A (ko) * | 2006-09-28 | 2008-04-03 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 칩 스케일 패키지 |
CN101661890A (zh) * | 2008-08-26 | 2010-03-03 | 欣兴电子股份有限公司 | 倒装片封装方法和倒装片封装结构 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116994962A (zh) * | 2023-09-25 | 2023-11-03 | 四川遂宁市利普芯微电子有限公司 | 一种芯片封装方法和封装结构 |
CN116994962B (zh) * | 2023-09-25 | 2023-11-28 | 四川遂宁市利普芯微电子有限公司 | 一种芯片封装方法和封装结构 |
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