CN113543462A - 用于芯片键合的基准标记 - Google Patents
用于芯片键合的基准标记 Download PDFInfo
- Publication number
- CN113543462A CN113543462A CN202110798175.1A CN202110798175A CN113543462A CN 113543462 A CN113543462 A CN 113543462A CN 202110798175 A CN202110798175 A CN 202110798175A CN 113543462 A CN113543462 A CN 113543462A
- Authority
- CN
- China
- Prior art keywords
- lesd
- conductive
- mounting region
- alignment mark
- fiducial alignment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000010276 construction Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000004696 Poly ether ether ketone Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920005570 flexible polymer Polymers 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920002530 polyetherether ketone Polymers 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/85132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Led Device Packages (AREA)
Abstract
本发明公开了一种用于安装发光半导体器件(200)(LESD)的柔性多层构造(100),该柔性多层构造包括具有LESD安装区域(120)的柔性介电基板(110),设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD(200)的对应的第一导电端子和第二导电端子的第一导电垫(130)和第二导电垫(140),以及用于LESD在LESD安装区域中的精确放置的第一基准对准标记(150)。第一基准对准标记设置在LESD安装区域内。
Description
本申请为申请号201680050499.4(国际申请号为PCT/US2016/049413)、国际申请日为2016年8月30日、发明名称为“用于芯片键合的基准标记”的专利申请的分案申请。
背景技术
柔性电路和柔性组件通常在电子设备诸如打印机、计算机、监视器等的各种应用中用作连接器。此类电路与以前使用的刚性电路板相比,在灵活性和空间节省方面均提供了优势。
在发光二极管(LED)附接到柔性电路和柔性组件的情况下,可利用附接技术。各种管芯附接技术已被用于例如倒装芯片管芯,包括使用焊料凸块和共熔键合进行附接,由于需要较少的附接材料(以及相应地较低的成本)和性能以及较好的可靠性,这是有吸引力的。共熔键合通常通过金和锡的金属间键合发生。然而,尽管键合工艺具有优势,但是它需要在管芯垫和附接的LED之间具有高水平的放置精度。
发明内容
本公开涉及用于安装发光半导体器件(LESD)的柔性多层构造。基准对准标记设置在柔性多层构造的LESD安装区域内。基准对准标记可设置在可耦合至LESD的端子的第一导电垫或第二导电垫的内部周边内。在一些实施方案中,基准标记在导电垫中形成沟槽并且被适配为邻近在LESD安装区域中安装的LESD的第一导电端子的侧面且沿该侧面延伸,使得当使用从第一导电端子流向第一沟槽的导电材料将第一导电端子电连接到第一导电垫时,第一沟槽足够深且足够宽,使得流动的第一导电端子的大部分至少部分地填充第一沟槽。
在一个方面,本说明涉及用于安装发光半导体器件(LESD)的柔性多层构造。这个构造包括用于安装发光半导体器件(LESD)的柔性多层构造,该柔性多层构造包括具有LESD安装区域的柔性介电基板,设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD的对应的第一导电端子和第二导电端子的第一导电垫和第二导电垫,以及用于LESD在LESD安装区域中的精确放置的第一基准对准标记。第一基准对准标记设置在LESD安装区域内。
在另一方面,本说明涉及LESD封装。LESD封装包括本文所述的柔性多层构造和安装在柔性介电基板的LESD安装区域中的LESD。该LESD具有电连接到第一导电垫的第一导电端子和电连接到第二导电垫的第二导电端子。第一基准对准标记的至少一部分在LESD封装的平面图中是可见的。
在另一方面,本说明涉及用于安装发光半导体器件(LESD)的柔性多层构造。该构造包括柔性介电基板,该柔性介电基板包括相反的顶部主表面和底部主表面以及在顶部主表面上用于接收LESD的LESD安装区域,以及设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD的对应的第一导电端子和第二导电端子的第一导电垫和第二导电垫。一个或多个沟槽在第一导电垫和任选地第二导电垫的周边的内部内形成于第一导电垫中。一个或多个沟槽中的每个被适配为邻近在LESD安装区域中安装的LESD的第一导电端子的侧面且沿该侧面延伸,使得当使用从第一导电端子流向一个或多个沟槽的导电材料时,第一导电端子电连接到第一导电垫。一个或多个沟槽足够深且足够宽,使得流动的第一导电端子的大部分至少部分地填充一个或多个沟槽。
在另外的方面,本说明涉及制造用于安装发光半导体器件(LESD)的柔性多层构造的方法。该方法包括提供具有相反的顶部主表面和底部主表面的柔性介电基板以及限定在柔性介电基板的顶部主表面上用于接收LESD的LESD安装区域。然后,该方法包括在LESD安装区域中形成对应于第一基准对准标记的图案,以及在柔性介电基板的顶部主表面上的LESD安装区域中形成用于电连接到在LESD安装区域中接收的LESD的对应的第一导电端子和第二导电端子的第一导电垫和第二导电垫。第一导电垫邻接第一基准标记的周边。然后,该方法包括移除该图案,该图案导致在第一导电垫的周边的内部内形成的第一基准对准标记。
通过阅读以下具体实施方式,这些以及各种其它特征和优点将显而易见。
附图说明
结合附图,参考以下对本公开的各种实施方案的详细说明,可更全面地理解本公开,其中:
图1为根据本说明的柔性LESD组件的示意图俯视平面图;
图2为沿线2-2截取的图1的柔性LESD组件的示意图横截面图;
图3为根据本说明的柔性LESD组件的示意图透视图;以及
图4为图3的组装的柔性LESD组件的截面部分的示意图透视图。
具体实施方式
在下面的具体实施方式中,参考了形成说明的一部分的附图,并且在附图中通过举例说明的方式示出了若干具体实施方案。应当理解,在不脱离本公开的范围或实质的情况下,可设想并进行其它实施方案。因此,以下具体实施方式不被认为具有限制意义。
除非另外指明,否则本文所使用的所有科学和技术术语具有在本领域中普遍使用的含义。本文提供的定义旨在有利于理解本文频繁使用的某些术语,并且并非旨在限制本公开的范围。
除非另外指明,否则说明书和权利要求书中所使用的表达特征尺寸、量和物理特性的所有数在所有情况下均应理解成由术语“约”修饰。因此,除非有相反的说明,否则在上述说明书和所附权利要求中列出的数值参数均为近似值,这些近似值可根据本领域的技术人员使用本文所公开的教导内容期望的特性而变化。
通过端点表述的数值范围包括该范围内所包含的所有数值(例如,1至5包括1、1.5、2、2.75、3、3.80、4和5)和该范围内的任何范围。
除非上下文另外清楚地指定,否则如本说明书和所附权利要求中使用的,单数形式“一个”、“一种”和“所述”涵盖了具有多个指代物的实施方案。
除非上下文另外清楚地指定,否则如本说明书和所附权利要求中使用的,术语“或”一般以其包括“和/或”的意义使用。
如本文所用,“具有”、“包括”、“包含”等均以其开放性意义使用,并且一般意指“包括但不限于”。应当理解,术语“基本上由…组成”、“由…组成”等等包含在“包括”等之中。
本文中使用与空间相关的术语(包括但不限于“下”、“上”、“在……下方”、“在……下面”、“在……上方”、“在……顶端”),是为了便于描述一个(或多个)元件相对于另一个元件的空间关系。除了附图中示出或本文所述的具体取向外,此类与空间相关的术语涵盖装置在使用或操作时的不同取向。例如,如果附图中描绘的对象翻转或倒转,则先前描述的在其他元件下方或下面的部分此时位于那些其他元件上方。
如本文所用,例如当元件、部件或层被描述为与另一元件、部件或层形成“一致界面”,或在“其上”、“连接到其”、“与其耦合”、“堆叠其上”或“与其接触”,则可为直接在其上、直接连接到其、直接与其耦合、直接堆叠其上或直接与其接触,或者例如居间的元件、部件或层可在特定元件、部件或层上,或连接到、耦合到或接触特定元件、部件或层。例如,当元件、部件或层被称为“直接位于”另一元件“上”、“直接连接到”另一元件、“直接与”另一元件“耦合”或“直接与”另一元件“接触”时,不存在居间的元件、部件或层。
本公开涉及柔性发光半导体器件(LESD)组件。特别是用于安装发光半导体器件(LESD)的柔性多层构造。基准对准标记设置在柔性多层构造的LESD安装区域内。基准对准标记可设置在可耦合至LESD的端子的第一导电垫或第二导电垫的内部周边内。在一些实施方案中,基准标记在导电垫中形成沟槽并且被适配为邻近在LESD安装区域中安装的LESD的第一导电端子的侧面且沿该侧面延伸,使得当使用从第一导电端子流向第一沟槽的导电材料将第一导电端子电连接到第一导电垫时,第一沟槽足够深且足够宽,使得流动的第一导电端子的大部分至少部分地填充第一沟槽。通过下文提供的示例的阐述将获得对本公开各方面的理解,然而本公开并不因此受到限制。
图1为根据本说明的柔性LESD组件100的示意图俯视平面图。图2为沿线2-2截取的图1的柔性LESD组件100的示意图横截面图。
用于安装发光半导体器件(LESD)的柔性多层构造100包括具有相反的顶部主表面112和底部主表面114的柔性介电基板110,以及在顶部主表面112上用于接收LESD 200的LESD安装区域120。LESD可包括发光二极管或激光二极管。
在许多实施方案中,柔性介电基板110由聚合物材料形成。在一些实施方案中,柔性介电基板由聚酰亚胺形成。在其它实施方案中,柔性介电基板由任何其它数量的适当柔性聚合物形成,包括但不限于聚对苯二甲酸乙二醇酯(PET)、液晶聚合物、聚碳酸酯、聚醚醚酮或热塑性聚合物。
第一导电垫130和第二导电垫140位于LESD安装区域120中或设置在LESD安装区域120中用于电连接到在LESD安装区域120中接收的LESD 200的对应的第一导电端子210和第二导电端子220。
基准对准标记150设置在LESD安装区域120内或位于LESD安装区域120内。基准对准标记150提供LESD 200在LESD安装区域120中的精确放置。柔性LESD组件100可根据需要包括两个或更多个基准对准标记150。
尽管在图1中的第一导电垫130上示出了两个基准对准标记150,应当理解一个或多个基准对准标记可设置在仅第二导电垫140上。在一些实施方案中,基准对准标记可设置在第一导电垫130和第二导电垫140两者上。
在许多实施方案中,一个或多个基准对准标记150设置在第一导电垫130的周边160的内部165和/或第二导电垫140的周边170的内部175内。在一些实施方案中,基准对准标记150设置在第一导电垫130和第二导电垫140之间。在这些实施方案中,基准对准标记150可为电绝缘的。一个或多个基准对准标记150可延伸到在第一导电垫130和/或第二导电垫140中的一个或多个凹槽中并形成该一个或多个凹槽,或者可从第一导电垫130和第二导电垫140中延伸出一个或多个突起并形成该一个或多个突起。一个或多个基准对准标记150可为独立地导电的或电绝缘的。
在其中基准对准标记在第一导电垫中形成凹槽的实施方案中,凹槽可以任意数量的方式形成。在这些实施方案中的一些中,基准对准标记在第一导电垫中通过移除导电垫中的一些形成凹槽。在其它实施方案中,基准对准标记在第一导电垫中通过在第一基准对准标记周围电镀金属形成凹槽。
在其中基准对准标记从第一导电垫形成突起的实施方案中,突起可以以任意数量的方式形成。在这些实施方案中的一些中,基准对准标记通过在第一导电垫上沉积图案从第一导电垫形成突起。在其它实施方案中,基准对准标记通过移除导电垫中的一些从第一导电垫形成突起。
在许多实施方案中,用于安装发光半导体器件(LESD)的柔性多层构造100包括两个或更多个基准对准标记150,基准对准标记150彼此间隔开并设置在LESD安装区域120内,或设置在第一导电垫130的周边160的内部165和/或第二导电垫140的周边170的内部175内。在一些实施方案中,第一基准对准标记150设置在或位于第一导电垫130的周边160的内部165内,并且第二基准对准标记150设置在或位于第二导电垫140的周边170的内部175内。
LESD封装包括本文所述的柔性多层构造100和安装在柔性介电基板110的LESD安装区域120中的LESD 200。LESD 200可包括电连接到第一导电垫130的第一导电端子210和电连接到第二导电垫140的第二导电端子220。在许多实施方案中,基准对准标记150的至少一部分在LESD封装的平面图(参见图1)中是可见的。在一些实施方案中,整个基准对准标记150在LESD封装的平面图中是可见的。
在其中LESD 200是倒装芯片型发光半导体器件的实施方案中,第一导电材料215设置在第一导电端子210与第一导电垫130之间并将第一导电端子210连接到第一导电垫130,并且第二导电材料225设置在第二导电端子220与第二导电垫140之间并将第二导电端子220连接到第二导电垫140。例如,第一导电材料215和第二导电材料225可独立地由导电膏、导电粘合剂或焊料凸块中的一种或多种形成。
在其中LESD 200是引线键合型发光半导体器件的实施方案中,第一导电线材将第一导电端子连接到第一导电垫130,并且第二导电线材将第二导电端子连接到第二导电垫140。
柔性多层构造100可另外包括在LESD安装区域120中形成的多个通孔。每个通孔在顶部主表面112和底部主表面114之间延伸并以导电材料填充以形成多个导电填充通孔135、导电填充通孔145。第一导电填充通孔135电连接到第一导电垫130。第二导电填充通孔145电连接到第二导电垫140。
图3为根据本说明的柔性LESD组件100的示意图透视图。图4为图3的组装的柔性LESD组件100的截面部分的示意图透视图。图3示出了从LESD安装区域120分解开的LESD200。
用于安装发光半导体器件(LESD)的柔性多层构造100包括具有相反的顶部主表面112和底部主表面114的柔性介电质基板110,以及在顶部主表面112上用于接收LESD 200的LESD安装区域。LESD可包括发光二极管或激光二极管。
第一导电垫130和第二导电垫140位于LESD安装区域中或设置在LESD安装区域中用于电连接到在LESD安装区域中接收的LESD 200的对应的第一导电端子210和第二导电端子220。
在这些实施方案中,基准对准标记151、153、155在第一导电垫130中形成第一沟槽并被适配为邻近在LESD安装区域中安装的LESD 200的第一导电端子210的第一例且沿该第一侧延伸,使得当使用从第一导电端子210流向第一沟槽151的导电材料将第一导电端子210电连接到第一导电垫130时,第一沟槽151足够深且足够宽,使得流动的第一导电端子的大部分至少部分地填充第一沟槽151。
类似地,基准对准标记152、154、156在第二导电垫140中形成第二沟槽并被适配为邻近在LESD安装区域中安装的LESD 200的第二导电端子220的第一例且沿该第一侧延伸,使得当使用从第二导电端子220流向第二沟槽152的导电材料将第二导电端子220电连接到第二导电垫140时,第二沟槽152足够深且足够宽,使得流动的第二导电端子的大部分至少部分地填充第二沟槽152。
一个或多个基准对准标记151、152、153、154、155、156是形成一个或多个沟槽的凹槽,使得在将LESD电连接到柔性电路的过程中,导电材料(例如:焊料)可从导电端子流走。此时,LESD可从随导电材料漂移的其原始位置移动。沿LESD的导电端子定位的沟槽的一个有用的关键效果是限制LESD的移动。
在许多实施方案中,基准对准标记包括在第一导电垫130中的两个或三个沟槽151、153、155,其被适配为邻近在LESD安装区域中安装的LESD 200的第一导电端子210的两侧或三侧并沿该两侧或三侧延伸。在一些实施方案中,每个沟槽151、153、155被适配为邻近在LESD安装区域中安装的LESD 200的第一导电端子210的不同侧并沿该不同侧延伸。如图3所示。
在许多实施方案中,基准对准标记包括在第二导电垫140中的两个或三个沟槽152、154、156,其被适配为邻近在LESD安装区域中安装的LESD 200的第二导电端子220的两侧或三侧并沿该两侧或三侧延伸。在一些实施方案中,每个沟槽152、154、156被适配为邻近在LESD安装区域中安装的LESD 200的第二导电端子220的不同侧并沿该不同侧延伸。如图3所示。
一个或多个沟槽151、153、155可在第一导电垫130的周边的内部内形成于第一导电垫130中。一个或多个沟槽151、153、155中的每个可邻近在LESD安装区域中安装的LESD200的第一导电端子210的侧面并沿该侧面延伸,使得当使用从第一导电端子130流向一个或多个沟槽151、153、155的导电材料将第一导电端子210电连接到第一导电垫130时,一个或多个沟槽151、153、155足够深且足够宽,使得流动的第一导电端子210的大部分至少部分地填充一个或多个沟槽。
相似地,一个或多个沟槽152、154、156可在第二导电垫140的周边的内部内形成于第二导电垫140中。一个或多个沟槽152、154、156中的每个可邻近在LESD安装区域中安装的LESD 200的第二导电端子220的侧面并沿该侧面延伸,使得当使用从第二导电端子140流向一个或多个沟槽152、154、156的导电材料将第二导电端子220电连接到第二导电垫140时,一个或多个沟槽152、154、156足够深且足够宽,使得流动的第二导电端子220的大部分至少部分地填充一个或多个沟槽。
在许多实施方案中,在平面图中,当第一导电端子210电连接到第一导电垫130时,每个沟槽151、153、155的至少一部分在LESD的外边界之外。在这些实施方案中的一些中,每个沟槽151、153、155在平面图中可见。在所选的实施方案中,整个沟槽151、153、155在平面图中可见。
本文所述的基准对准标记可通过任何有用的方式形成。如上所述,可随着形成导电垫移除或不设置材料以形成基准对准标记,或者可将材料添加到导电垫以形成基准对准标记。
形成用于安装发光半导体器件(LESD)的柔性多层构造的例示性方法包括提供具有相反的顶部主表面112和底部主表面114的柔性介电基板110,以及限定在柔性介电基板110的顶部主表面112上用于接收LESD 200的LESD安装区域120。
然后,在LESD安装区域中形成对应于第一基准对准标记的图案,并且在LESD安装区域中形成用于电连接到LESD 200的对应的第一导电端子210和第二导电端子220的第一导电垫130和第二导电垫140。第一导电垫130邻接第一基准标记的周边。在许多实施方案中,形成第一导电垫130和第二导电垫140的步骤包括将金属电镀到柔性介电基板110上。
然后,该方法包括移除该图案,该图案导致在第一导电垫130的周边的内部内形成的第一基准对准标记150。
因此,公开了用于芯片键合的基准标记的实施方案。
本文中所引用的所有参考文献及出版物全文以引用方式明确地并入本公开中,但它们可能与本公开直接冲突的内容除外。虽然本文已经举例说明并描述了具体实施方案,但本领域的普通技术人员将会知道,在不脱离本公开范围的情况下,可用多种替代的和/或等同形式的具体实施来代替所示出和所描述的具体实施方案。本申请旨在涵盖本文所讨论的具体实施方案的任何改型或变型。因此,本公开旨在仅受权利要求及其等同形式的限制。所公开的实施方案仅为举例说明而非限制目的而给出。
Claims (6)
1.一种用于安装发光半导体器件(LESD)的柔性多层构造,所述柔性多层构造包括:
柔性介电基板,所述柔性介电基板包括相反的顶部主表面和底部主表面以及在所述顶部主表面上用于接收LESD的LESD安装区域;
第一导电垫和第二导电垫,所述第一导电垫和所述第二导电垫设置在所述LESD安装区域中用于电连接到在所述LESD安装区域中接收的LESD的对应的第一导电端子和第二导电端子;以及
第一基准对准标记,所述第一基准对准标记用于LESD在所述LESD安装区域中的精确放置,所述第一基准对准标记设置在所述LESD安装区域内,平行于LESD的所述第一导电端子的外边缘并沿着所述第一导电端子的外边缘延伸;和第二基准对准标记,所述第二基准对准标记用于LESD在所述LESD安装区域中的精确放置,所述第二基准对准标记设置在所述LESD安装区域内,平行于LESD的所述第二导电端子的外边缘并沿着所述第二导电端子的外边缘延伸,其中,所述第一基准对准标记是第一沟槽并且所述第二基准对准标记是第二沟槽,使得在所述LESD安装区域中安装LESD时,在平面图中,所述第一沟槽和所述第二沟槽整个在所述LESD的外边界之外。
2.根据权利要求1所述的柔性多层构造,其中,所述第一基准对准标记设置在所述第一导电垫和所述第二导电垫中的一个导电垫的周边的内部内。
3.根据权利要求1所述的柔性多层构造,其中,所述第一沟槽被设置为使得当使用从所述第一导电端子流向所述第一沟槽的导电材料将所述第一导电端子电连接到所述第一导电垫时,所述第一沟槽足够深且足够宽,使得流动的所述第一导电端子的大部分至少部分地填充所述第一沟槽。
4.一种LESD封装,包括:
根据权利要求1所述的柔性多层构造;
安装在所述柔性介电基板的所述LESD安装区域中的LESD,所述LESD具有电连接到所述第一导电垫的第一导电端子和电连接到所述第二导电垫的第二导电端子。
5.一种用于安装发光半导体器件(LESD)的柔性多层构造,所述柔性多层构造包括:
柔性介电基板,所述柔性介电基板包括相反的顶部主表面和底部主表面以及在所述顶部主表面上用于接收LESD的LESD安装区域;
第一导电垫和第二导电垫,所述第一导电垫和所述第二导电垫设置在所述LESD安装区域中用于电连接到在所述LESD安装区域中接收的LESD的对应的第一导电端子和第二导电端子;以及
在所述第一导电垫的周边的内部内形成于所述第一导电垫中的一个或多个沟槽,所述一个或多个沟槽中的每个被适配为邻近在所述LESD安装区域中安装的LESD的第一导电端子的外边缘且沿所述外边缘并且平行于所述外边缘延伸,使得当使用从所述第一导电端子流向所述一个或多个沟槽的导电材料将所述第一导电端子电连接到所述第一导电垫时,所述一个或多个沟槽足够深且足够宽,使得流动的导电材料的大部分至少部分地填充所述一个或多个沟槽,使得当所述第一导电端子电连接到所述第一导电垫时,在平面图中,所述多个沟槽中的每个沟槽是可见的并且在所述LESD的外边界之外。
6.一种形成用于安装发光半导体器件(LESD)的柔性多层构造的方法,所述方法包括:
提供具有相反的顶部主表面和底部主表面的柔性介电基板;
限定在所述柔性介电基板的所述顶部主表面上用于接收LESD的LESD安装区域;
在所述LESD安装区域中形成对应于第一基准对准标记和第二基准对准标记的图案;
在所述柔性介电基板的所述顶部主表面上的所述LESD安装区域中形成用于电连接到在所述LESD安装区域中接收的LESD的对应的第一导电端子和第二导电端子的第一导电垫和第二导电垫,所述第一导电垫邻接所述第一基准对准标记的周边,所述第二导电垫邻接所述第二基准对准标记的周边;以及
移除所述图案,所述图案导致在所述第一导电垫的周边的内部内形成的第一基准对准标记并在所述第二导电垫的周边的内部内形成的第二基准对准标记,使得所述第一基准对准标记是设置为邻近并平行于所述第一导电端子的外边缘的第一沟槽,所述第二基准对准标记是设置为邻近并平行于所述第二导电端子的外边缘的第二沟槽,使得当所述第一导电端子电连接到所述第一导电垫并且所述第二导电端子电连接到所述第二导电垫时,在平面图中,所述第一沟槽和所述第二沟槽是可见的并且在所述LESD的外边界之外。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562213371P | 2015-09-02 | 2015-09-02 | |
US62/213,371 | 2015-09-02 | ||
CN201680050499.4A CN107926113A (zh) | 2015-09-02 | 2016-08-30 | 用于芯片键合的基准标记 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201680050499.4A Division CN107926113A (zh) | 2015-09-02 | 2016-08-30 | 用于芯片键合的基准标记 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113543462A true CN113543462A (zh) | 2021-10-22 |
Family
ID=56889234
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201680050499.4A Pending CN107926113A (zh) | 2015-09-02 | 2016-08-30 | 用于芯片键合的基准标记 |
CN202110798175.1A Withdrawn CN113543462A (zh) | 2015-09-02 | 2016-08-30 | 用于芯片键合的基准标记 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201680050499.4A Pending CN107926113A (zh) | 2015-09-02 | 2016-08-30 | 用于芯片键合的基准标记 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10438897B2 (zh) |
CN (2) | CN107926113A (zh) |
TW (1) | TW201724568A (zh) |
WO (1) | WO2017040482A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019003111A1 (en) * | 2017-06-29 | 2019-01-03 | 3M Innovative Properties Company | FLEXIBLE CIRCUIT WITH METAL AND METAL OXIDE LAYERS CONTAINING THE SAME METAL |
CN110881245A (zh) * | 2019-11-28 | 2020-03-13 | 深南电路股份有限公司 | 线路板及其制造方法 |
DE102021113592A1 (de) * | 2021-05-26 | 2022-12-01 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches halbleiterbauteil und paneel |
US20240063136A1 (en) * | 2022-08-19 | 2024-02-22 | Intel Corporation | Integrated circuit device with electrically active fiducials |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01283993A (ja) * | 1988-05-11 | 1989-11-15 | Hitachi Ltd | 回路プリント板、その面付け部品位置認識装置、及び面付け部品検査装置 |
US9480133B2 (en) * | 2010-01-04 | 2016-10-25 | Cooledge Lighting Inc. | Light-emitting element repair in array-based lighting devices |
JP5985846B2 (ja) * | 2011-06-29 | 2016-09-06 | Flexceed株式会社 | 発光素子搭載用基板及びledパッケージ |
US20160057855A1 (en) * | 2013-04-15 | 2016-02-25 | Heptagon Micro Optics Pte. Ltd. | Accurate Positioning and Alignment of a Component During Processes Such as Reflow Soldering |
JP6286911B2 (ja) * | 2013-07-26 | 2018-03-07 | セイコーエプソン株式会社 | 実装構造、電気光学装置及び電子機器 |
-
2016
- 2016-08-30 WO PCT/US2016/049413 patent/WO2017040482A1/en active Application Filing
- 2016-08-30 CN CN201680050499.4A patent/CN107926113A/zh active Pending
- 2016-08-30 US US15/753,426 patent/US10438897B2/en active Active
- 2016-08-30 CN CN202110798175.1A patent/CN113543462A/zh not_active Withdrawn
- 2016-09-01 TW TW105128244A patent/TW201724568A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
US20180240756A1 (en) | 2018-08-23 |
WO2017040482A1 (en) | 2017-03-09 |
US10438897B2 (en) | 2019-10-08 |
CN107926113A (zh) | 2018-04-17 |
TW201724568A (zh) | 2017-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10128214B2 (en) | Substrate and the method to fabricate thereof | |
US9559043B2 (en) | Multi-level leadframe with interconnect areas for soldering conductive bumps, multi-level package assembly and method for manufacturing the same | |
US20230207416A1 (en) | Semiconductor packages | |
CN113543462A (zh) | 用于芯片键合的基准标记 | |
US8659154B2 (en) | Semiconductor device including adhesive covered element | |
US20210202425A1 (en) | Semiconductor package using flip-chip technology | |
US10128221B2 (en) | Package assembly having interconnect for stacked electronic devices and method for manufacturing the same | |
US20150171064A1 (en) | Package assembly and method for manufacturing the same | |
EP3154084A2 (en) | Semiconductor package using flip-chip technology | |
US10014456B2 (en) | Flexible circuits with coplanar conductive features and methods of making same | |
KR102459651B1 (ko) | 발광 소자 패키지 및 이의 제조 방법 | |
US8354744B2 (en) | Stacked semiconductor package having reduced height | |
CN105489580A (zh) | 半导体衬底及半导体封装结构 | |
US20090065949A1 (en) | Semiconductor package and semiconductor module having the same | |
CN107924973B (zh) | 用于安装发光半导体器件的柔性电路 | |
US10201086B2 (en) | Electronic device | |
US20100327434A1 (en) | Semiconductor device and method of manufacturing the same | |
CN109768023B (zh) | 具有表面安装结构的扁平无引线封装体 | |
US9870977B2 (en) | Semiconductor device with heat information mark | |
KR102628100B1 (ko) | 내장된 칩을 구비하는 반도체 패키지 및 이의 제조 방법 | |
US11670574B2 (en) | Semiconductor device | |
US20230307586A1 (en) | Mounting arrangements for semiconductor packages and related methods | |
US20040245624A1 (en) | Using solder balls of multiple sizes to couple one or more semiconductor structures to an electrical device | |
CN115245056A (zh) | 印刷电路板 | |
CN117529804A (zh) | 芯片封装结构和用于制备芯片封装结构的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WW01 | Invention patent application withdrawn after publication |
Application publication date: 20211022 |
|
WW01 | Invention patent application withdrawn after publication |