CN105246249A - 电路基板及其制造方法 - Google Patents

电路基板及其制造方法 Download PDF

Info

Publication number
CN105246249A
CN105246249A CN201510353256.5A CN201510353256A CN105246249A CN 105246249 A CN105246249 A CN 105246249A CN 201510353256 A CN201510353256 A CN 201510353256A CN 105246249 A CN105246249 A CN 105246249A
Authority
CN
China
Prior art keywords
metal derby
cavity
substrate
core substrate
circuit substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510353256.5A
Other languages
English (en)
Inventor
富川满广
浅野浩二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of CN105246249A publication Critical patent/CN105246249A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本发明提供能够抑制金属块与绝缘树脂层的剥离的电路基板及其制造方法。本发明的电路基板(10)中，收容在芯基板(11)的空腔(16)内的金属块(17)中的由第一绝缘树脂层(21、21)覆盖的表面和背面这两个面(第一主面(17F)、第二主面(17S))形成粗糙面，因此，能够抑制金属块(17)与第一绝缘树脂层(21、21)的剥离，电路基板(10)中的金属块(17)的固定状态稳定。另外，金属块(17)的侧面(17A)也形成粗糙面，因此，在电路基板(10)的板厚方向上金属块(17)的固定状态也稳定。

Description

电路基板及其制造方法
技术领域
本发明涉及在具有空腔的芯基板上层叠有增层(builduplayer)的电路基板及其制造方法。
背景技术
以往，作为这种电路基板，已知有将收容在空腔内的金属块的表面和背面这两个面利用增层中含有的绝缘树脂层进行固定的电路基板(例如，参见专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2013-135168号(第[0028]～[0030]段、图3(B))
发明内容
发明所要解决的课题
但是，上述的现有电路基板中，有时绝缘树脂层会从金属块剥离而使金属块的固定强度降低。
本发明是鉴于上述情况而完成的，其目的在于提供能够抑制金属块与绝缘树脂层的剥离的电路基板及其制造方法。
解决课题的手段
用于实现上述目的的本发明第一方面所涉及的发明为一种电路基板，其具有：芯基板，贯通所述芯基板的空腔，收容在所述空腔内的金属块，层叠在所述芯基板的表面和背面且含有覆盖所述空腔的绝缘树脂层的增层，以及填充在所述空腔与所述金属块的间隙内的填充树脂；所述电路基板中，所述金属块中的由所述增层覆盖的表面和背面这两个面中与树脂连接的面形成为粗糙面。
附图说明
图1是本发明的第一实施方式所涉及的电路基板的俯视图。
图2是电路基板的制品区域的俯视图。
图3是图2的A-A切断面的电路基板的侧截面图。
图4是表示电路基板的制造工序的侧截面图。
图5是表示电路基板的制造工序的侧截面图。
图6是表示电路基板的制造工序的侧截面图。
图7是表示电路基板的制造工序的侧截面图。
图8是表示电路基板的制造工序的侧截面图
图9是表示电路基板的制造工序的侧截面图。
图10是包含电路基板的PoP的侧截面图。
图11是第二实施方式的电路基板的侧截面图。
具体实施方式
[第一实施方式]
以下，基于图1～图10对本发明的第一实施方式进行说明。如图1的俯视图所示，本实施方式的电路基板10例如具有沿着外缘部的框状的舍弃区域R1，该舍弃区域R1的内侧被划分为正方形的多个制品区域R2。图2中放大示出了一个制品区域R2，将该制品区域R2沿对角线切断而得到的电路基板10的截面结构放大示于图3。
如图3所示，电路基板10形成在芯基板11的表面和背面这两个面上具有增层20、20的结构。芯基板11由绝缘性部件构成。在芯基板11的作为表面侧的面的F面11F和芯基板11的作为背面侧的面的S面11S上分别形成有导体电路层12。另外，在芯基板11中形成有空腔16和多个导电用贯通孔14。
导电用贯通孔14从芯基板11的F面11F和S面11S这两面分别开孔，直径朝向深侧逐渐缩小，锥形孔14A、14A的小径侧端部相互连通，形成中间缩颈形状。与此相对，空腔16形成具有长方体状的空间的形状。
在各导电用贯通孔14内镀敷填充而形成多个通孔导电导体15，利用这些通孔导电导体15将F面11F的导体电路层12与S面11S的导体电路层12之间连接。
在空腔16内收容有金属块17。金属块17例如为铜制的长方体，金属块17的平面形状比空腔16的平面形状小一圈。另外，金属块17的厚度芯基板11的板厚稍大，即作为金属块17的表面和背面中的一个面的第一主面17F与作为金属块17的表面和背面中的另一个面的第二主面17S之间的距离比芯基板11的板厚稍大。并且，金属块17分别自芯基板11的F面11F和S面11S稍稍突出，金属块17的第一主面17F与芯基板11的F面11F中的导体电路层12的最外表面大致处于同一平面，另一方面，金属块17的第二主面17S与芯基板11的S面11S中的导体电路层12的最外表面大致处于同一平面。另外，在金属块17与空腔16的内表面之间的间隙内填充有本发明所涉及的填充树脂16J。
金属块17的第一主面17F和第二主面17S、以及这些第一主面17F和第二主面17S之间的4个侧面17A(即，金属块17的所有外表面)形成为粗糙面。具体而言，将金属块17在酸液(例如，以硫酸和过氧化氢作为主要成分的酸)中浸渍预定时间来浸蚀表面，由此，金属块17的表面的算术平均粗糙度Ra达到0.1[μm]～3.0[μm](根据JISB0601-1994的定义)。
芯基板11的F面11F侧的增层20和S面11S侧的增层20均从芯基板11侧依次层叠第一绝缘树脂层21、第一导体层22、第二绝缘树脂层23、第二导体层24而成，在第二导体层24上层叠有阻焊层25。另外，在第一绝缘树脂层21和第二绝缘树脂层23中分别形成有多个导通孔21H、23H，这些导通孔21H、23H均形成为直径朝向芯基板11侧逐渐缩小的圆锥状。进而，在这些导通孔21H、23H内镀敷填充而形成多个导通导体(viaconductor)21D、23D。并且，利用第一绝缘树脂层21的导通导体21D将导体电路层12与第一导体层22之间、以及金属块17与第一导体层22之间连接，利用第二绝缘树脂层23的导通导体23D将第一导体层22与第二导体层24之间连接。另外，在阻焊层25中形成有多个焊盘用孔，第二导体层24的一部分位于焊盘用孔内而形成焊盘26。
在芯基板11的F面11F上的作为增层20的最外表面的电路基板10的F面10F中，多个焊盘26由大焊盘26A组和小焊盘26C组构成，该大焊盘26A组沿着制品区域R2的外缘部以2列排列，该小焊盘26C组在由这些大焊盘26A组包围的内侧的区域内以纵横多列排列。另外，由小焊盘26C组构成本发明所涉及的电子部件安装部26J。进而，例如图2所示，在制品区域R2的对角线上排列的位于小焊盘26C组的中央的4个小焊盘26C、以及在这4个小焊盘26C的列的附近与上述对角线平行地排列的3个小焊盘26C合计这7个小焊盘26C的正下方的位置，配置有金属块17。并且，在这7个小焊盘26C中，如图3所示，例如2个小焊盘26C经由4个导通导体21D、23D与金属块17连接。与此相对，在芯基板11的S面11S上的作为增层20的最外表面的电路基板10的S面10S中，比小焊盘26C大的3个中焊盘26B构成本发明所涉及的基板连接部，并经由6个导通导体21D、23D与金属块17连接。即，本实施方式的电路基板10中，与金属块17连接的导通导体21D的数量在S面11S侧的增层20中比在芯基板11的F面11F侧的增层20中多。
本实施方式的电路基板10如下制造。
(1)如图4(A)所示，作为芯基板11，准备在由环氧树脂或BT(双马来酰亚胺三嗪)树脂和玻璃布等增强材料构成的绝缘性基材11K的表面和背面这两个面上层叠有铜箔11C的芯基板。
(2)如图4(B)所示，从F面11F侧对芯基板11照射例如CO2激光，穿出用于形成导电用贯通孔14(参见图3)的锥形孔14A。
(3)如图4(C)所示，在芯基板11的S面11S中正对着上述F面11F侧的锥形孔14A的背面位置照射CO2激光，穿出锥形孔14A，由这些锥形孔14A、14A形成导电用贯通孔14。
(4)进行化学镀处理，在铜箔11C上和导电用贯通孔14的内面形成化学镀膜(未图示)。
(5)如图4(D)所示，在铜箔11C上的化学镀膜上形成预定图案的抗镀剂33。
(6)进行电镀处理，如图5(A)所示，导电用贯通孔14内被镀敷填充而形成通孔导电导体15，同时，在铜箔11C上的化学镀膜(未图示)中的从抗镀剂33露出的部分形成电镀膜34。
(7)剥离抗镀剂33，同时将抗镀剂33下方的化学镀膜(未图示)和铜箔11C除去，如图5(B)所示，由残留的电镀膜34、化学镀膜和铜箔11C在芯基板11的F面11F上形成导体电路层12，同时在芯基板11的S面11S上形成导体电路层12。并且，形成F面11F的导体电路层12与S面11S的导体电路层12由通孔导电导体15连接的状态。
(8)如图5(C)所示，在芯基板11上利用镂铣机或CO2激光形成空腔16。
(9)如图5(D)所示，以封住空腔16的方式将由PET膜形成的胶带90粘贴在芯基板11的S面11S上。
(10)准备金属块17。金属块17通过将铜的板材或铜的方材切断而形成，在收容于耐酸性的网状结构的容器内的状态下，在储存于储存槽内的酸液(例如，以硫酸和过氧化氢作为主要成分的酸)中浸渍预定时间，然后水洗。由此，金属块17的整个表面形成为粗糙面。
(11)如图6(A)所示，利用安装器(未图示)将金属块17收纳于空腔16内。
(12)如图6(B)所示，在芯基板11的F面11F上的导体电路层12上层叠作为第一绝缘树脂层21的预浸料(对芯材进行树脂浸渗而形成的B阶段的树脂片)和铜箔37后，进行热压。此时，芯基板11的F面11F的导体电路层12、12相互之间被预浸料填埋，从预浸料渗出的热固性树脂填充到空腔16的内面与金属块17的间隙内。
(13)如图6(C)所示，除去胶带90。
(14)如图6(D)所示，在芯基板11的S面11S上的导体电路层12上层叠作为第一绝缘树脂层21的预浸料和铜箔37后，进行热压。此时，芯基板11的S面11S的导体电路层12、12相互之间被预浸料填埋，从预浸料渗出的热固性树脂填充到空腔16的内面与金属块17的间隙内。另外，有热固性树脂从芯基板11的F面11F和S面11S的预浸料渗出而填充到空腔16的内面与金属块17的间隙内，由该热固性树脂形成上述的填充树脂16J。
需要说明的是，也可以使用不含有芯材的树脂膜代替预浸料作为第一绝缘树脂层21。这种情况下，可以不层叠铜箔而利用半加成法直接在树脂膜的表面形成导体电路层。
(15)如图7(A)所示，对上述由预浸料形成的芯基板11的表面和背面这两侧的第一绝缘树脂层21、21照射CO2激光，形成多个导通孔21H。这些多个导通孔21H中的一部分导通孔21H配置在导体电路层12上，其他的一部分导通孔21H配置在金属块17上。需要说明的是，在金属块17上形成导通孔21H时，位于导通孔21H的深侧的金属块17的粗糙面的凹凸被激光照射或照射后的除胶渣处理消除也没有关系。
(16)进行化学镀处理，在第一绝缘树脂层21、21上和导通孔21H、21H内形成化学镀膜(未图示)。
(17)如图7(B)所示，在铜箔37上的化学镀膜上形成预定图案的抗镀剂40。
(18)进行电镀处理，如图7(C)所示，在导通孔21H、21H内镀敷填充而形成导通导体21D、21D，并且，在第一绝缘树脂层21、21上的化学镀膜(未图示)中的从抗镀剂40露出的部分形成电镀膜39、39。
(19)将抗镀剂40剥离，同时，将抗镀剂40下方的化学镀膜(未图示)和铜箔37除去，如图8(A)所示，由残留的电镀膜39、化学镀膜和铜箔37在芯基板11的表面和背面的各第一绝缘树脂层21上形成第一导体层22。并且，形成如下状态：芯基板11的表面和背面的各第一导体层22的一部分与导体电路层12由导通导体21D连接，同时，各第一导体层22的其他一部分与金属块17由导通导体21D连接。
(20)通过与上述的(12)～(19)同样的处理，如图8(B)所示，在芯基板11的表面和背面的各第一导体层22上形成第二绝缘树脂层23和第二导体层24，形成各第二导体层24的一部分与第一导体层22由导通导体23D连接的状态。
(21)如图8(C)所示，在芯基板11的表面和背面的各第二导体层24上层叠阻焊层25、25。
(22)如图9所示，在芯基板11的表面和背面的阻焊层25、25的预定部位形成圆锥状的焊盘用孔，芯基板11的表面和背面的各第二导体层24中的从焊盘用孔露出的部分成为焊盘26。
(23)在焊盘26上依次层叠镍层、钯层、金层，形成图3所示的金属膜41。如上完成电路基板10。
关于本实施方式的电路基板10的结构和制造方法的说明如上。接下来一同说明电路基板10的使用例和电路基板10的作用效果。本实施方式的电路基板10例如以下述方式使用。即，如图10所示，在电路基板10所具有的上述大、中、小的焊盘26A、26B、26C上形成符合这些各焊盘大小的大、中、小的焊料凸块27A、27B、27C。然后，例如，将在下表面具有与电路基板10的F面10F的小焊盘组同样配置的焊盘组的CPU80搭载于各制品区域R2的小焊料凸块27C组上并进行钎焊，形成第一封装基板10P。此时，CPU80所具有的例如接地用的2个焊盘经由导通导体21D、23D与电路基板10的金属块17连接。
接着，将在电路基板82的F面82F安装有存储器81的第二封装基板82P从CPU80的上方配置到第一封装基板10P上，在该第二封装基板82P中的电路基板82的S面82S上所具备的焊盘上钎焊第一封装基板10P中的电路基板10的大焊料凸块27A，形成PoP83(层叠封装83，PackageonPackage83)。需要说明的是，在PoP83中的电路基板10、82之间填充未图示的树脂。
接着，将PoP83配置在母板84上，在该母板84所具有的焊盘组上钎焊PoP83中的电路基板10的中焊料凸块27B。此时，母板84所具有的例如接地用的焊盘与电路基板10中的金属块17上连接的焊盘26进行钎焊。需要说明的是，在CPU80和母板84具有散热专用的焊盘的情况下，这些散热专用的焊盘与电路基板10的金属块17可以通过导通导体21D、23D进行连接。
CPU80发热时，该热量经由安装有CPU80的电路基板10的F面10F侧的增层20所含有的导通导体21D、23D传递至金属块17，并经由电路基板10的S面10S侧的增层20所含有的导通导体21D、23D从金属块17向母板84散热。在此，本实施方式的电路基板10中，与金属块17连接的导通导体21D的数量在连接有散热目的地的母板84的S面11S侧的增层20中比在安装有CPU80的F面10F侧的增层20中多，因此，金属块17中的蓄热得到抑制，能够有效地进行散热。
电路基板10随着CPU80的使用、不使用而反复发生热伸缩。并且，由于金属块17与增层20的第一绝缘树脂层21的热伸缩率的差异，在金属块17与增层20的第一绝缘树脂层21之间产生剪切力的作用，可能使导通导体21D与第一绝缘树脂层21一同从金属块17剥离。但是，本实施方式的电路基板10中，金属块17中的由第一绝缘树脂层21、21覆盖的表面和背面这两个面(第一主面17F和第二主面17S)形成为粗糙面，因此，能够抑制金属块17与第一绝缘树脂层21、21的剥离，电路基板10中的金属块17的固定状态稳定。另外，金属块17的侧面17A也形成为粗糙面，因此，在电路基板10的板厚方向上金属块17的固定状态也稳定。而且，通过使金属块17的表面为粗糙面，金属块17与第一绝缘树脂层21、21和空腔16内的填充树脂16J的接触面积增加，从金属块17向电路基板10散热的效率提高。
[第二实施方式]
本实施方式的电路基板10V示于图11。该电路基板10V中，在收容金属块17的空腔16的附近具备收容层叠陶瓷电容器30的多个空腔32。层叠陶瓷电容器30例如形成用一对电极31、31覆盖陶瓷制棱柱体的两端部的结构。另外，各层叠陶瓷电容器30与金属块17同样地自芯基板11V的F面11F和S面11S稍稍突出，层叠陶瓷电容器30的各电极31的第一平面31F与芯基板11的F面11F侧的导体电路层12的最外表面处于同一平面，同时，层叠陶瓷电容器30的各电极31的第二平面31S与芯基板11的S面11S侧的导体电路层12的最外表面处于同一平面。并且，在这些各层叠陶瓷电容器30的电极31上，连接有芯基板11的表面和背面这两面的增层20、20所含有的导通导体21D、23D。另外，制造该电路基板10V时，金属块17与层叠陶瓷电容器30通过相同的工序收容到空腔16、32内。
[其他实施方式]
本发明不限于上述实施方式，例如，以下说明的实施方式也包含在本发明的技术范围内，而且，除下述以外，实施时也可以在不脱离主旨的范围内进行各种变更。
(1)上述第一和第二实施方式的导通导体21D形成由导通导体23D连接至露出于电路基板10、10V的最外表面的焊盘26的状态，但是例如也可以为：未连接有导通导体23D、未设置有焊盘26等、导通导体21D上连接的导体未连接至露出于电路基板10、10V的最外表面的部分的状态。
(2)上述第一和第二实施方式的电路基板10、10V中，金属块17上连接的导通导体21D的数量在S面11S侧的增层20中比在芯基板11的F面11F侧的增层20中多，但也可以是F面11F侧的增层20中的导通导体21D的数量更多，或者可以为相同数量。
(3)上述第一和第二实施方式的金属块17是在将铜的板材或铜的方材切断后对表面进行粗糙化，但也可以在切断前进行粗糙化。这种情况下，金属块17的所有侧面或者侧面的一部分表面为未进行粗糙化的状态。
(4)上述第一和第二实施方式的金属块利用酸进行了表面的粗糙化，但例如也可以通过颗粒的喷吹、凹凸面的按压来进行粗糙化。
(5)上述第二实施方式中，通过与金属块17相同的工序将层叠陶瓷电容器30收容到空腔32内，但除了非层叠陶瓷电容器30的其他电子部件例如电容器、电阻、热敏电阻、线圈等无源部件以外，也可以将IC电路等有源部件等收容到空腔32内。
[符号的说明]
10、10V电路基板
11、11V芯基板
16、32空腔
16J填充树脂
17金属块
20增层
21第一绝缘树脂层(绝缘树脂层)
21D导通导体(第一导通导体、第二导通导体)
26J电子部件安装部
26B中焊盘(基板连接部)
30层叠陶瓷电容器(电子部件)

Claims (17)

1.一种电路基板，
其具有：
芯基板，
贯通所述芯基板的空腔，
收容在所述空腔内的金属块，
包含层叠在所述芯基板的表面和背面并覆盖所述空腔的绝缘树脂层的增层，以及
填充在所述空腔与所述金属块的间隙内的填充树脂；
所述电路基板中，所述金属块中的由所述增层覆盖的表面和背面这两个面中与树脂连接的面形成为粗糙面。
2.如权利要求1所述的电路基板，其中，所述金属块中的所述表面和背面这两个面之间的所有侧面中与树脂连接的面形成为粗糙面。
3.如权利要求1或2所述的电路基板，其中，所述金属块的表面和背面的粗糙面与侧面的粗糙面形成为同一连续的粗糙面。
4.如权利要求1～3中任一项所述的电路基板，其中，所述粗糙面的算术平均粗糙度为0.1μm～3.0μm。
5.如权利要求1～4中任一项所述的电路基板，其中，将所述金属块用酸浸蚀来形成所述粗糙面。
6.如权利要求1～5中任一项所述的电路基板，其具有：
贯通所述芯基板的多个所述空腔；
收容在任意所述空腔内的所述金属块；
收容在任意其他所述空腔内的电子部件；以及
填充在所述空腔与所述金属块之间的间隙内的填充树脂。
7.如权利要求1～6中任一项所述的电路基板，其具有：
用于安装电子部件的电子部件安装部，其设置于层叠在所述芯基板的表面侧的所述增层的最外部；
与其他电路基板连接的基板连接部，其设置于层叠在所述芯基板的背面侧的所述增层的最外部；
第一导通导体，其设置于所述电子部件安装部侧的最内部的所述增层，与所述金属块连接；以及
第二导通导体，其设置于所述基板连接部侧的最内部的所述增层，与所述金属块连接且数量比所述第一导通导体多。
8.如权利要求1～7中任一项所述的电路基板，其中，覆盖所述空腔的所述绝缘树脂层的一部分进入所述空腔内而形成所述填充树脂。
9.一种电路基板的制造方法，
其进行下述工序：
在芯基板内形成空腔，
在所述空腔内收容金属块，
在所述芯基板的表面和背面层叠覆盖所述空腔和所述金属块的增层，以及
将填充树脂填充到所述空腔与所述金属块的间隙内；
所述电路基板的制造方法中，对所述金属块中的由所述增层覆盖的表面和背面这两个面进行粗糙化。
10.如权利要求9所述的电路基板的制造方法，其中，对所述金属块中的所述表面和背面这两个面之间的所有侧面进行粗糙化。
11.如权利要求9或10所述的电路基板的制造方法，其中，对所述金属块中的表面和背面这两个面以及侧面同时进行粗糙化。
12.如权利要求9～11中任一项所述的电路基板的制造方法，其中，在将所述金属块收容到所述空腔内之前，对所述金属块进行粗糙化。
13.如权利要求9～12中任一项所述的电路基板的制造方法，其中，使所述粗糙面的算术平均粗糙度为0.1μm～3.0μm。
14.如权利要求9～13中任一项所述的电路基板的制造方法，其中，将所述金属块用酸浸蚀来进行所述粗糙化。
15.如权利要求9～14中任一项所述的电路基板的制造方法，其中，进行下述工序：
在所述芯基板内形成多个所述空腔；
在任意所述空腔内收容所述金属块；
在任意其他所述空腔内收容电子部件；以及
将填充树脂填充到所述空腔与所述金属块之间的间隙内。
16.如权利要求9～15中任一项所述的电路基板的制造方法，其中，进行下述工序：
在层叠于所述芯基板的表面侧的所述增层的最外部，形成用于安装电子部件的电子部件安装部；
在层叠于所述芯基板的背面侧的所述增层的最外部，形成与其他电路基板连接的基板连接部；
在所述电子部件安装部侧的最内部的所述增层，形成与所述金属块连接的第一导通导体；以及
在所述基板连接部侧的最内部的所述增层，形成与所述金属块连接且数量比所述第一导通导体多的第二导通导体。
17.如权利要求9～16中任一项所述的电路基板的制造方法，其中，使覆盖所述空腔的所述绝缘树脂层的一部分进入所述空腔内而形成所述填充树脂。
CN201510353256.5A 2014-07-03 2015-06-24 电路基板及其制造方法 Pending CN105246249A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-137450 2014-07-03
JP2014137450A JP2016015432A (ja) 2014-07-03 2014-07-03 回路基板及びその製造方法

Publications (1)

Publication Number Publication Date
CN105246249A true CN105246249A (zh) 2016-01-13

Family

ID=55018062

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510353256.5A Pending CN105246249A (zh) 2014-07-03 2015-06-24 电路基板及其制造方法

Country Status (3)

Country Link
US (1) US9872401B2 (zh)
JP (1) JP2016015432A (zh)
CN (1) CN105246249A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114271035A (zh) * 2019-09-03 2022-04-01 富士通互连技术株式会社 基板、基板的制造方法及电子设备

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102216506B1 (ko) * 2015-11-10 2021-02-17 삼성전기주식회사 방열부재 및 이를 구비한 인쇄회로기판
AU2019212513A1 (en) 2018-01-26 2020-09-03 Fluidx Medical Technology, Llc Apparatus and method of using in situ solidifying complex coacervates for vascular occlusion
US10978417B2 (en) * 2019-04-29 2021-04-13 Advanced Semiconductor Engineering, Inc. Wiring structure and method for manufacturing the same
CN110944447A (zh) * 2019-10-28 2020-03-31 汕头凯星印制板有限公司 一种金属化孔嵌入铜柱导强电线路板及其制造工艺
CN110933875A (zh) * 2019-11-18 2020-03-27 深圳崇达多层线路板有限公司 一种埋铜块pcb的制作方法
US11439018B2 (en) 2020-12-29 2022-09-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method of manufacturing the same
US11412618B2 (en) 2020-12-29 2022-08-09 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100065323A1 (en) * 2005-06-30 2010-03-18 Ibiden Co., Ltd. Printed wiring board
CN101686611A (zh) * 2008-09-28 2010-03-31 华为技术有限公司 多层电路板及其制作方法和通信设备
US20130269986A1 (en) * 2012-04-13 2013-10-17 Subtron Technology Co., Ltd. Package carrier and manufacturing method thereof
CN103841750A (zh) * 2012-11-23 2014-06-04 旭德科技股份有限公司 封装载板

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835598A (en) 1985-06-13 1989-05-30 Matsushita Electric Works, Ltd. Wiring board
SE513786C2 (sv) * 1999-03-09 2000-11-06 Ericsson Telefon Ab L M Metod för framställning av mönsterkort samt anordning för värmeavledning framställt enligt metoden
US7514637B1 (en) * 1999-08-06 2009-04-07 Ibiden Co., Ltd. Electroplating solution, method for fabricating multilayer printed wiring board using the solution, and multilayer printed wiring board
US20050067378A1 (en) 2003-09-30 2005-03-31 Harry Fuerhaupter Method for micro-roughening treatment of copper and mixed-metal circuitry
KR100751995B1 (ko) * 2006-06-30 2007-08-28 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP4525786B2 (ja) * 2008-03-31 2010-08-18 Ｔｄｋ株式会社 電子部品及び電子部品モジュール
US8525041B2 (en) 2009-02-20 2013-09-03 Ibiden Co., Ltd. Multilayer wiring board and method for manufacturing the same
KR20130014122A (ko) * 2011-07-29 2013-02-07 삼성전기주식회사 전자 소자 내장 인쇄회로기판 및 그 제조방법
DE102011112090A1 (de) * 2011-09-04 2013-03-07 Schoeller-Electronics Gmbh Verfahren zur Bestückung einer Leiterplatte
JP5987314B2 (ja) 2011-12-27 2016-09-07 イビデン株式会社 プリント配線板
JP2016015433A (ja) * 2014-07-03 2016-01-28 イビデン株式会社 回路基板及びその製造方法
JP2016025143A (ja) * 2014-07-17 2016-02-08 イビデン株式会社 回路基板及びその製造方法
JP2016149475A (ja) * 2015-02-13 2016-08-18 イビデン株式会社 回路基板及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100065323A1 (en) * 2005-06-30 2010-03-18 Ibiden Co., Ltd. Printed wiring board
CN101686611A (zh) * 2008-09-28 2010-03-31 华为技术有限公司 多层电路板及其制作方法和通信设备
US20130269986A1 (en) * 2012-04-13 2013-10-17 Subtron Technology Co., Ltd. Package carrier and manufacturing method thereof
CN103841750A (zh) * 2012-11-23 2014-06-04 旭德科技股份有限公司 封装载板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114271035A (zh) * 2019-09-03 2022-04-01 富士通互连技术株式会社 基板、基板的制造方法及电子设备

Also Published As

Publication number Publication date
US9872401B2 (en) 2018-01-16
JP2016015432A (ja) 2016-01-28
US20160007451A1 (en) 2016-01-07

Similar Documents

Publication Publication Date Title
CN105246249A (zh) 电路基板及其制造方法
US8956918B2 (en) Method of manufacturing a chip arrangement comprising disposing a metal structure over a carrier
CN104244616B (zh) 一种无芯板薄型基板的制作方法
US9698094B2 (en) Wiring board and electronic component device
TWI555451B (zh) 電路基板、電路基板的製造方法及電子機器
CN104717839B (zh) 厚铜电路板及其制作方法
CN106340461B (zh) 一种超薄无芯封装基板的加工方法和结构
US9236364B2 (en) Package carrier and manufacturing method thereof
CN103889168A (zh) 承载电路板、承载电路板的制作方法及封装结构
JP2015220281A (ja) プリント配線板
CN104701189A (zh) 三层封装基板的制作方法及三层封装基板
JP2015220282A (ja) プリント配線板
CN103681559A (zh) 芯片封装基板和结构及其制作方法
CN104241231A (zh) 芯片封装基板及其制作方法
TW201446100A (zh) 具有內埋元件的電路板及其製作方法
CN103871996A (zh) 封装结构及其制作方法
CN110621123A (zh) 一种导热pcb的制作方法及pcb
CN104299919B (zh) 无芯层封装结构及其制造方法
CN105448856A (zh) 芯片封装结构、制作方法及芯片封装基板
CN103781283A (zh) 一种电路板制作方法
CN112533381B (zh) 母板制作方法
JP2016127148A (ja) 配線基板の製造方法
CN103889169B (zh) 封装基板及其制作方法
US20140201992A1 (en) Circuit board structure having embedded electronic element and fabrication method thereof
CN103779233A (zh) 承载板的制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160113

WD01 Invention patent application deemed withdrawn after publication