CN105097997A - Preparation method of N-type silicon chip a-Si:H film for heterojunction with intrinsic thin layer (HIT) battery - Google Patents
Preparation method of N-type silicon chip a-Si:H film for heterojunction with intrinsic thin layer (HIT) battery Download PDFInfo
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- CN105097997A CN105097997A CN201510538704.9A CN201510538704A CN105097997A CN 105097997 A CN105097997 A CN 105097997A CN 201510538704 A CN201510538704 A CN 201510538704A CN 105097997 A CN105097997 A CN 105097997A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 105
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 105
- 239000010703 silicon Substances 0.000 title claims abstract description 105
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title claims abstract description 35
- 238000000151 deposition Methods 0.000 claims abstract description 35
- 230000008021 deposition Effects 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 18
- 239000007789 gas Substances 0.000 claims abstract description 17
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 12
- 238000004140 cleaning Methods 0.000 claims abstract description 11
- 238000001816 cooling Methods 0.000 claims description 8
- 238000005086 pumping Methods 0.000 claims description 8
- 238000004062 sedimentation Methods 0.000 claims description 8
- 238000005070 sampling Methods 0.000 claims description 4
- 230000007306 turnover Effects 0.000 claims description 4
- 238000007654 immersion Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 abstract description 11
- 230000007547 defect Effects 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000010792 warming Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 44
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000005215 recombination Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a preparation method of an N-type silicon chip a-Si:H film for a heterojunction with intrinsic thin layer (HIT) battery. The preparation method comprises the following steps: (1) cleaning and texturing an N-type silicon chip; (2) carrying out oxidation layer removal treatment; (3) putting the N-type silicon chip into a plasma enhanced chemical vapor deposition (PECVD) cavity, firstly extracting background vacuum, heating and warming the N-type silicon chip, extracting high vacuum, introducing deposition gases SiH4 and H2, carrying out a-Si:H film deposition on the front surface of the N-type silicon chip, and turning over the silicon chip; and (4) repeating the processes in the step (3), carrying out a-Si:H film deposition on the back surface of the N-type silicon chip, and finishing preparation of the N-type silicon chip a-Si:H film for the HIT battery. According to the preparation method, the a-Si:H film with high passivation quality and low defect density can be obtained; the surface quality of the silicon chip is greatly improved; and the efficiency of the HIT battery is effectively improved.
Description
Technical field
The present invention relates to a kind of preparation method of HIT battery N-type silicon chip a-Si:H film, be specifically related to a kind of preparation method of high passivation quality fabricating low-defect-density HIT battery N-type silicon chip a-Si:H film.
Background technology
HIT solar cell is as the one of high-efficiency battery, and it both make use of low temperature thin film depositing operation, has given play to again the advantage of crystalline silicon high mobility, and preparation technology is simple simultaneously.Wherein, HIT battery crystalline silicon features is generally N-type silicon chip, and it has, and open circuit voltage is high, conversion efficiency high.On the one hand, HIT battery is completely different with traditional crystal silicon solar battery from manufacture craft in structure, and existing technical process is substantially inapplicable on HIT battery; But then, it can ensure higher efficiency (international peak efficiency reaches 25.6%) while sheet, and application prospect is boundless, is one of Main way of following battery development.
The N-type silicon chip of phosphorus doping is the main backing material manufacturing HIT battery, and it has higher conversion efficiency for the manufacture of HIT battery.The amorphous silicon layer of intrinsic amorphous silicon layer, doping, transparent conductive film and gate electrode form double-side cell in the two sides of crystalline silicon substrate deposition respectively.It adopts high-quality and thin doped amorphous silicon layer to form heterojunction, utilizes thin intrinsic amorphous silicon layer to carry out passivation to the dangling bonds of surface of crystalline silicon simultaneously, reduces interface state defects to improve hetero-junction solar cell efficiency.This battery PN junction is to obtain by deposition a-Si:H, different from traditional diffusion, it is higher to silicon chip surface quality requirement, silicon slice surface defects density need the least possible, the deposition of silicon chip surface a-Si:H and passivation effect huge to further battery performance impact.Therefore, a kind of HIT battery N-type silicon chip a-Si:H method for manufacturing thin film of high passivation quality fabricating low-defect-density is needed.And current, the technology of preparing of HIT battery N-type silicon chip a-Si:H film lacks relatively, and existing amorphous silicon membrane deposition is mainly used for amorphous silicon battery, and its film quality is difficult to the requirement meeting HIT battery.Therefore, one of the key issue prepared by HIT battery that how to provide a kind of HIT battery N-type silicon chip a-Si:H method for manufacturing thin film of high passivation quality fabricating low-defect-density to become.
Summary of the invention
The technical problem to be solved in the present invention overcomes the deficiencies in the prior art, a kind of preparation method of HIT battery N-type silicon chip a-Si:H film is provided, this preparation method can obtain the a-Si:H film of high passivation quality and fabricating low-defect-density, increase substantially silicon chip surface quality, the basis ensureing HIT battery short circuit current stabilization promotes its open circuit voltage and fill factor, curve factor largely, thus the effective efficiency improving HIT battery.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A preparation method for HIT battery N-type silicon chip a-Si:H film, comprises the following steps:
(1) by N-type silicon chip cleaning and texturing;
(2) step (1) gained N-type silicon chip is carried out oxide layer process;
(3) step (2) gained N-type silicon chip is placed in PECVD chamber, first takes out base vacuum, then heat temperature raising, pumping high vacuum, then pass into deposition gases SiH
4with H
2, regulate deposition pressure and radio frequency power density, the front of N-type silicon chip carried out to the deposition of a-Si:H film, deposited rear cooling and by silicon chip turn-over;
(4) repeat the process of step (3), the reverse side of N-type silicon chip is carried out to the deposition of a-Si:H film, deposited rear cooling sampling, namely obtained HIT battery N-type silicon chip a-Si:H film.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (3), first take out base vacuum to below 20Pa, be then heated to 190 DEG C ~ 200 DEG C, pumping high vacuum to 5 × 10
-4below Pa.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (3), described SiH
4with H
2gas flow ratio (i.e. volume flow ratio) be 1: 5 ~ 6.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (3), described deposition pressure is 60Pa ~ 80Pa, and described radio frequency power density is 0.01W/cm
2~ 0.02W/cm
2.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (3), the sedimentation time of the front a-Si:H film of described N-type silicon chip is 10s ~ 12s, and deposit thickness is 8nm ~ 10nm.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (4), the sedimentation time of the reverse side a-Si:H film of described N-type silicon chip is 10s ~ 12s, and deposit thickness is 8nm ~ 10nm.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (1), through described N-type silicon chip cleaning and texturing, remove the surface damage layer 18 μm ~ 22 μm of N-type silicon chip, and obtained pyramid matte, pyramid Diagonal Dimension is 5 μm ~ 10 μm.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (2), described oxide layer process step (1) gained N-type silicon chip is placed in HF solution soak, and then cleans, dries up.
In the preparation method of above-mentioned HIT battery N-type silicon chip a-Si:H film, preferably, in described step (2), the volumetric concentration of described HF solution is 2% ~ 3%, and the time of described immersion is 10s ~ 20s.
Compared with prior art, the invention has the advantages that:
Preparation method of the present invention is adopted to carry out a-Si:H thin film deposition to HIT battery N-type silicon chip is two-sided, the deposit thickness preferably 8 ~ 10nm of a-Si:H, after double-sided deposition a-Si:H film, obtain the N-type silicon chip surface of high passivation quality low surface defect density, minority carrier life time can reach 483 more than μ s (body minority carrier life time <1ms), silicon chip surface recombination rate <30cm/s.When ensureing silicon chip surface passivation, effectively ensure that follow-up PN junction tunneling effect (a-Si:H layer is enough thin), effectively raise open circuit voltage and the fill factor, curve factor of battery when ensureing HIT battery short circuit current stabilization, thus effectively raise the efficiency of HIT battery.
Accompanying drawing explanation
Fig. 1 is preparation technology's flow chart of HIT battery N-type silicon chip a-Si:H film in the embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description and concrete preferred embodiment, the invention will be further described, but protection range not thereby limiting the invention.
The material adopted in following examples and instrument are commercially available.
embodiment 1:
A preparation method for HIT battery N-type silicon chip a-Si:H film of the present invention, technological process as shown in Figure 1, comprises the following steps:
(1) N-type silicon chip cleaning and texturing: the N-type silicon chip being used for HIT battery is carried out cleaning and texturing process, mainly complete silicon chip surface mechanical damage layer to remove and the preparation of pyramid matte, damaged layer on surface of silicon slice one side removes 18 μm, and pyramid Diagonal Dimension is 5 ~ 8 μm.
(2) oxide layer process (HF process): N-type silicon chip is after cleaning and texturing, and being inserted volumetric concentration is in the HF solution of 2.5%, reaction 16s, the main natural oxidizing layer removing silicon chip surface, taking-up after completing, clean with deionized water rinsing, N
2dry up.
(3) deposition of N-type silicon chip front a-Si:H film
(3.1) low vacuum is taken out in setting-out: carry out PECVD(and plasma enhanced chemical vapor deposition to step (2) gained N-type silicon chip) process, N-type silicon chip is placed in PECVD chamber, take out base vacuum, make base vacuum be reduced to below 18Pa, complete initial vacuum process.
(3.2) pumping high vacuum is heated: sample stage temperature to 200 DEG C in heating PECVD chamber, pumping high vacuum to 4.8 × 10
-4below Pa.
(3.3) deposit a-Si:H film: until temperature and vacuum degree up to standard and stable after, pass into deposition gases SiH
4with H
2, SiH
4with H
2gas flow ratio (volume flow ratio) be 1: 5, after gas flow is stable, regulate deposition pressure and radio frequency power density, gas build-up of luminance is carried out to the deposition of a-Si:H, wherein deposition pressure is 60Pa, and radio frequency power density is 0.01W/cm
2, sedimentation time is 10s, obtains a-Si:H film in N-type silicon chip front, and the thickness of corresponding a-Si:H film is 8nm, has deposited rear cooling and has led to argon gas vacuum breaker and to begin to speak room by silicon chip turn-over.
(4) deposition of N-type silicon chip reverse side a-Si:H film
The deposition (technological parameter is identical with step (3)) of N-type silicon chip reverse side a-Si:H film is completed by the deposition process of step (3), sedimentation time is 12s, the thickness of corresponding a-Si:H film is 10nm, deposited rear cooling lead to argon gas vacuum breaker begin to speak sampling, obtain HIT battery N-type silicon chip a-Si:H film.
In the above conditions after double-sided deposition a-Si:H film, obtain the N-type silicon chip surface of high passivation quality low surface defect density, minority carrier life time reaches 420 μ s(body minority carrier life time <1ms), silicon chip surface recombination rate <30cm/s, battery ImpliedVoc reaches 702mv.
embodiment 2:
A preparation method for HIT battery N-type silicon chip a-Si:H film of the present invention, technological process as shown in Figure 1, comprises the following steps:
(1) N-type silicon chip cleaning and texturing: the N-type silicon chip being used for HIT battery is carried out cleaning and texturing process, mainly complete silicon chip surface mechanical damage layer to remove and the preparation of pyramid matte, damaged layer on surface of silicon slice one side removes 22 μm, and pyramid Diagonal Dimension is 6 ~ 10 μm.
(2) oxide layer process (HF process): N-type silicon chip is after cleaning and texturing, and being inserted volumetric concentration is in the HF solution of 3%, reaction 10s, the main natural oxidizing layer removing silicon chip surface, taking-up after completing, clean with deionized water rinsing, N
2dry up.
(3) deposition of N-type silicon chip front a-Si:H film
(3.1) low vacuum is taken out in setting-out: carry out PECVD(and plasma enhanced chemical vapor deposition to step (2) gained N-type silicon chip) process, N-type silicon chip is placed in PECVD chamber, take out base vacuum, make base vacuum be reduced to below 20Pa, complete initial vacuum process.
(3.2) pumping high vacuum is heated: sample stage temperature to 190 DEG C in heating PECVD chamber, pumping high vacuum to 4.9 × 10
-4below Pa.
(3.3) deposit a-Si:H film: until temperature and vacuum degree up to standard and stable after, pass into deposition gases SiH
4with H
2, SiH
4with H
2gas flow ratio be 1: 6, after gas flow is stable, regulate deposition pressure and radio frequency power density, gas build-up of luminance is carried out to the deposition of a-Si:H, wherein deposition pressure is 80Pa, and radio frequency power density is 0.02W/cm
2, sedimentation time is 12s, obtains a-Si:H film in N-type silicon chip front, and the thickness of corresponding a-Si:H film is 10nm, has deposited rear cooling and has led to argon gas vacuum breaker and to begin to speak room by silicon chip turn-over.
(4) deposition of N-type silicon chip reverse side a-Si:H film
The deposition (technological parameter is identical with step (3)) of N-type silicon chip reverse side a-Si:H film is completed by the deposition process of step (3), sedimentation time is 10s, the thickness of corresponding a-Si:H film is 8nm, deposited rear cooling lead to argon gas vacuum breaker begin to speak sampling, obtain HIT battery N-type silicon chip a-Si:H film.
In the above conditions after double-sided deposition a-Si:H film, obtain the N-type silicon chip surface of high passivation quality low surface defect density, minority carrier life time reaches 483 μ s(body minority carrier life time <1ms), silicon chip surface recombination rate <25cm/s, battery ImpliedVoc reaches 713mv.
The above is only the preferred embodiment of the present invention, and protection scope of the present invention is also not only confined to above-described embodiment.All technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention.It is noted that for those skilled in the art, improvements and modifications under the premise without departing from the principles of the invention, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. a HIT battery preparation method for N-type silicon chip a-Si:H film, comprises the following steps:
(1) by N-type silicon chip cleaning and texturing;
(2) step (1) gained N-type silicon chip is carried out oxide layer process;
(3) step (2) gained N-type silicon chip is placed in PECVD chamber, first takes out base vacuum, then heat temperature raising, pumping high vacuum, then pass into deposition gases SiH
4with H
2, regulate deposition pressure and radio frequency power density, the front of N-type silicon chip carried out to the deposition of a-Si:H film, deposited rear cooling and by silicon chip turn-over;
(4) repeat the process of step (3), the reverse side of N-type silicon chip is carried out to the deposition of a-Si:H film, deposited rear cooling sampling, namely obtained HIT battery N-type silicon chip a-Si:H film.
2. the preparation method of HIT battery N-type silicon chip a-Si:H film according to claim 1, is characterized in that, in described step (3), first takes out base vacuum to below 20Pa, is then heated to 190 DEG C ~ 200 DEG C, pumping high vacuum to 5 × 10
-4below Pa.
3. the preparation method of HIT battery N-type silicon chip a-Si:H film according to claim 1, is characterized in that, in described step (3), and described SiH
4with H
2gas flow ratio be 1: 5 ~ 6.
4. the preparation method of HIT battery N-type silicon chip a-Si:H film according to claim 1, is characterized in that, in described step (3), described deposition pressure is 60Pa ~ 80Pa, and described radio frequency power density is 0.01W/cm
2~ 0.02W/cm
2.
5. the preparation method of N-type silicon chip a-Si:H film of the HIT battery according to any one of Claims 1 to 4, it is characterized in that, in described step (3), the sedimentation time of the front a-Si:H film of described N-type silicon chip is 10s ~ 12s, and deposit thickness is 8nm ~ 10nm.
6. the preparation method of N-type silicon chip a-Si:H film of the HIT battery according to any one of Claims 1 to 4, it is characterized in that, in described step (4), the sedimentation time of the reverse side a-Si:H film of described N-type silicon chip is 10s ~ 12s, and deposit thickness is 8nm ~ 10nm.
7. the preparation method of N-type silicon chip a-Si:H film of the HIT battery according to any one of Claims 1 to 4, it is characterized in that, in described step (1), through described N-type silicon chip cleaning and texturing, remove the surface damage layer 18 μm ~ 22 μm of N-type silicon chip, and obtained pyramid matte, pyramid Diagonal Dimension is 5 μm ~ 10 μm.
8. the preparation method of N-type silicon chip a-Si:H film of the HIT battery according to any one of Claims 1 to 4, it is characterized in that, in described step (2), described oxide layer process step (1) gained N-type silicon chip is placed in HF solution soak, and then cleans, dries up.
9. the preparation method of HIT battery N-type silicon chip a-Si:H film according to claim 8, is characterized in that, in described step (2), the volumetric concentration of described HF solution is 2% ~ 3%, and the time of described immersion is 10s ~ 20s.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946390A (en) * | 2017-12-04 | 2018-04-20 | 孙健春 | It is a kind of that there is the solar cell and production method for changing power grid |
| CN109545656A (en) * | 2018-10-12 | 2019-03-29 | 南昌大学 | Hydrogenation non crystal silicon film preparation method |
| CN110707182A (en) * | 2019-10-18 | 2020-01-17 | 苏州联诺太阳能科技有限公司 | Preparation method of heterojunction battery |
| CN111403492A (en) * | 2018-12-27 | 2020-07-10 | 成都珠峰永明科技有限公司 | Preparation method of passivation layer for solar cell and preparation method of solar cell |
| CN114242833A (en) * | 2021-11-18 | 2022-03-25 | 国家电投集团科学技术研究院有限公司 | Silicon wafer processing method of heterojunction solar cell |
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| CN107946390A (en) * | 2017-12-04 | 2018-04-20 | 孙健春 | It is a kind of that there is the solar cell and production method for changing power grid |
| CN109545656A (en) * | 2018-10-12 | 2019-03-29 | 南昌大学 | Hydrogenation non crystal silicon film preparation method |
| CN111403492A (en) * | 2018-12-27 | 2020-07-10 | 成都珠峰永明科技有限公司 | Preparation method of passivation layer for solar cell and preparation method of solar cell |
| CN110707182A (en) * | 2019-10-18 | 2020-01-17 | 苏州联诺太阳能科技有限公司 | Preparation method of heterojunction battery |
| CN110707182B (en) * | 2019-10-18 | 2022-07-12 | 苏州联诺太阳能科技有限公司 | Preparation method of heterojunction battery |
| CN114242833A (en) * | 2021-11-18 | 2022-03-25 | 国家电投集团科学技术研究院有限公司 | Silicon wafer processing method of heterojunction solar cell |
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