CN113594299B - Manufacturing process of P++ structure of N-type silicon wafer - Google Patents
Manufacturing process of P++ structure of N-type silicon wafer Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 88
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 88
- 239000010703 silicon Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052796 boron Inorganic materials 0.000 claims abstract description 42
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 238000001816 cooling Methods 0.000 claims abstract description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 42
- 229910052757 nitrogen Inorganic materials 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 11
- 229910001882 dioxygen Inorganic materials 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 8
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 8
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 6
- 239000010453 quartz Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 238000007599 discharging Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract description 2
- 230000000087 stabilizing effect Effects 0.000 description 4
- 238000000608 laser ablation Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The invention provides a manufacturing process of an N-type silicon wafer P++ structure, which adopts step-shaped sectional temperature rise and fall to perform two times of diffusion, and firstly performs low-temperature constant-temperature first diffusion at a lower temperature to uniformly distribute boron atoms on the surface of the silicon wafer; then heating and high-temperature anaerobic propulsion are carried out, after a shallow junction lightly doped region is generated on the surface of the silicon wafer, cooling and low-temperature secondary diffusion are carried out, and a uniform boron-rich layer is formed on the surface of the silicon wafer; carrying out heavy doping on the surface by laser SE, and finally cleaning the silicon surface to form a final PN junction, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction; the preparation process can achieve the effects of reducing boron source consumption and improving electrical property collection effect.
Description
Technical Field
The invention relates to the field of solar cell production and manufacturing, in particular to a manufacturing process of an N-type silicon wafer P++ structure.
Background
In the technical field of the current solar battery, along with the continuous progress of the high-efficiency battery technology, the photoelectric conversion efficiency of the solar battery is also continuously improved, and one of the solar battery is to utilize laser for doping to prepare a selective P++ emission electrode battery. The battery has mainly two features: 1) The contact area of the metal grid line and the silicon wafer is a heavily doped area, which can form good ohmic contact and improve the filling factor; 2) The light receiving area is a lightly doped area, the response of short waves can be improved, and the recombination of minority carriers is reduced due to low surface concentration, so that the open-circuit voltage and the short-circuit current are improved.
The existing P++ layer of the N-type battery has relatively complex manufacturing process and difficult realization, and has the following defects during manufacturing: firstly, because the light-receiving area of the silicon wafer is a lightly doped area, a high-sheet-resistance process is required to be used in the diffusion process, and the higher-sheet-resistance process is, the lower the boron concentration on the surface of the silicon wafer is, the better heavy doping cannot be formed during laser ablation, so that poor ohmic contact is caused, the filling factor is reduced, and the battery efficiency is reduced; secondly, considering that the boron-expanded region of the silicon wafer is a high doping concentration region, the solid solubility difference of boron/phosphorus atoms in an oxide layer and Si is considered, the boron concentration of the etched surface is reduced, and good heavy doping cannot be formed.
Disclosure of Invention
Aiming at the technical problems, the invention provides a manufacturing process of an N-type silicon wafer P++ structure.
A manufacturing process of an N-type silicon wafer P++ structure mainly comprises the following steps:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to enable the surface of the silicon wafer to generate a pyramid-shaped surface structure, vertically or horizontally inserting the silicon wafer into a quartz crystal boat of a low-pressure diffusion furnace, and feeding the silicon wafer into a tube;
s2: heating to 850-880 ℃, and evacuating and detecting leakage;
s3: keeping the temperature at 850-880 ℃, and introducing nitrogen after constant-pressure evacuation to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: the temperature is kept between 850 ℃ and 880 ℃, nitrogen, oxygen and a boron source are introduced to carry out deposition diffusion on the surface of the silicon wafer, so that boron atoms are uniformly distributed on the surface of the silicon wafer;
s5: heating to 920-1000 deg.c and introducing nitrogen to stabilize pressure;
s6: keeping the temperature at 920-1000 ℃, and pushing for a period of time at constant temperature to enable the surface of the silicon wafer to generate a shallow junction lightly doped region;
s7: slowly cooling to 850-890 ℃ in nitrogen atmosphere;
s8: the temperature is kept at 850-890 ℃, and nitrogen, oxygen and boron sources are introduced to carry out secondary deposition diffusion on the surface of the silicon wafer, so that a uniform boron-rich layer is formed on the surface of the shallower PN junction of the silicon wafer;
s9: slowly cooling in nitrogen atmosphere, and discharging the tube;
s10: carrying out heavy doping treatment on the diffused silicon wafer by using laser SE;
s11: and cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction.
Preferably, the temperature rise time in step S2 is set at 900S.
Preferably, in the steps S3-S6 and S8-S9, the total flow of the gas in the furnace tube is always kept at 2500sccm; in the step S7, the total flow of the gas in the furnace tube is always kept at 2500-3500sccm.
Preferably, the flow rate of nitrogen gas introduced in the step S5 is 1100sccm-1900sccm, the flow rate of the boron source is 400-800sccm, and the flow rate of oxygen gas is 200-600sccm, wherein the gas flow rate ratio of the boron source to the oxygen gas is 4:3-4:2, and the oxygen gas flow rate is set according to the ratio of the boron source flow rate.
Preferably, the advancing time in step S6 is 1200-2400S, during which the tube remains anaerobic.
Preferably, the flow rate of nitrogen gas introduced in the step S8 is 750sccm-1750sccm, the flow rate of the boron source is 600-1000sccm, and the flow rate of oxygen gas is 150-750sccm, wherein the gas flow rate ratio of the boron source to the oxygen gas is 4:3-4:1, and the oxygen gas flow rate is set according to the ratio of the boron source flow rate.
Preferably, after the step S9, the sheet resistance of the surface of the silicon wafer is between 100 and 140 omega/sp, and the junction depth is between 0.3 and 0.6um.
Preferably, in step S10, the laser parameter selection power is between 32 and 38w, the marking speed is 22000-26500mm/S, the frequency is 170-230KHz, and the light spot width is 90-120um.
Preferably, after the step S10, the sheet resistance of the surface of the silicon wafer is between 70 and 90 omega/sp, the junction depth is between 0.5 and 0.9um, and the surface concentration is more than 3E19/cm 3 。
Preferably, the boron source is BBr 3 /BCl 3 Steam.
The beneficial effects of the invention are as follows: adopting stepped sectional temperature rise and fall to perform twice diffusion, and performing low-temperature constant-temperature first diffusion at a lower temperature to uniformly distribute boron atoms on the surface of a silicon wafer; then heating and high-temperature anaerobic propulsion are carried out, after a shallow junction lightly doped region is generated on the surface of the silicon wafer, cooling and low-temperature secondary diffusion are carried out, and a uniform boron-rich layer is formed on the surface of the silicon wafer; carrying out heavy doping on the surface by laser SE, and finally cleaning the silicon surface to form a final PN junction, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction; the preparation process can achieve the effects of reducing boron source consumption and improving electrical property collection effect.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a P++ structure of an N-type silicon wafer according to an embodiment of the invention;
the figures represent the numbers:
1. n-type silicon wafer 2, P++ layer 3, P+ layer 4 and printing slurry.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making creative efforts based on the embodiments of the present invention are included in the protection scope of the present invention.
The P++ structure of the N-type silicon wafer is shown in fig. 1, an N-type silicon wafer 1 is taken as a substrate, a P-type shallow junction lightly doped P+ layer 3 is formed in a non-grid line area (namely a light receiving area), and a P-type deep junction heavily doped P++ layer 2 is formed in a grid line area (namely a printing paste 4 area).
Example 1
A manufacturing process of an N-type silicon wafer P++ structure mainly comprises the following steps:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to enable the surface of the silicon wafer to generate a pyramid-shaped surface structure, vertically or horizontally inserting the silicon wafer into a quartz crystal boat of a low-pressure diffusion furnace, and feeding the silicon wafer into a tube;
s2: heating to 850 ℃, setting the heating time at 900s, enabling the silicon wafer to reach the temperature set by the process, evacuating and detecting the leak, and ensuring that the pressure maintaining of the furnace tube has no problem;
s3: keeping the temperature at 850 ℃, and after constant-pressure evacuation, introducing nitrogen with the flow of 2500sccm to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: maintaining the temperature at 850 deg.C and total flow of 2500sccm, introducing 1900sccm nitrogen gas, 200sccm oxygen gas and 400sccm boron source (BBr) 3 /BCl 3 Vapor) to perform deposition diffusion on the surface of the silicon wafer to uniformly distribute boron atoms on the siliconA sheet surface; the oxygen flow is set according to the proportion of the boron source flow, and nitrogen is used as compensation gas for stabilizing the total gas quantity; the oxygen flow is as small as possible (the boron source is decomposed and introduced), and the quartz device can be protected from corrosion;
s5: heating to 920 ℃, and introducing nitrogen with the flow of 2500sccm for pressure stabilization;
s6: maintaining the temperature at 920 ℃, maintaining the flow at 2500sccm, and pushing at constant temperature for 1200-2400s (keeping the anaerobic state in the tube during the period) so as to generate a shallow junction lightly doped region on the surface of the silicon wafer;
s7: keeping the total flow of 2500-3500sccm, and slowly cooling to 850 ℃ in a nitrogen atmosphere;
s8: maintaining the temperature at 850 deg.C, maintaining 2500sccm total flow, introducing 1750sccm nitrogen, 150sccm oxygen and 600sccm boron source (BBr) 3 /BCl 3 Performing secondary deposition diffusion (oxygen flow is set according to the proportion of boron source flow, and nitrogen is introduced as compensation gas for stabilizing total gas quantity) on the surface of the silicon wafer, so that a uniform boron-rich layer is formed on the surface of a shallower PN junction of the silicon wafer; the boron-rich layer not only solves the problem of insufficient BSG concentration of laser ablation, but also is easy to remove in the subsequent boron washing process, so that the emitter is still kept to be a lightly doped region with low surface concentration, and the problems of poor ohmic contact and reduced filling factor caused by low BSG concentration during laser doping can be effectively solved;
s9: maintaining the total flow of 2500sccm, slowly cooling in nitrogen atmosphere, and discharging the tube; at this time, the sheet resistance of the surface of the silicon wafer is approximately 140 omega/sp, and the junction depth is 0.3um;
s10: carrying out heavy doping treatment on the diffused silicon wafer by using laser SE, wherein the laser parameter selection power is 36w, the marking speed is 22500mm/s, the frequency is 210KHz, and the light spot width is 90-120um; after the treatment is finished, the sheet resistance of the surface of the silicon wafer is approximately 90 omega/sp, the junction depth is 0.5um, and the surface concentration is more than 3E19/cm 3 ；
S11: and cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction.
Example two
A manufacturing process of an N-type silicon wafer P++ structure mainly comprises the following steps:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to enable the surface of the silicon wafer to generate a pyramid-shaped surface structure, vertically or horizontally inserting the silicon wafer into a quartz crystal boat of a low-pressure diffusion furnace, and feeding the silicon wafer into a tube;
s2: heating to 880 ℃, setting the heating time at 900s, enabling the silicon wafer to reach the temperature set by the process, evacuating and detecting the leak, and ensuring that the pressure maintaining of the furnace tube has no problem;
s3: keeping the temperature at 880 ℃, and after constant-pressure evacuation, introducing nitrogen with the flow of 2500sccm to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: maintaining the temperature at 880 deg.C and total flow of 2500sccm, introducing 1100sccm nitrogen gas, 600sccm oxygen gas and 800sccm boron source (BBr) 3 /BCl 3 Steam) carrying out deposition diffusion on the surface of the silicon wafer to ensure that boron atoms are uniformly distributed on the surface of the silicon wafer; the oxygen flow is set according to the proportion of the boron source flow, and nitrogen is used as compensation gas for stabilizing the total gas quantity; the oxygen flow is as small as possible (the boron source is decomposed and introduced), and the quartz device can be protected from corrosion;
s5: heating to 1000 ℃, and introducing nitrogen with the flow rate of 2500sccm for pressure stabilization;
s6: keeping the temperature at 1000 ℃, keeping the flow at 2500sccm, and pushing at constant temperature for 1200-2400s (keeping the anaerobic state in the tube during the period) so as to generate a shallow junction lightly doped region on the surface of the silicon wafer;
s7: maintaining the total flow of 2500-3500sccm, and slowly cooling to 890 ℃ in a nitrogen atmosphere;
s8: maintaining the temperature at 890 deg.C and total flow of 2500sccm, introducing 750sccm nitrogen, 750sccm oxygen and 1000sccm boron source (BBr) 3 /BCl 3 Performing secondary deposition diffusion (oxygen flow is set according to the proportion of boron source flow, and nitrogen is introduced as compensation gas for stabilizing total gas quantity) on the surface of the silicon wafer, so that a uniform boron-rich layer is formed on the surface of a shallower PN junction of the silicon wafer; the boron-rich layer not only solves the problem of insufficient BSG concentration of laser ablation, but also is very compatible in the subsequent boron washing processThe method is easy to remove, so that the emitter is still kept to be a lightly doped region with low surface concentration, and the problems of poor ohmic contact and reduced filling factor caused by low BSG concentration during laser doping can be effectively solved;
s9: maintaining the total flow of 2500sccm, slowly cooling in nitrogen atmosphere, and discharging the tube; at the moment, the sheet resistance of the surface of the silicon wafer is approximately 100 omega/sp, and the junction depth is 0.6um;
s10: carrying out heavy doping treatment on the diffused silicon wafer by using laser SE, wherein the laser parameter selection power is 36w, the marking speed is 22500mm/s, the frequency is 210KHz, and the light spot width is 90-120um; after the treatment is finished, the sheet resistance of the surface of the silicon wafer is approximately 70 omega/sp, the junction depth is 0.9um, and the surface concentration is more than 3E19/cm 3 ；
S11: and cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction.
Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.
Claims (7)
1. The manufacturing process of the P++ structure of the N-type silicon wafer is characterized by mainly comprising the following steps of:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to enable the surface of the silicon wafer to generate a pyramid-shaped surface structure, vertically or horizontally inserting the silicon wafer into a quartz crystal boat of a low-pressure diffusion furnace, and feeding the silicon wafer into a tube;
s2: heating to 850-880 ℃, and evacuating and detecting leakage;
s3: keeping the temperature at 850-880 ℃, and introducing nitrogen after constant-pressure evacuation to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: the temperature is kept between 850 ℃ and 880 ℃, nitrogen, oxygen and a boron source are introduced to carry out deposition diffusion on the surface of the silicon wafer, so that boron atoms are uniformly distributed on the surface of the silicon wafer;
s5: heating to 920-1000 deg.c and introducing nitrogen to stabilize pressure;
s6: keeping the temperature at 920-1000 ℃, and pushing for a period of time at constant temperature to enable the surface of the silicon wafer to generate a shallow junction lightly doped region;
s7: slowly cooling to 850-890 ℃ in nitrogen atmosphere;
s8: the temperature is kept at 850-890 ℃, and nitrogen, oxygen and boron sources are introduced to carry out secondary deposition diffusion on the surface of the silicon wafer, so that a uniform boron-rich layer is formed on the surface of the shallower PN junction of the silicon wafer;
s9: slowly cooling in nitrogen atmosphere, and discharging the tube;
s10: carrying out heavy doping treatment on the diffused silicon wafer by using laser SE;
s11: cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction;
the advancing time in the step S6 is 1200-2400S, and the tube is kept in an anaerobic state during the advancing time;
after the step S10, the sheet resistance of the surface of the silicon wafer is between 70 and 90 omega/sp, the junction depth is between 0.5 and 0.9um, and the surface concentration is more than 3E19/cm 3 ；
The boron source is BBr 3 /BCl 3 Steam.
2. The process for manufacturing the P++ structure of the N-type silicon wafer according to claim 1, which is characterized in that: the temperature rise time in step S2 is set at 900S.
3. The process for manufacturing the P++ structure of the N-type silicon wafer according to claim 1, which is characterized in that: in the steps S3-S6 and S8-S9, the total flow of the gas in the furnace tube is always kept at 2500sccm; in the step S7, the total flow of the gas in the furnace tube is always kept at 2500-3500sccm.
4. A process for fabricating an N-type silicon wafer p++ structure according to claim 3, wherein: the flow rate of nitrogen gas introduced in the step S5 is 1100-1900 sccm, the flow rate of the boron source is 400-800sccm, the flow rate of oxygen gas is 200-600sccm, wherein the gas flow rate ratio of the boron source to the oxygen gas is 4:3-4:2, and the oxygen gas flow rate is set according to the ratio of the boron source flow rate.
5. A process for fabricating an N-type silicon wafer p++ structure according to claim 3, wherein: the flow rate of nitrogen gas introduced in the step S8 is 750sccm-1750sccm, the flow rate of the boron source is 600-1000sccm, the flow rate of oxygen is 150-750sccm, wherein the gas flow rate ratio of the boron source to the oxygen is 4:3-4:1, and the oxygen flow rate is set according to the ratio of the boron source flow rate.
6. The process for manufacturing the P++ structure of the N-type silicon wafer according to claim 1, which is characterized in that: after the step S9, the sheet resistance of the surface of the silicon wafer is between 100 and 140 omega/sp, and the junction depth is between 0.3 and 0.6um.
7. The process for manufacturing the P++ structure of the N-type silicon wafer according to claim 1, which is characterized in that: in step S10, the laser parameter selection power is between 32 and 38w, the marking speed is 22000-26500mm/S, the frequency is 170-230KHz, and the light spot width is 90-120um.
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