CN113594299A - Manufacturing process of N-type silicon wafer P + + structure - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 83
- 239000010703 silicon Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052796 boron Inorganic materials 0.000 claims abstract description 43
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 238000001816 cooling Methods 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 48
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 26
- 239000001301 oxygen Substances 0.000 claims description 26
- 229910052760 oxygen Inorganic materials 0.000 claims description 26
- 229910052757 nitrogen Inorganic materials 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 22
- 239000007789 gas Substances 0.000 claims description 16
- 239000010453 quartz Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 8
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 8
- 229910015844 BCl3 Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical group BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 claims description 4
- 238000007599 discharging Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910015845 BBr3 Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 4
- 230000000087 stabilizing effect Effects 0.000 description 5
- 238000000608 laser ablation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention provides a manufacturing process of a P + + structure of an N-type silicon wafer, which adopts step-shaped sectional heating and cooling to carry out two-time diffusion, and firstly carries out low-temperature constant-temperature first diffusion at a lower temperature to ensure that boron atoms are uniformly distributed on the surface of the silicon wafer; then heating and carrying out high-temperature oxygen-free propulsion, after a shallow junction lightly doped region is generated on the surface of the silicon wafer, cooling and carrying out low-temperature secondary diffusion to form a uniform boron-rich layer on the surface of the silicon wafer; carrying out heavy doping on the surface by laser SE, and finally cleaning the surface of the silicon to form a final PN junction, wherein the PN junction is deep junction heavy doping in an SE region, and the non-SE region is shallow junction light doping; the manufacturing process can achieve the effects of reducing the consumption of boron sources and improving the collecting effect of electrical property.
Description
Technical Field
The invention relates to the field of solar cell production and manufacturing, in particular to a manufacturing process of an N-type silicon wafer P + + structure.
Background
In the current solar cell technology field, with the continuous progress of high-efficiency cell technology, the photoelectric conversion efficiency is also continuously improved, and one of the methods is to dope by using laser to prepare a selective P + + emission electrode cell. The battery has two main characteristics: 1) the contact area of the metal grid line and the silicon wafer is a heavily doped area which can form good ohmic contact and improve the filling factor; 2) the light receiving area is a lightly doped area, short wave response can be improved, and minority carrier recombination is reduced due to low surface concentration, so that open-circuit voltage and short-circuit current are increased.
The existing N-type cell P + + layer is relatively complex in manufacturing process and difficult to realize, and has the following defects in manufacturing: firstly, because the light receiving area of the silicon wafer is a lightly doped area, the diffusion process needs to use a high sheet resistance process, the higher the sheet resistance process, the lower the boron concentration on the surface, and good heavy doping cannot be formed during laser ablation, so that poor ohmic contact is caused, the filling factor is reduced, and the battery efficiency is reduced; secondly, considering that the boron diffusion area of the silicon wafer is a high doping concentration area, the concentration of boron on the etched surface is reduced due to the solid solubility difference of boron/phosphorus atoms in an oxide layer and Si, and good heavy doping cannot be formed.
Disclosure of Invention
Aiming at the technical problem, the invention provides a manufacturing process of an N-type silicon wafer P + + structure.
A manufacturing process of an N-type silicon wafer P + + structure mainly comprises the following steps:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to generate a pyramid-shaped surface structure on the surface of the silicon wafer, vertically or horizontally inserting the silicon wafer into a quartz boat of a low-pressure diffusion furnace, and introducing the silicon wafer into the quartz boat;
s2: heating to 850-880 ℃, and evacuating and detecting leakage;
s3: keeping the temperature at 850-880 ℃, evacuating at constant pressure, and introducing nitrogen to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: keeping the temperature at 850-880 ℃, introducing nitrogen, oxygen and a boron source to carry out deposition diffusion on the surface of the silicon wafer, so that boron atoms are uniformly distributed on the surface of the silicon wafer;
s5: heating to 920-1000 ℃, and introducing nitrogen to stabilize the pressure;
s6: keeping the temperature at 920-1000 ℃, and advancing for a period of time at constant temperature to generate a shallow junction lightly doped region on the surface of the silicon wafer;
s7: slowly cooling to 850-890 ℃ under the nitrogen atmosphere;
s8: keeping the temperature at 850-890 ℃, and introducing nitrogen, oxygen and a boron source to carry out secondary deposition diffusion on the surface of the silicon wafer so as to form a uniform boron-rich layer on the surface of a shallow PN junction of the silicon wafer;
s9: slowly cooling in the nitrogen atmosphere, and discharging the pipe;
s10: carrying out heavy doping treatment on the diffused silicon wafer through laser SE;
s11: and cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction.
Preferably, the temperature rise time in step S2 is set to 900S.
Preferably, in steps S3-S6 and S8-S9, the total flow rate of the gas in the furnace tube is kept at 2500 sccm; the total flow rate of the gas in the furnace tube in step S7 is kept at 2500-.
Preferably, the flow rate of the nitrogen introduced in step S5 is 1100sccm to 1900sccm, the flow rate of the boron source is 400sccm and 800sccm, and the flow rate of the oxygen is 200sccm and 600sccm, wherein the gas flow rate ratio of the boron source and the oxygen is 4:3 to 4:2, and the oxygen flow rate is set according to the flow rate ratio of the boron source.
Preferably, the advancing time in step S6 is 1200-2400S, during which the tube is kept in an oxygen-free state.
Preferably, the flow rate of the nitrogen introduced in step S8 is 750sccm to 1750sccm, the flow rate of the boron source is 600sccm and 1000sccm, and the flow rate of the oxygen is 150sccm and 750sccm, wherein the gas flow ratio of the boron source and the oxygen is 4:3 to 4:1, and the oxygen flow rate is set according to the flow rate ratio of the boron source.
Preferably, after the step S9, the sheet resistance of the silicon wafer surface is between 100-140 Ω/sp, and the junction depth is 0.3-0.6 um.
Preferably, in step S10, the laser parameter selection power is 32-38w, the marking speed is 22000-26500mm/S, the frequency is 170-230KHz, and the spot width is 90-120 um.
Preferably, after the step S10, the sheet resistance of the silicon wafer surface is between 70 and 90 omega/sp, the junction depth is between 0.5 and 0.9um, and the surface concentration is more than 3E19/cm3。
Preferably, the boron source is BBr3/BCl3And (4) steam.
The invention has the beneficial effects that: step-shaped subsection temperature rise and fall is adopted for carrying out two-time diffusion, and first diffusion is carried out at low temperature and constant temperature at low temperature, so that boron atoms are uniformly distributed on the surface of the silicon wafer; then heating and carrying out high-temperature oxygen-free propulsion, after a shallow junction lightly doped region is generated on the surface of the silicon wafer, cooling and carrying out low-temperature secondary diffusion to form a uniform boron-rich layer on the surface of the silicon wafer; carrying out heavy doping on the surface by laser SE, and finally cleaning the surface of the silicon to form a final PN junction, wherein the PN junction is deep junction heavy doping in an SE region, and the non-SE region is shallow junction light doping; the manufacturing process can achieve the effects of reducing the consumption of boron sources and improving the collecting effect of electrical property.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a P + + structure of an N-type silicon wafer according to an embodiment of the present invention;
the figures in the drawings represent:
1. an N-type silicon wafer 2, a P + + layer 3, a P + layer 4 and printing slurry.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the protection scope of the present invention.
The P + + structure of the N-type silicon wafer is shown in fig. 1, and a P-type shallow junction lightly doped P + layer 3 is formed in a non-grid line region (i.e., a light receiving region) and a P-type deep junction heavily doped P + + layer 2 is formed in a grid line region (i.e., a printing paste 4 region) by using the N-type silicon wafer 1 as a substrate.
Example one
A manufacturing process of an N-type silicon wafer P + + structure mainly comprises the following steps:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to generate a pyramid-shaped surface structure on the surface of the silicon wafer, vertically or horizontally inserting the silicon wafer into a quartz boat of a low-pressure diffusion furnace, and introducing the silicon wafer into the quartz boat;
s2: heating to 850 ℃, setting the heating time at 900s, enabling the silicon wafer to reach the temperature set by the process, evacuating and detecting leakage, and ensuring that the pressure maintaining of the furnace tube has no problem;
s3: keeping the temperature at 850 ℃, pumping out nitrogen with the flow of 2500sccm after constant pressure pumping so as to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: the temperature was maintained at 850 deg.C, a total flow of 2500sccm was maintained, 1900sccm of nitrogen, 200sccm of oxygen, and 400sccm of boron source (BBr) were introduced3/BCl3Steam) is used for carrying out deposition diffusion on the surface of the silicon wafer, so that boron atoms are uniformly distributed on the surface of the silicon wafer; wherein the oxygen flow is set according to the proportion of the boron source flow, and nitrogen is introduced as compensation gas for stabilizing the total gas quantity; oxygen is introduced into the quartz tube at a flow rate as small as possible (the introduced boron source is decomposed), and the quartz tube can be protected from being corroded;
s5: heating to 920 ℃, and introducing nitrogen with the flow of 2500sccm for pressure stabilization;
s6: keeping the temperature at 920 ℃, keeping the flow at 2500sccm, and advancing at a constant temperature of 1200-2400s (keeping an oxygen-free state in the tube) to enable a shallow junction lightly doped region to be generated on the surface of the silicon wafer;
s7: keeping the total flow of 2500-3500sccm, and slowly cooling to 850 ℃ in a nitrogen atmosphere;
s8: the temperature was maintained at 850 deg.C, a total flow of 2500sccm was maintained, 1750sccm of nitrogen, 150sccm of oxygen, and 600sccm of boron source (BBr) were introduced3/BCl3Steam) to carry out secondary deposition diffusion on the surface of the silicon wafer (the oxygen flow is set according to the proportion of the boron source flow, and nitrogen is introduced as compensation gas for stabilizing the total gas quantity), so that a uniform boron-rich layer is formed on the surface of a shallower PN junction of the silicon wafer; the boron-rich layer not only solves the problem of insufficient BSG concentration of laser ablation, but also is easy to remove in the subsequent boron washing process, so that the emitter is still kept in a lightly doped region with low surface concentration, and the problems of poor ohmic contact and reduced filling factor caused by low BSG concentration in laser doping can be effectively solved;
s9: keeping the total flow of 2500sccm, slowly cooling in a nitrogen atmosphere, and discharging a pipe; at the moment, the sheet resistance of the surface of the silicon chip is approximately 140 omega/sp, and the junction depth is 0.3 um;
s10: heavily doping the diffused silicon wafer by laser SE, wherein the laser parameter selection power is 36w, the marking speed is 22500mm/s, the frequency is 210KHz, and the light spot width is 90-120 um; after the treatment is finished, the sheet resistance of the silicon wafer surface is approximately 90 omega/sp, the junction depth is 0.5um, and the surface concentration is more than 3E19/cm3；
S11: and cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction.
Example two
A manufacturing process of an N-type silicon wafer P + + structure mainly comprises the following steps:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to generate a pyramid-shaped surface structure on the surface of the silicon wafer, vertically or horizontally inserting the silicon wafer into a quartz boat of a low-pressure diffusion furnace, and introducing the silicon wafer into the quartz boat;
s2: heating to 880 ℃, setting the heating time to 900s, enabling the silicon wafer to reach the temperature set by the process, evacuating and detecting leakage, and ensuring that the pressure maintaining of the furnace tube has no problem;
s3: keeping the temperature at 880 ℃, evacuating at constant pressure, and introducing nitrogen with the flow of 2500sccm to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: the temperature was maintained at 880 deg.C, a total flow of 2500sccm was maintained, and 1100sccm of nitrogen, 600sccm of oxygen, and 800sccm of boron source (BBr) were introduced3/BCl3Steam) is used for carrying out deposition diffusion on the surface of the silicon wafer, so that boron atoms are uniformly distributed on the surface of the silicon wafer; wherein the oxygen flow is set according to the proportion of the boron source flow, and nitrogen is introduced as compensation gas for stabilizing the total gas quantity; oxygen is introduced into the quartz tube at a flow rate as small as possible (the introduced boron source is decomposed), and the quartz tube can be protected from being corroded;
s5: heating to 1000 ℃, and introducing nitrogen with the flow of 2500sccm for stabilizing pressure;
s6: keeping the temperature at 1000 ℃, keeping the flow at 2500sccm, advancing at a constant temperature for 1200-2400s (keeping an oxygen-free state in the tube during the process), and generating a shallow junction lightly doped region on the surface of the silicon wafer;
s7: keeping the total flow of 2500-3500sccm, and slowly cooling to 890 ℃ in a nitrogen atmosphere;
s8: the temperature was kept at 890 ℃ and a total flow of 2500sccm was maintained, 750sccm of nitrogen, 750sccm of oxygen and 1000sccm of boron source (BBr) was passed3/BCl3Steam) to carry out secondary deposition diffusion on the surface of the silicon wafer (the oxygen flow is set according to the proportion of the boron source flow, and nitrogen is introduced as compensation gas for stabilizing the total gas quantity), so that a uniform boron-rich layer is formed on the surface of a shallower PN junction of the silicon wafer; the boron-rich layer not only solves the problem of insufficient BSG concentration of laser ablation, but also is easy to remove in the subsequent boron washing process, so that the emitter is still kept in a lightly doped region with low surface concentration, and the problems of poor ohmic contact and reduced filling factor caused by low BSG concentration in laser doping can be effectively solved;
s9: keeping the total flow of 2500sccm, slowly cooling in a nitrogen atmosphere, and discharging a pipe; at the moment, the sheet resistance of the surface of the silicon chip is approximately 100 omega/sp, and the junction depth is 0.6 um;
s10: heavily doping the diffused silicon wafer by laser SE, wherein the laser parameter selection power is 36w, the marking speed is 22500mm/s, the frequency is 210KHz, and the light spot width is 90-120 um; after the treatment is finished, the sheet resistance of the silicon wafer surface is approximately 70 omega/sp, the junction depth is 0.9um, and the surface concentration is more than 3E19/cm3；
S11: and cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction.
Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention.
Claims (10)
1. A manufacturing process of an N-type silicon wafer P + + structure is characterized by mainly comprising the following steps:
s1: taking an N-type silicon wafer as a substrate material, cleaning and texturing to generate a pyramid-shaped surface structure on the surface of the silicon wafer, vertically or horizontally inserting the silicon wafer into a quartz boat of a low-pressure diffusion furnace, and introducing the silicon wafer into the quartz boat;
s2: heating to 850-880 ℃, and evacuating and detecting leakage;
s3: keeping the temperature at 850-880 ℃, evacuating at constant pressure, and introducing nitrogen to stabilize the air pressure in the tube and the temperature of the silicon wafer;
s4: keeping the temperature at 850-880 ℃, introducing nitrogen, oxygen and a boron source to carry out deposition diffusion on the surface of the silicon wafer, so that boron atoms are uniformly distributed on the surface of the silicon wafer;
s5: heating to 920-1000 ℃, and introducing nitrogen to stabilize the pressure;
s6: keeping the temperature at 920-1000 ℃, and advancing for a period of time at constant temperature to generate a shallow junction lightly doped region on the surface of the silicon wafer;
s7: slowly cooling to 850-890 ℃ under the nitrogen atmosphere;
s8: keeping the temperature at 850-890 ℃, and introducing nitrogen, oxygen and a boron source to carry out secondary deposition diffusion on the surface of the silicon wafer so as to form a uniform boron-rich layer on the surface of a shallow PN junction of the silicon wafer;
s9: slowly cooling in the nitrogen atmosphere, and discharging the pipe;
s10: carrying out heavy doping treatment on the diffused silicon wafer through laser SE;
s11: and cleaning to form a final PN junction on the surface of the silicon wafer, wherein the PN junction is heavily doped with a deep junction in an SE region, and the non-SE region is lightly doped with a shallow junction.
2. The process according to claim 1, wherein the process comprises the following steps: the temperature rise time in step S2 is set at 900S.
3. The process according to claim 1, wherein the process comprises the following steps: in steps S3-S6 and S8-S9, the total flow of gas in the furnace tube is kept at 2500sccm all the time; the total flow rate of the gas in the furnace tube in step S7 is kept at 2500-.
4. The process according to claim 3, wherein the process comprises the following steps: the flow rate of the nitrogen introduced in the step S5 is 1100sccm-1900sccm, the flow rate of the boron source is 400-800sccm, and the flow rate of the oxygen is 200-600sccm, wherein the gas flow rate ratio of the boron source and the oxygen is 4:3-4:2, and the oxygen flow rate is set according to the flow rate ratio of the boron source.
5. The process according to claim 3, wherein the process comprises the following steps: the advancing time in step S6 is 1200-.
6. The process according to claim 3, wherein the process comprises the following steps: the flow rate of the nitrogen introduced in the step S8 is 750sccm-1750sccm, the flow rate of the boron source is 600-1000sccm, and the flow rate of the oxygen is 150-750sccm, wherein the gas flow rate ratio of the boron source and the oxygen is 4:3-4:1, and the oxygen flow rate is set according to the ratio of the boron source flow rate.
7. The process according to claim 1, wherein the process comprises the following steps: after the step S9, the sheet resistance of the silicon wafer surface is between 100-140 Ω/sp, and the junction depth is 0.3-0.6 um.
8. The process according to claim 1, wherein the process comprises the following steps: in step S10, the laser parameter selection power is 32-38w, the marking speed is 22000-26500mm/S, the frequency is 170-230KHz, and the spot width is 90-120 um.
9. The process according to claim 8, wherein the process comprises the following steps: after step S10, the sheet resistance of the silicon wafer surface is between 70-90 Ω/sp, the junction depth is 0.5-0.9um, and the surface concentration is greater than 3E19/cm3。
10. The process for preparing a P + + structure on an N-type silicon wafer according to any one of claims 1 to 9Characterized in that: the boron source is BBr3/BCl3And (4) steam.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117133834A (en) * | 2023-10-25 | 2023-11-28 | 金阳(泉州)新能源科技有限公司 | Short-process preparation method and application of combined passivation back contact battery |
| EP4283687A1 (en) * | 2022-05-26 | 2023-11-29 | Zhejiang Jinko Solar Co., Ltd. | Solar cell and production method thereof, photovoltaic module |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102473592A (en) * | 2009-07-02 | 2012-05-23 | 英诺瓦莱特公司 | Methods of using a silicon nanoparticle fluid to control in situ a set of dopant diffusion profiles |
| CN103050568A (en) * | 2011-10-13 | 2013-04-17 | 三星Sdi株式会社 | Method of manufacturing a photoelectric device |
| CN103632935A (en) * | 2013-11-29 | 2014-03-12 | 英利集团有限公司 | Boron diffusion method of N type silicon chip, crystalline silicon solar cell and manufacturing method of crystalline silicon solar cell |
| CN104205363A (en) * | 2012-05-04 | 2014-12-10 | 泰姆普雷斯艾普公司 | Method of manufacturing a solar cell and equipment therefore |
| CN105304753A (en) * | 2015-09-25 | 2016-02-03 | 中国电子科技集团公司第四十八研究所 | N-type cell boron diffusion technology |
| CN106711280A (en) * | 2016-12-01 | 2017-05-24 | 江苏福克斯新能源科技有限公司 | Method of making N-type double-sided battery |
| CN108054088A (en) * | 2017-12-15 | 2018-05-18 | 浙江晶科能源有限公司 | N-type silicon chip Boron diffusion method, crystal silicon solar energy battery and preparation method thereof |
| CN110600558A (en) * | 2019-07-27 | 2019-12-20 | 江苏顺风光电科技有限公司 | Boron process suitable for P + selective emitter battery |
| CN111477719A (en) * | 2019-10-22 | 2020-07-31 | 国家电投集团西安太阳能电力有限公司 | Manufacturing method of full-suede N-type double-sided battery |
| CN111524797A (en) * | 2020-04-26 | 2020-08-11 | 泰州中来光电科技有限公司 | Preparation method of selective emitter |
| CN111739957A (en) * | 2020-06-30 | 2020-10-02 | 常州时创能源股份有限公司 | Selective doping method of N-type solar cell |
| CN112201575A (en) * | 2020-09-11 | 2021-01-08 | 青海黄河上游水电开发有限责任公司光伏产业技术分公司 | Selective boron source doping method and preparation method of double-sided battery |
-
2021
- 2021-07-27 CN CN202110852908.5A patent/CN113594299B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102473592A (en) * | 2009-07-02 | 2012-05-23 | 英诺瓦莱特公司 | Methods of using a silicon nanoparticle fluid to control in situ a set of dopant diffusion profiles |
| CN103050568A (en) * | 2011-10-13 | 2013-04-17 | 三星Sdi株式会社 | Method of manufacturing a photoelectric device |
| CN104205363A (en) * | 2012-05-04 | 2014-12-10 | 泰姆普雷斯艾普公司 | Method of manufacturing a solar cell and equipment therefore |
| CN103632935A (en) * | 2013-11-29 | 2014-03-12 | 英利集团有限公司 | Boron diffusion method of N type silicon chip, crystalline silicon solar cell and manufacturing method of crystalline silicon solar cell |
| CN105304753A (en) * | 2015-09-25 | 2016-02-03 | 中国电子科技集团公司第四十八研究所 | N-type cell boron diffusion technology |
| CN106711280A (en) * | 2016-12-01 | 2017-05-24 | 江苏福克斯新能源科技有限公司 | Method of making N-type double-sided battery |
| CN108054088A (en) * | 2017-12-15 | 2018-05-18 | 浙江晶科能源有限公司 | N-type silicon chip Boron diffusion method, crystal silicon solar energy battery and preparation method thereof |
| CN110600558A (en) * | 2019-07-27 | 2019-12-20 | 江苏顺风光电科技有限公司 | Boron process suitable for P + selective emitter battery |
| CN111477719A (en) * | 2019-10-22 | 2020-07-31 | 国家电投集团西安太阳能电力有限公司 | Manufacturing method of full-suede N-type double-sided battery |
| CN111524797A (en) * | 2020-04-26 | 2020-08-11 | 泰州中来光电科技有限公司 | Preparation method of selective emitter |
| CN111739957A (en) * | 2020-06-30 | 2020-10-02 | 常州时创能源股份有限公司 | Selective doping method of N-type solar cell |
| CN112201575A (en) * | 2020-09-11 | 2021-01-08 | 青海黄河上游水电开发有限责任公司光伏产业技术分公司 | Selective boron source doping method and preparation method of double-sided battery |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4283687A1 (en) * | 2022-05-26 | 2023-11-29 | Zhejiang Jinko Solar Co., Ltd. | Solar cell and production method thereof, photovoltaic module |
| NL2033695A (en) * | 2022-05-26 | 2023-12-05 | Zhejiang Jinko Solar Co Ltd | Solar cell and production method thereof, photovoltaic module |
| CN117133834A (en) * | 2023-10-25 | 2023-11-28 | 金阳(泉州)新能源科技有限公司 | Short-process preparation method and application of combined passivation back contact battery |
| CN117133834B (en) * | 2023-10-25 | 2024-02-27 | 金阳(泉州)新能源科技有限公司 | Short-process preparation method and application of combined passivation back contact battery |
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