CN105093759A - 一种阵列基板及其制备方法、显示面板、显示装置 - Google Patents
一种阵列基板及其制备方法、显示面板、显示装置 Download PDFInfo
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Abstract
本发明提供一种阵列基板及其制备方法、显示面板、显示装置,用于解决现有技术中由阵列基板的周边区域由于封框胶受力导致信号走线产生各种不良的问题。本发明提供的子阵列基板及其制备方法、显示面板、显示装置,由于在阵列基板的周边区域的与封框胶接触的部分设有保护层,该保护层能阻止封框胶受力时对信号走线造成的不良。
Description
技术领域
本发明涉及显示技术领域,具体地,涉及一种阵列基板及其制备方法、显示面板、显示装置。
背景技术
液晶显示器得到了广泛的应用,液晶显示器包括阵列基板和彩膜基板,以及位于阵列基板和彩膜基板之间的液晶层,通过阵列基板或彩膜基板上的电极之间产生的电场来控制液晶分子的偏转实现显示功能。根据产生电场的电极的布置不同可以把液晶显示器分为TN型(TwistedNematic,扭曲向列)或ADS型(ADvancedSuperDimensionSwitch,高级超维场转换技术,简称ADS)。
TN型液晶显示器的阵列基板包括显示区域和周边区域,其中,显示区域用于设置像素单元和对像素单元进行控制的薄膜晶体管,周边区域用于设置各种信号走线,信号走线为驱动薄膜晶体管提供控制信号。
TN型显示器的结构示意图如图1所示,在周边区域的阵列基板和彩膜基板之间设有封框胶8,其中,封框胶8中含有金球81,该金球81用于将阵列基板上的公共电极信号传递到位于彩膜基板上的公共电极9上。
在周边区域的阵列基板玻璃1上设置与栅极同层布置的公共电极走线2、栅极走线21;在栅极金属层上设置栅极绝缘层3,在栅极绝缘层3上设置与源漏极同层布置的数据走线4;在栅极层上设置钝化层5,在钝化层5上设置与像素电极6同层布置的连接层61,其中,连接层61通过位于钝化层5的第二过孔和位于栅极绝缘层3中的第一过孔与公共电极走线2连接,这样公共电极信号从公共电极走线2经连接层61、金球81传递至位于彩膜基板上的公共电极9上。
在彩膜基板的彩膜基板玻璃13上设有彩膜层,彩膜层包括间隔设置的像素12,像素12之间设有黑矩阵11,在彩膜层上设置绝缘层平坦层10,在绝缘层平坦层10上设置公共电极9,在公共电极9上设置取向层7。
随着液晶面板向大型化、高精细化、高频率以及3D显示等方向的发展,业界需要开发低电阻的栅线、数据线、薄膜晶体管的源漏极及管脚等电极材料。由于电极材料电阻的减小,降低了阻抗容抗(RC)延迟,栅线和数据线尺寸可以制作得更精细,提高了开口率。由于金属铜的电阻仅为2μΩ·cm,因此,其目前已经成为电极材料的首选。
如图1所示,TN型显示器采用当铜作为电极材料时,其质较软,抗压能力差同时易被氧化。进行信赖性评价时易产生走线不良,尤其当前主流的窄边框设计的周边区域的空间很小时,需将电极信号走线在栅极层和源漏极层金属(栅极层和源漏极层均采用铜材料)上交替布线;阵列基板周边区域(像素12区外)的栅极走线21、数据线走线4和公共电极走线2被封框胶8覆盖区域,封框胶8中包含有金球81。由于钝化层5比较脆弱,同时,信号走线(栅极走线21、公共电极走线2或数据线走线4)是采用抗压比较差的铜制作,在封框胶8受到挤压时,金球81会造成栅极走线21和公共电极走线2短路,或数据线走线4和公共电极走线2短路,从而严重影响产品的质量。
如果增加钝化层5的厚度虽可以改善此不良,但根据存储电容公式Cst=εS/d,降低存储电容,会增加漏电率,影响显示效果,同时也会增加镀膜成本和刻蚀过孔所需的时间。
而对于ADS型显示器,如图2所示,与图1不同的是,彩膜基板上不用设置公共电极9,公共电极9设置在阵列基板上,此时,狭缝状的公共电极9和像素电极6之间形成电场控制液晶分子的偏转,进而实现显示。
此时,封框胶8中依然包含有硅球82或类似的作为支撑的玻璃纤维。由于钝化层5比较脆弱,同时,信号走线(栅极走线21、公共电极走线2或数据线走线4)是采用抗压比较差的铜制作,在封框胶8受到挤压时,硅球82会造成封框胶8对应的区域的钝化层5和信号走线发生断裂,从而严重影响产品的质量。
发明内容
解决上述问题所采用的技术方案是一种阵列基板及其制备方法、显示面板、显示装置。
本发明提供的一种阵列基板,包括显示区域和周边区域,所述周边区域设置有信号走线,在周边区域的预设区域设置有保护层,所述预设区域至少包括设置有信号走线的区域。
可选的,所述保护层是采用金属或金属氧化物制备的。
可选的,所述金属氧化物包括氧化铟锡或氧化铟锌。
可选的,所述阵列基板的周边区域设置有栅极金属层、栅极绝缘层、源漏金属层、钝化层及所述保护层。
可选的,所述阵列基板的显示区域设置有栅极金属层、栅极绝缘层、有源层、源漏金属层、钝化层及像素电极,所述保护层与所述像素电极同层绝缘布置。
可选的,所述信号走线分布于所述源漏金属层和/或栅极金属层中。
可选的,所述信号走线包括布置于栅极金属层的公共电极走线和栅极走线,以及布置于所述源漏金属层的数据走线。
可选的,所述保护层通过位于所述钝化层的第二过孔和位于栅极绝缘层的第一过孔与所述公共电极走线电连接。
可选的,所述阵列基板的显示区域设置有相对绝缘设置的公共电极和像素电极;所述保护层与所述公共电极或像素电极同层绝缘布置。
可选的,所述信号走线分布于所述源漏金属层和/或栅极金属层中。
可选的,所述信号走线包括布置于栅极金属层的公共电极走线和栅极走线,以及布置于所述源漏金属层的数据走线。
可选的,所述阵列基板的显示区域还设置有栅极金属层、栅极绝缘层、有源层、源漏金属层、绝缘层、以及位于所述公共电极及所述像素电极之间的钝化层。
本发明的另一个目的在于提供一种上述阵列基板的制备方法,包括如下步骤:
在衬底基板上形成薄膜晶体管;
在形成薄膜晶体管的衬底基板上通过构图工艺形成像素电极和/或公共电极;其中,所述保护层与所述像素电极或公共电极采用一次构图工艺形成。
可选的,包括以下步骤:
在衬底基板上通过构图工艺在所述阵列基板的显示区域形成栅极图形及与所述栅极同层布置的位于所述阵列基板的周边区域的栅极走线和公共电极走线的图形;
通过构图工艺形成栅极绝缘层的图形,其中,在所述阵列基板的周边区域形成第一过孔;
通过构图工艺形成有源层的图形;
通过构图工艺在所述阵列基板的显示区域形成源漏极图形及与所述源漏极同层布置的位于所述阵列基板的周边区域的数据走线的图形;
通过构图工艺形成钝化层的图形,其中,在所述钝化层位于所述阵列基板的周边区域的对应位置形成与所述栅极绝缘层的第一过孔相对应的第二过孔;
在钝化层上通过一次构图工艺形成在所述阵列基板的显示区域形成像素电极,在所述阵列基板的周边区域形成保护层,其中,所述保护层通过所述第一过孔和所述第二过孔与所述公共电极走线连接。
可选的,包括以下步骤:
在衬底基板上通过构图工艺在所述阵列基板的显示区域形成栅极图形及与所述栅极同层布置的位于所述阵列基板的周边区域的栅极走线和公共电极走线的图形;
通过构图工艺形成栅极绝缘层的图形;
通过构图工艺形成有源层的图形;
通过构图工艺在所述阵列基板的显示区域形成源漏极图形及与所述源漏极同层布置的位于所述阵列基板的周边区域的数据走线的图形;
形成绝缘层;
在绝缘层上通过构图工艺形成公共电极或像素电极;
在公共电极或像素电极上形成钝化层;
在钝化层上通过一次构图工艺在所述阵列基板的显示区域形成对应的像素电极或公共电极,其中,在所述阵列基板的周边区域形成保护层。
本发明的另一个目的在于提供本发明的另一个目的在于提供一种显示面板,包括上述的阵列基板。
本发明的另一个目的在于提供本发明的另一个目的在于提供一种显示装置,包括上述的显示面板。
本发明提供的阵列基板及其制备方法、显示面板、显示装置,由于在周边区域的与封框胶接触的部分设有保护层,当封框胶8中含有金球或硅球时,能防止上述金球,或硅球和/或玻璃纤维等支撑物刺破钝化层,进而造成信号走线的短路或断裂。
附图说明
图1为现有技术中TN型显示器的结构示意图;
图2为现有技术中ADS型显示器的结构示意图;
图3为本实施例1或3中TN型显示器的结构示意图;
图4为本实施例2或4中ADS型显示器的结构示意图;
其中,
1.阵列基板玻璃;2.公共电极走线;21.栅极走线;3.栅极绝缘层;4.数据走线;5.钝化层;6.像素电极;61.连接层;62.保护层;7.取向层;8.封框胶;81.金球;9.公共电极;10.绝缘层;11.黑矩阵;12.像素;13.彩膜基板玻璃。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。需要说明的是,附图和具体实施方式中仅是为了更好的说明本发明,且仅为部分实现方式,并非对本发明的限制。
实施例1:
如图3所示,本实施例提供一种阵列基板,包括显示区域和周边区域,所述周边区域设置有信号走线,在周边区域的预设区域设置有保护层62,所述预设区域至少包括设置有信号走线的区域。
本实施例提供的阵列基板,由于在周边区域的预设区域设有保护层62,所述的保护层62能够阻止封框胶8中的金球81,在受压后对阵列基板的信号走线产生不良影响。也就是说,能防止上述金球81刺破钝化层5,进而造成信号走线的短路。
可选的,所述保护层62是采用金属或金属氧化物制备的。一般情况下金属或金属氧化物硬度大,同时、对应TN型显示器还需要保护层62具有导电功能,因为需要将公共电极信号通过保护层62传递到彩膜基板上公共电极9上。
可选的,所述金属氧化物包括氧化铟锡或氧化铟锌。应当理解的是,保护层62可以独立的采用一次构图工艺制备,但是,如图3所示,当保护层62与同层设置的像素电极6都是采用氧化铟锡或氧化铟锌制备时,能够采用一次构图工艺形成,节省工艺步骤、降低制备成本。
对于TN型显示器,所述阵列基板的周边区域设置有栅极金属层、栅极绝缘层3、源漏金属层、钝化层5及所述保护层62。应当理解的是,上述功能层的具体布置可以按现有技术能实现的方式进行布置。应当理解的是,上述的功能层可以和显示区域对应的功能层同时形成,在构图中保留上述的功能层,显示区域还可以包括其它功能层,例如,有源层等。
作为具体的实施方式的一种,如图3所示,所述阵列基板的周边区域沿所述保护层62至衬底方向依次设置钝化层5、源漏金属层(与数据走线4同层)、栅极绝缘层3、栅极金属层(与公共电极走线2和栅极走线21同层)。其中,保护层62与显示区域的像素电极6同层绝缘布置。
应当理解的是,上述各信号走线也可以按需要在不同的金属层中进行调整,在此不作限定。
应当理解的是,本实施例以底栅型的结构进行介绍,实质上顶栅型的结构也是适合的,在此不作限定。
可选的,所述信号走线分布于所述源漏金属层和/或栅极金属层中。
可选的,所述信号走线包括布置于栅极金属层的公共电极走线2和栅极走线21,以及布置于所述源漏金属层的数据走线4。应当理解的是,上述走线的布置也可以采用其它方式,在此不作限定。
可选的,所述保护层62通过位于所述钝化层5的第二过孔和位于栅极绝缘层3的第一过孔与所述公共电极走线2电连接。这样就能使公共电极走线2的信号通过保护层62传递到彩膜基板上的公共电极9上。
这样封框胶8中的金球81与保护层62接触时,控制公共电极9的信号从公共电极走线2传递至保护层62,并经过与保护层62接触的金球81传递至彩膜基板的上的公共电极9,从而控制液晶的分子的偏转、实现显示。
如图3所示,由于所述保护层62与像素电极6同层绝缘布置(在封框胶8靠近显示区域的部分保护层62和像素电极6隔离布置),这样公共电极9信号和像素电极6的信号不会相互影响,同样,为了使保护层62和与栅极同层设置的公共电极走线2连接,保护层62通过位于栅极绝缘层3的第一过孔和位于钝化层5的第二过孔与公共电极走线2连接。
可选的,所述阵列基板的显示区域对应设置有栅极金属层、栅极绝缘层3、有源层(未示出)、源漏金属层、钝化层5及像素电极6,所述保护层62与所述像素电极6同层绝缘布置。其中,在源漏金属层中形成同层间隔设置的源极和漏极,其中,源极通入数据线信号,漏极连接像素电极6;
在栅极金属层形成栅极,栅极中通入扫描信号,通过扫描信号控制有源层的导通进而控制数据信号向像素电极6的传递,结合公共电极9的信号在像素电极6和公共电极9形成控制液晶的电场,从而实现液晶分子偏转的控制。
应当理解的是,薄膜晶体管的结构为现有技术范畴,在此不再一一赘述。
实施例2:
如图4所示,本实施例提供一种阵列基板,包括显示区域和周边区域,所述周边区域设置有信号走线,在周边区域的预设区域设置有保护层62,所述预设区域至少包括设置有信号走线的区域。
本实施例提供的阵列基板,由于在周边区域的预设区域设有保护层62,所述的保护层62能够阻止封框胶8中硅球82和/或玻璃纤维等支撑物在受压后对阵列基板的信号走线产生不良影响。也就是说,能防止上述硅球82和/或玻璃纤维等支撑物刺破钝化层5,进而造成信号走线的断裂。
可选的,所述保护层62是采用金属或金属氧化物制备的。一般情况下金属或金属氧化物硬度大,保护能力更强。
可选的,所述金属氧化物包括氧化铟锡或氧化铟锌。应当理解的是,保护层62可以独立的采用一次构图工艺制备,但是,如图4所示,当保护层62与同层设置的公共电极9(根据布置不同也可以是像素电极6)都是采用氧化铟锡或氧化铟锌制备时,能够采用一次构图工艺形成,节省工艺步骤、降低制备成本。
具体地,对于ADS型显示器,所述阵列基板的周边区域设置有栅极金属层(与公共电极走线2和栅极走线21同层)、栅极绝缘层3、源漏金属层(与数据走线4同层)、钝化层5及所述保护层62(与像素电极6或公共电极9同层)。应当理解的是,上述功能层的具体布置可以按现有技术能实现的方式进行布置。
应当理解的是,上述的功能层可以和显示区域对应的功能层同时形成的,只是在构图中保留上述的功能层,显示区域还可以包括其它功能层,例如,有源层等。
作为具体的实施方式的一种,如图4所示,所述阵列基板的周边区域沿所述保护层62至衬底方向依次设置钝化层5、源漏金属层(与数据走线4同层)、栅极绝缘层3、栅极金属层(与公共电极走线2和栅极走线21同层)。其中,保护层62与显示区域的公共电极9同层绝缘布置。作为结构的变形保护层62也可以与显示区域的公共电极9同层绝缘布置,只需要将保护层62与显示区域的公共电极9和像素电极6中远离阵列基板衬底玻璃的一层同层布置即可。
应当理解的是,上述各信号走线也可以按需要在不同的金属层中进行调整,在此不作限定。
应当理解的是,本实施例以底栅型的结构进行介绍,实质上顶栅型的结构也是适合的,在此不作限定。
可选的,所述阵列基板的显示区域设置有相对绝缘设置的公共电极9和像素电极6;所述保护层62与所述公共电极9或像素电极6同层绝缘布置。只需要将保护层62与显示区域的公共电极9和像素电极6中远离阵列基板衬底玻璃的一层同层布置即可。这样可以采用一次构图工艺形成保护层62,从而节省工艺步骤、降低制备成本。
可选的,所述信号走线分布于所述源漏金属层和/或栅极金属层中。
可选的,所述信号走线包括布置于栅极金属层的公共电极走线2和栅极走线21,以及布置于所述源漏金属层的数据走线4。应当理解的是,上述走线的布置也可以采用其它方式,在此不作限定。
可选的,所述阵列基板的显示区域还设置有栅极金属层、栅极绝缘层3、有源层(未示出)、源漏金属层、绝缘层(未示出)、以及位于所述公共电极9及所述像素电极6之间的钝化层5。其中,在源漏金属层中形成同层间隔设置的源极和漏极,其中,源极通入数据线信号,漏极连接像素电极6;
在栅极金属层形成栅极,栅极中通入扫描信号,通过扫描信号控制有源层的导通进而控制数据信号向像素电极6的传递,结合公共电极9的信号在像素电极6和公共电极9形成控制液晶的电场,从而实现液晶分子偏转的控制。
应当理解的是,薄膜晶体管的结构为现有技术范畴,在此不再一一赘述。
实施例3
本实施例提供一种阵列基板的制备方法,包括如下步骤:
在衬底基板上形成薄膜晶体管;
在形成薄膜晶体管的衬底基板上通过构图工艺形成像素电极6;其中,所述保护层62与所述像素电极6采用一次构图工艺形成。通过一次构图工艺形成保护层62和像素电极6,从而节省工艺步骤、降低制备成本。
可选的,包括以下步骤:
在衬底基板上通过构图工艺在所述阵列基板的显示区域形成栅极图形及与所述栅极同层布置的位于所述阵列基板的周边区域的栅极走线21和公共电极走线2的图形;
通过构图工艺形成栅极绝缘层3的图形,其中,在所述阵列基板的周边区域形成第一过孔;
通过构图工艺形成有源层的图形;
通过构图工艺在所述阵列基板的显示区域形成源漏极图形及与所述源漏极同层布置的位于所述阵列基板的周边区域的数据走线4的图形;
通过构图工艺形成钝化层5的图形,其中,在所述钝化层5位于所述阵列基板的周边区域的对应位置形成与所述栅极绝缘层3的第一过孔相对应的第二过孔;
在钝化层5上通过一次构图工艺形成在所述阵列基板的显示区域形成像素电极6,在所述阵列基板的周边区域形成保护层62,其中,所述保护层62通过所述第一过孔和所述第二过孔与所述公共电极走线2连接。
具体地,以TN型阵列基板的制作过程为例进行介绍:
(1)在阵列基板玻璃1上,通过溅射或热蒸发等方法,沉积一层缓冲层薄膜和铜薄膜,缓冲层薄膜的厚度约为100~1000A,缓冲层薄膜的材质可以包括金属Ta、Cr、Mo、W、Nb等金属,或者合金,或者透明导电薄膜。其中,铜层薄膜的厚度约为1000~5000A。
然后通过涂光刻胶、曝光、显影和湿法刻蚀及剥离工艺得到显示区域的栅极、周边区域的栅极走线21和公共电极走线2等与栅金属层同层设置的其它走线的图形。
(2)在完成步骤(1)的基板上,通过等离子体增强化学气相沉积法形成栅极绝缘层3、半导体层、欧姆接触层的薄膜。其中,栅极绝缘层3薄膜的厚度具体可为1000~4000A,栅极绝缘层3的材质具体可以包括氮化物SiNx或者氮氧化合物(SiOxNy),或者是氮化物(SiNx)和氮氧化合物(SiOxNy)的复合物等。半导体层薄膜的厚度具体可为1000~4000A。欧姆接触层薄膜的厚度具体可为500~1000A。
然后通过涂光刻胶、曝光、显影和干法刻蚀及剥离工艺得到显示区域的薄膜晶体管的沟道。而对于周边区域半导体层和欧姆接触层均通过光刻工艺去除,形成位于栅极绝缘层3中第一过孔。
(3)接着通过溅射或热蒸发的方法依次沉积上厚度约为100~1000A金属Ta、Cr、Mo、W、Nb等金属、或合金、或者透明导电薄膜作为缓冲层,然后再沉积厚度约为1000~5000A的铜层,或由多层金属组成源漏极金属层。
然后通过涂光刻胶、曝光、显影和湿法刻蚀及剥离工艺得到显示区域的源极、漏极。在周边区域形成数据走线4等与源漏金属层同层设置的其它走线。
(4)完成步骤(3)的阵列基板上通过等离子体增强化学气相沉积法沉积厚度约为700~5000A的钝化层5,并通过构图工艺形成钝化层5的图形,例如,第二过孔。钝化层5的材质具体可以包括氧化物、氮化物或者氧氮化合物等。
(5)在完成步骤(4)的阵列基板上,通过溅射或热蒸发等方法沉积一层厚度约为300~1000A的透明导电层。透明导电层的材质具体可以包括氧化铟锡、或者氧化铟锌、或者其它金属及金属氧化物。
通过一次构图工艺形成显示区域的像素电极6和周边区域的保护层62的图形。这样保护层62不用单独采用一次构图工艺形成,可以节省一次构图工艺。
继续制备阵列基板所需的其它必要功能层,在此不再一一赘述。
应当理解的是,上述工艺是采用五次曝光工艺形成的,此外还可以采用四次曝光工艺制作。即:
完成步骤(2)栅极绝缘层3、半导体层、欧姆接触层的薄膜的沉积后不进行曝光和刻蚀工艺,接着通过溅射或热蒸发的方法依次沉积缓冲层和铜层。后续,可采用半色调或灰色调掩模板曝光显影工艺,经过多步刻蚀之后形成栅极绝缘层3、半导体层、欧姆接触层、源漏极金属层,以及与其中的金属层同层设置的信号走线等在显示区域和周边区域对应的图形。其余工序没有变化。
经过上述步骤形成如图3所示的阵列基板,与封框胶8接触保护层62与像素电极6采用一次构图工艺形成。这样能够减少一次构图工艺,节省制造成本。
实施例4:
本实施例提供一种阵列基板的制备方法,包括如下步骤:
在衬底基板上形成薄膜晶体管;
在形成薄膜晶体管的衬底基板上通过构图工艺形成像素电极6;其中,所述保护层62与所述像素电极6或公共电极9采用一次构图工艺形成。通过一次构图工艺形成保护层62和像素电极6或公共电极9,从而节省工艺步骤、降低制备成本。
具体地,包括以下步骤:
在衬底基板上通过构图工艺在所述阵列基板的显示区域形成栅极图形及与所述栅极同层布置的位于所述阵列基板的周边区域的栅极走线21和公共电极走线2的图形;
通过构图工艺形成栅极绝缘层3的图形;
通过构图工艺形成有源层的图形;
通过构图工艺在所述阵列基板的显示区域形成源漏极图形及与所述源漏极同层布置的位于所述阵列基板的周边区域的数据走线4的图形;
形成绝缘层;
在绝缘层上通过构图工艺形成公共电极9或像素电极6;
在公共电极9或像素电极6上形成钝化层5;
在钝化层5上通过一次构图工艺在所述阵列基板的显示区域形成对应的像素电极6或公共电极9,其中,在所述阵列基板的周边区域形成保护层62。
如图4所示,ADS型阵列基板的制备方法与TN型的阵列基板的制备方法类似,在此不再一一赘述,保护层62与公共电极9采用一次构图工艺形成,这样能够减少一次构图工艺,节省制造成本。应当理解的是,将上述公共电极9和像素电极6的位置交换也是适用的,只需要将保护层62与显示区域的公共电极9和像素电极6中远离阵列基板衬底玻璃的一层同层布置即可。
实施例5:
本实施例提供一种显示面板,包括上述阵列基板。对于TN型或ADS型,显示面板包括上述的阵列基板,以及与该阵列基板对盒的彩膜基板,还可以为,将彩膜层集成于阵列基板,则显示面板包括阵列基板和对向基板,此外,显示面板的形式还可以为现有可实现的一些其他方式,这里不做限定。
实施例6:
本实施例提供一种显示装置,包括上述显示面板。显示装置可以包括电视、电脑、手机、数码相机、ATM机、电子广告牌等各种具有显示功能的装置。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (17)
1.一种阵列基板,包括显示区域和周边区域,所述周边区域设置有信号走线,其特征在于,在周边区域的预设区域设置有保护层,所述预设区域至少包括设置有信号走线的区域。
2.如权利要求1所述的阵列基板,其特征在于,所述保护层是采用金属或金属氧化物制备的。
3.如权利要求2所述的阵列基板,其特征在于,所述金属氧化物包括氧化铟锡或氧化铟锌。
4.如权利要求1所述的阵列基板,其特征在于,所述阵列基板的周边区域设置有栅极金属层、栅极绝缘层、源漏金属层、钝化层及所述保护层。
5.如权利要求4所述的阵列基板,其特征在于,所述阵列基板的显示区域设置有栅极金属层、栅极绝缘层、有源层、源漏金属层、钝化层及像素电极,所述保护层与所述像素电极同层绝缘布置。
6.如权利要求5所述的阵列基板,其特征在于,所述信号走线分布于所述源漏金属层和/或栅极金属层中。
7.如权利要求6所述的阵列基板,其特征在于,所述信号走线包括布置于栅极金属层的公共电极走线和栅极走线,以及布置于所述源漏金属层的数据走线。
8.如权利要求7所述的阵列基板,其特征在于,所述保护层通过位于所述钝化层的第二过孔和位于栅极绝缘层的第一过孔与所述公共电极走线电连接。
9.如权利要求4所述的阵列基板,其特征在于,所述阵列基板的显示区域设置有相对绝缘设置的公共电极和像素电极;所述保护层与所述公共电极或像素电极同层绝缘布置。
10.如权利要求9所述的阵列基板,其特征在于,所述信号走线分布于所述源漏金属层和/或栅极金属层中。
11.如权利要求10所述的阵列基板,其特征在于,所述信号走线包括布置于栅极金属层的公共电极走线和栅极走线,以及布置于所述源漏金属层的数据走线。
12.如权利要求9所述的阵列基板,其特征在于,所述阵列基板的显示区域还设置有栅极金属层、栅极绝缘层、有源层、源漏金属层、绝缘层、以及位于所述公共电极及所述像素电极之间的钝化层。
13.一种如权利要求1-12任一项所述的阵列基板的制备方法,其特征在于,包括如下步骤:
在衬底基板上形成薄膜晶体管;
在形成薄膜晶体管的衬底基板上通过构图工艺形成像素电极和/或公共电极;其中,所述保护层与所述像素电极或公共电极采用一次构图工艺形成。
14.如权利要求13所述的阵列基板的制备方法,其特征在于,包括以下步骤:
在衬底基板上通过构图工艺在所述阵列基板的显示区域形成栅极图形及与所述栅极同层布置的位于所述阵列基板的周边区域的栅极走线和公共电极走线的图形;
通过构图工艺形成栅极绝缘层的图形,其中,在所述阵列基板的周边区域形成第一过孔;
通过构图工艺形成有源层的图形;
通过构图工艺在所述阵列基板的显示区域形成源漏极图形及与所述源漏极同层布置的位于所述阵列基板的周边区域的数据走线的图形;
通过构图工艺形成钝化层的图形,其中,在所述钝化层位于所述阵列基板的周边区域的对应位置形成与所述栅极绝缘层的第一过孔相对应的第二过孔;
在钝化层上通过一次构图工艺形成在所述阵列基板的显示区域形成像素电极,在所述阵列基板的周边区域形成保护层,其中,所述保护层通过所述第一过孔和所述第二过孔与所述公共电极走线连接。
15.如权利要求13所述的阵列基板的制备方法,其特征在于,包括以下步骤:
在衬底基板上通过构图工艺在所述阵列基板的显示区域形成栅极图形及与所述栅极同层布置的位于所述阵列基板的周边区域的栅极走线和公共电极走线的图形;
通过构图工艺形成栅极绝缘层的图形;
通过构图工艺形成有源层的图形;
通过构图工艺在所述阵列基板的显示区域形成源漏极图形及与所述源漏极同层布置的位于所述阵列基板的周边区域的数据走线的图形;
形成绝缘层;
在绝缘层上通过构图工艺形成公共电极或像素电极;
在公共电极或像素电极上形成钝化层;
在钝化层上通过一次构图工艺在所述阵列基板的显示区域形成对应的像素电极或公共电极,以及在所述阵列基板的周边区域形成保护层。
16.一种显示面板,其特征在于,包括如权利要求1-12任一项所述的阵列基板。
17.一种显示装置,其特征在于,包括如权利要求16所述的显示面板。
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WO2017041478A1 (zh) * | 2015-09-11 | 2017-03-16 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法、显示面板、显示装置 |
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CN107170754A (zh) * | 2017-05-15 | 2017-09-15 | 京东方科技集团股份有限公司 | 显示装置、阵列基板及阵列基板制作方法 |
CN107024809A (zh) * | 2017-05-27 | 2017-08-08 | 深圳市华星光电技术有限公司 | 液晶盒透镜面板及液晶显示装置 |
CN108196409B (zh) * | 2018-01-02 | 2022-01-28 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板、显示装置和制作方法 |
CN108196409A (zh) * | 2018-01-02 | 2018-06-22 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板、显示装置和制作方法 |
CN109358459A (zh) * | 2018-11-09 | 2019-02-19 | 惠科股份有限公司 | 一种显示面板、制作方法和显示装置 |
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CN110098199B (zh) * | 2019-05-05 | 2022-04-05 | 深圳市华星光电半导体显示技术有限公司 | 显示面板及显示装置 |
US11462570B2 (en) | 2019-05-05 | 2022-10-04 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
CN113703235A (zh) * | 2021-07-30 | 2021-11-26 | 惠科股份有限公司 | 阵列基板、阵列基板的制作工艺及显示面板 |
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US20170285430A1 (en) | 2017-10-05 |
WO2017041478A1 (zh) | 2017-03-16 |
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