CN105009268A - 用于在低温下进行半导体测试的方法及设备 - Google Patents

用于在低温下进行半导体测试的方法及设备 Download PDF

Info

Publication number
CN105009268A
CN105009268A CN201480013752.XA CN201480013752A CN105009268A CN 105009268 A CN105009268 A CN 105009268A CN 201480013752 A CN201480013752 A CN 201480013752A CN 105009268 A CN105009268 A CN 105009268A
Authority
CN
China
Prior art keywords
adhesive tape
band
test
semiconductor device
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480013752.XA
Other languages
English (en)
Other versions
CN105009268B (zh
Inventor
圣提·巴特森诺英
尤特哈那·吉塔布
菲沙努·桑巴克朗
马努斯恰·恰诺克
普拉希特·斯里普拉瑟特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of CN105009268A publication Critical patent/CN105009268A/zh
Application granted granted Critical
Publication of CN105009268B publication Critical patent/CN105009268B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • G01R1/0408Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Dicing (AREA)
  • Adhesive Tapes (AREA)

Abstract

本发明揭示一种用于测试布置在条带上的多个半导体装置的方法,其可包含在框架(105)上形成半导体装置(104)阵列,其中邻近半导体装置的接触衬垫被短接;部分切割所述条带以电隔离在所述阵列中的个别半导体装置;将所述条带放置在经配置以耐受低温(例如,低于-20℃或低于-50℃)的胶带(120)上;在测试夹头(110)上布置所述条带及胶带;将所述测试夹头、条带及胶带暴露于低于环境温度的温度且当暴露于低温时,测试所述多个半导体装置。在一个实施例中,将KAPTONTM膜用作所述胶带。

Description

用于在低温下进行半导体测试的方法及设备
相关申请案的交叉参考
本申请案主张2013年3月14日申请的第61/784,499号美国临时申请案的权益,所述临时申请案全文并入本文中。
技术领域
本发明涉及一种用于半导体测试的方法,特定来说,涉及用于低温下在膜框架上的无引线封装隔离(部分切割)条带的测试的方法。
背景技术
用于半导体装置的无引线封装是(例如)四侧扁平无引线(QFN)或双侧扁平无引线(DFN)封装。此类装置包括半导体裸片,半导体裸片位于无引线的模制外壳内。外壳包括并非从外壳延伸的接触衬垫。在制造工艺中,多个这些装置放置在相应QFN/DFN金属“引线框架”上,且被共同模制以形成如图1中展示的包含多个装置的矩阵的条带。
在常规QFN/DFN组装过程中,所述模制条带中的半导体装置被短接在一起且因此不允许测试。因此,为将如图1中展示的这种条带处理为所谓的条带测试形式,在测试之前,半导体装置需要被至少部分隔离。这通常通过锯切刀片、激光或水刀完成。图2展示在部分隔离之后,布置在条带中的若干半导体装置的放大图。如展示,在分离邻近半导体装置的接触衬垫的位置处切割装置。常常在此种部分隔离过程之后发现某种条带翘曲。然而,仍可在用于环境温度或高温条带测试的相应机器中将所述条带用于测试。
某些半导体装置(例如,用于汽车工业的装置)需要在低温下的测试。然而,当暴露于低温(例如在环境室中在低于-20℃的温度下)时,归因于金属引线框架(条带)的性质,隔离(部分切割)条带可经历显著翘曲。归因于由此类低温导致的翘曲,无法适当执行测试,(例如)这是因为翘曲将导致在常规条带测试输送装置(test handler)中的真空机制失效。图3A及3B展示在暴露于低温之后的翘曲条带的实例。由于这个原因,许多半导体制造商将隔离条带的测试限于环境温度测试且不执行低温下的测试。
用于低温下的条带测试的另一已尝试的解决方案是在装置完全分离(单切)之后,将半导体装置留在膜框架上,且对经单切装置执行低温测试。然而,在单切过程期间的胶带变形会影响装置之间的对准及/或间隔,导致在后续从框架拣取装置期间的问题且限制了并行测试的数目。
因此,需要改进的制造及/或组装工序以允许低温测试在无引线封装中的半导体装置,例如,布置在隔离(部分切割)条带中的半导体装置。
发明内容
一个实施例提供一种用于测试布置在条带上的多个半导体装置的方法,其可包含:在框架上形成半导体装置阵列,其中邻近半导体装置的接触衬垫被短接;部分切割条带以电隔离阵列中的个别半导体装置;将条带放置在经配置以在低到-20℃以下的温度下使用的胶带上;在测试夹头上布置条带及胶带;将测试夹头、条带及胶带暴露于低于环境温度的温度,且当暴露于低温时,测试多个半导体装置。
胶带在UV固化之前可具大于1,200gf/in的粘着力及/或在UV固化之后可具小于10gf/in的粘着力。胶带经配置以可耐受低达-50℃的温度而不改变布置在胶带上的半导体装置的任何热性质。举例来说,KAPTONTM膜可用作胶带。
另一实施例提供一种用于在低温下测试半导体装置的设备,其包括测试夹头;胶带,其布置在测试夹头上;及经隔离测试条带,其布置在胶带上,经隔离测试条带包括在框架上的半导体装置阵列,且经部分切割以电隔离阵列中的邻近半导体装置。胶带经配置以在低到-20℃以下或低到-50℃的温度下使用。举例来说,KAPTONTM膜可用作胶带。另外,可在胶带上方及环绕条带布置金属框架。
附图说明
以下参考图式讨论实例实施例,其中:
图1说明包含布置在位于金属引线框架上的阵列中的多个半导体装置的实例条带;
图2展示图1的条带的一部分的放大图,其中通过锯切刀片、激光或水刀形成的切割线而部分隔离邻近半导体装置以形成隔离条带;
图3A及3B展示布置在测试夹头上的图2的隔离条带,其中隔离条带由于暴露于低温而翘曲;
图4A及4B说明根据实例实施例的用于部分切割测试条带的低温测试的实例设备,其包含用于在低温测试期间将部分切割测试条带固定到测试条带的胶带;及
图5说明使用如图4A及4B中展示的实例设备的低温测试过程的实例方法200。
具体实施方式
如上讨论,本发明提供用于经隔离(部分切割)半导体装置测试条带的低温测试的实施例,其可避免或减少与常规技术相关联的问题,例如在低温暴露期间的引线框架翘曲的问题。
根据各种实施例,为了消除半导体装置条带在低温下的翘曲,使用特殊胶带将半导体装置测试条带固定到测试夹头,且应用框架。在一些实施例中,条带仅被部分切割以将装置维持在其预期的位置及芯片到芯片间隔处,以适于执行适当测试。接着在条带胶带组合件上方放置框架。这个措施已证明是有效的且具有长期可靠性而不会改变IC测试条带的任何产品特性。
图4A及4B说明根据实例实施例的用于部分切割测试条带的低温测试的实例设备100。图4A展示设备100的分解图,而图4B展示设备100的部分组装图。如所展示,设备100包含测试条带102,其包含在引线框架105上的半导体装置(例如,芯片)104的二维阵列;测试夹头110,其用于支撑测试条带102;胶带(或膜)120;及任选金属框架124。将胶带120应用到测试夹头110的顶部表面,且接着将测试条带102安装到胶带120上。还可以环绕测试条带102的方式将任选金属框架124安装到胶带120上。
如通过邻近半导体装置104之间的切割线106指示,可例如利用锯切刀片、激光或水刀部分切割测试条带102以使个别半导体装置104彼此隔离。提供这种隔离以避免在测试期间在半导体装置104之间的短路。
胶带或膜130可经配置以耐受低温(例如,低到-20℃以下或甚至低于-50℃),同时维持充分粘着力且不改变上覆半导体装置104的任何热性质。在一些实施例中,胶带130在环境温度及低温(例如低于-20℃或低于-50℃)两者下提供在测试夹头110与测试条带框架105(例如,SUS304不锈钢)之间的大于1,200gf/in的粘着力。这种粘着力可减少或消除在全部测试温度下隔离(部分切割)测试条带102变形(例如,翘曲)的可能性。在一些实施例中,在UV固化之后,胶带130还提供在胶带130与测试条带框架105之间的小于10gf/in的粘着力,其实质上减少或消除了在胶带拆卸过程之后剩余在测试条带引线框架105上的残余物。在一些实施例中,胶带130是KAPTONTM膜。
图5说明使用如图4A及4B中展示的实例设备100的低温测试过程的实例方法200。在步骤202中,形成具有模制囊封的DFN/QFN引线框架条带。在步骤204处执行条带锯切安装。接着,在步骤206处,在测试条带上执行部分切割以形成如图4A及4B中展示的隔离测试条带102。在步骤208处,接着如图4A及4B中展示,使用胶带130将隔离测试条带102安装到测试夹头110。在步骤210处,在环境温度、高温及低温(例如,低于-20℃或低于-50℃)下测试被安装测试条带102。接着在步骤212处执行UV擦除。在步骤214处,接着可执行胶带拆卸及条带标记。在步骤216处,测试条带可被锯切安装及单切。最终,在步骤218处,经单切装置(例如,芯片)可被检验且放置到管或卷盘中。
图4A及4B的布置及图5的过程可允许增加低温膜框架测试的DFN/QFN并行性。另外,可消除关于广范围温度测试的封装大小限制。最后,可减少或消除转换时间或转换工具成本。
尽管本发明中详细描述所揭示的实施例,但应了解,在不背离实施例的精神及范围的情况下,可对实施例做出各种改变、取代及变更。

Claims (14)

1.一种用于测试布置在条带上的多个半导体装置的方法,其包括:
在框架上形成半导体装置阵列,其中邻近半导体装置的接触衬垫被短接;
部分切割所述条带以电隔离所述阵列中的个别半导体装置;
将所述条带放置在经配置以在低到-20℃以下的温度下使用的胶带上;
将所述条带及所述胶带布置在测试夹头上;
将所述测试夹头、所述条带及所述胶带暴露于低于环境温度的温度;以及
当暴露于低温时,测试所述多个半导体装置。
2.根据权利要求1所述的方法,其进一步包括将金属框架环绕所述条带放置在所述胶带上。
3.根据权利要求1所述的方法,其中所述条带被部分锯切,使得侧轨保持在所述条带上。
4.根据权利要求1所述的方法,其中所述胶带在UV固化之前具有大于1,200gf/in的粘着力。
5.根据权利要求1所述的方法,其中所述胶带在UV固化之后具有小于10gf/in的粘着力。
6.根据权利要求1所述的方法,其中所述胶带经配置以耐受高达-50℃的温度而不改变布置在所述胶带上的所述半导体装置的任何热性质。
7.根据权利要求1所述的方法,其中所述胶带是KAPTONTM膜。
8.一种用于在低温下测试半导体装置的设备,其包括:
测试夹头;
胶带,其布置在所述测试夹头上;以及
经隔离测试条带,其布置在所述胶带上,所述经隔离测试条带包括在框架上的半导体装置阵列且被部分切割以电隔离在所述阵列中的邻近半导体装置;
其中所述胶带经配置以在低到-20℃以下的温度下使用。
9.根据权利要求8所述的设备,其进一步包括布置在所述胶带上且环绕所述条带的金属框架。
10.根据权利要求8所述的设备,其中所述条带经部分锯切,使得侧轨保持在所述条带上。
11.根据权利要求8所述的设备,其中所述胶带在UV固化之前具有大于1,200gf/in的粘着力。
12.根据权利要求8所述的设备,其中所述胶带在UV固化之后具有小于10gf/in的粘着力。
13.根据权利要求8所述的设备,其中所述胶带经配置以耐受高达-50℃的温度而不改变布置在所述胶带上的所述半导体装置的任何热性质。
14.根据权利要求8所述的设备,其中所述胶带是KAPTONTM膜。
CN201480013752.XA 2013-03-14 2014-03-12 用于在低温下进行半导体测试的方法及设备 Active CN105009268B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361784499P 2013-03-14 2013-03-14
US61/784,499 2013-03-14
US14/204,123 2014-03-11
US14/204,123 US9224659B2 (en) 2013-03-14 2014-03-11 Method and apparatus for semiconductor testing at low temperature
PCT/US2014/024413 WO2014159611A1 (en) 2013-03-14 2014-03-12 Method and apparatus for semiconductor testing at low temperature

Publications (2)

Publication Number Publication Date
CN105009268A true CN105009268A (zh) 2015-10-28
CN105009268B CN105009268B (zh) 2018-07-27

Family

ID=51528888

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480013752.XA Active CN105009268B (zh) 2013-03-14 2014-03-12 用于在低温下进行半导体测试的方法及设备

Country Status (6)

Country Link
US (2) US9224659B2 (zh)
EP (1) EP2973674A1 (zh)
KR (1) KR20150132227A (zh)
CN (1) CN105009268B (zh)
TW (1) TWI619157B (zh)
WO (1) WO2014159611A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111458619A (zh) * 2020-04-15 2020-07-28 长春长光辰芯光电技术有限公司 背照式cmos图像传感器的低温测试方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9224659B2 (en) 2013-03-14 2015-12-29 Microchip Technology Incorporated Method and apparatus for semiconductor testing at low temperature
KR102518092B1 (ko) * 2021-05-03 2023-04-06 매그나칩 반도체 유한회사 디스플레이 드라이버 ic의 신뢰성 테스트 방법
US11906576B1 (en) 2021-05-04 2024-02-20 Johnstech International Corporation Contact assembly array and testing system having contact assembly array
US11867752B1 (en) * 2021-05-13 2024-01-09 Johnstech International Corporation Contact assembly and kelvin testing system having contact assembly

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1433059A (zh) * 2002-01-07 2003-07-30 三星电子株式会社 半导体器件的测试系统
CN1494580A (zh) * 2000-12-01 2004-05-05 3M 交联压敏粘合剂组合物和基于该组合物的用于高温应用的胶粘制品
CN1638079A (zh) * 2003-12-22 2005-07-13 株式会社瑞萨科技 半导体集成电路器件的制造方法
US7442739B1 (en) * 2003-11-12 2008-10-28 Henkel Corporation Hot melt pressure sensitive adhesives
US20120252142A1 (en) * 2011-04-01 2012-10-04 Texas Instruments Incorporated Singulation and Strip Testing of No-Lead Integrated Circuit Packages Without Tape Frame

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247035B2 (en) * 2000-06-20 2007-07-24 Nanonexus, Inc. Enhanced stress metal spring contactor
KR100541729B1 (ko) * 2003-06-23 2006-01-10 삼성전자주식회사 반도체소자 검사장치
JP4191204B2 (ja) * 2006-05-12 2008-12-03 エルピーダメモリ株式会社 半導体装置およびその製造方法
KR20100086673A (ko) * 2009-01-23 2010-08-02 삼성테크윈 주식회사 접착 테이프 및 이를 적용한 반도체 패키지
US20130243715A1 (en) * 2010-11-24 2013-09-19 L'oreal S.A. Compositions containing acrylic thickener and oil
US9224659B2 (en) 2013-03-14 2015-12-29 Microchip Technology Incorporated Method and apparatus for semiconductor testing at low temperature
JP6109032B2 (ja) * 2013-10-02 2017-04-05 三菱電機株式会社 半導体試験治具およびその搬送治具、ならびにそれらを用いた異物除去方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1494580A (zh) * 2000-12-01 2004-05-05 3M 交联压敏粘合剂组合物和基于该组合物的用于高温应用的胶粘制品
CN1433059A (zh) * 2002-01-07 2003-07-30 三星电子株式会社 半导体器件的测试系统
US7442739B1 (en) * 2003-11-12 2008-10-28 Henkel Corporation Hot melt pressure sensitive adhesives
CN1638079A (zh) * 2003-12-22 2005-07-13 株式会社瑞萨科技 半导体集成电路器件的制造方法
US20120252142A1 (en) * 2011-04-01 2012-10-04 Texas Instruments Incorporated Singulation and Strip Testing of No-Lead Integrated Circuit Packages Without Tape Frame

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111458619A (zh) * 2020-04-15 2020-07-28 长春长光辰芯光电技术有限公司 背照式cmos图像传感器的低温测试方法
CN111458619B (zh) * 2020-04-15 2022-07-12 长春长光辰芯光电技术有限公司 背照式cmos图像传感器的低温测试方法

Also Published As

Publication number Publication date
US20160118308A1 (en) 2016-04-28
EP2973674A1 (en) 2016-01-20
WO2014159611A1 (en) 2014-10-02
CN105009268B (zh) 2018-07-27
US9224659B2 (en) 2015-12-29
US9385053B2 (en) 2016-07-05
KR20150132227A (ko) 2015-11-25
US20140273307A1 (en) 2014-09-18
TW201448004A (zh) 2014-12-16
TWI619157B (zh) 2018-03-21

Similar Documents

Publication Publication Date Title
CN105009268A (zh) 用于在低温下进行半导体测试的方法及设备
US7888179B2 (en) Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof
KR102325824B1 (ko) 반도체 장치의 제조방법
US9252063B2 (en) Extended contact area for leadframe strip testing
CN105575825A (zh) 芯片封装方法及封装组件
US20140027772A1 (en) Wafers and Chips Comprising Test Structures
CN108666301A (zh) 为半导体管芯提供电磁干扰屏蔽的线上流动管芯贴装薄膜和传导模塑料
US20150130037A1 (en) Method of Electrically Isolating Shared Leads of a Lead Frame Strip
CN105706215A (zh) 半导体元件的制造方法和半导体元件
US20140291867A1 (en) Apparatus and method to attach a wireless communication device into a semiconductor package
US9754834B2 (en) Method of electrically isolating leads of a lead frame strip by laser beam cutting
US20150325503A1 (en) Method of singularizing packages and leadframe
CN104701156A (zh) 用于在裸片分离过程期间减小背面裸片损坏的方法
CN103730376B (zh) 封装测试方法
KR20140105200A (ko) 기판 스트립
CN108695169B (zh) 制作多个封装半导体器件的方法
US20090325321A1 (en) Reclaiming Packages
TW201413262A (zh) 封裝檢測方法
TW569371B (en) Semiconductor device and manufacturing method therefor
US11596056B2 (en) Methods and devices related to reduced packaging substrate deformation
JP2014049682A (ja) 半導体装置の製造方法
JP2004055765A (ja) Icパッケージの製造方法およびリードフレーム
CN107895715A (zh) 一种硅片晶圆划片后检测工艺
KR20100123414A (ko) 반도체 패키지 및 그 제조방법
KR950015734A (ko) 리드프레임 및 그 리드프레임을 갖는 반도체 장치의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant