CN104995741B - 半导体纳米线的凹槽式接触 - Google Patents

半导体纳米线的凹槽式接触 Download PDF

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CN104995741B
CN104995741B CN201380073253.5A CN201380073253A CN104995741B CN 104995741 B CN104995741 B CN 104995741B CN 201380073253 A CN201380073253 A CN 201380073253A CN 104995741 B CN104995741 B CN 104995741B
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semiconductor nanowires
top surface
nano wire
insulating materials
electrode
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CN104995741A (zh
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I.阿贝里
M.芒努松
D.阿索利
L.I.萨米尔森
J.奥尔松
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Sol Voltaics AB
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Sol Voltaics AB
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Abstract

一种半导体纳米线器件，包括：至少一根半导体纳米线，其具有底面和顶面；绝缘材料，其包围所述半导体纳米线；以及电极，其欧姆接触所述半导体纳米线的顶面。所述电极与所述半导体纳米线的半导体材料的接触由与所述半导体纳米线的顶面的接触占主导。

Description

半导体纳米线的凹槽式接触
相关申请的交叉参考
本申请要求于2012年12月21日提交的序列号为13/723,413的美国非临时专利申请的优先权，其全部公开内容在此以引用的方式并入本文。
技术领域
本发明涉及半导体器件，并且更具体地涉及纳米线半导体器件。
背景技术
传统上，通过将纳米线封装在绝缘体中，然后对绝缘体进行蚀刻以使每根线材的顶端露出来实现轴向纳米线器件的电接触。然后沉积导电材料以形成纳米线的电接触。
本发明人观察到，现有技术中1×1mm2的InP纳米线太阳能电池的平均开路电压Voc比所预期的来自理想的InP太阳能电池(900mV)的显著低(500-700mV)。除了纳米线太阳能电池的平均Voc较低之外，Voc的分布通常是大的，具有若干100mV的标准偏差。因此，具有较高的开路电压且开路电压的小分布的纳米线太阳能电池是所需的。
发明内容
一个实施例涉及半导体纳米线器件，其包括：至少一根半导体纳米线，其具有底面和顶面；绝缘材料，其包围所述半导体纳米线；以及电极，其欧姆接触所述半导体纳米线的顶面。所述电极与所述半导体纳米线的半导体材料的接触由与所述半导体纳米线的顶面的接触占主导。
另一实施例涉及半导体纳米线器件，包括：至少一根半导体纳米线，其具有底面和顶面；绝缘材料，其包围所述半导体纳米线并且延伸到所述纳米线的顶面以上以在所述绝缘材料的侧壁与所述纳米线的顶面之间产生凹槽；以及电极，其填充所述凹槽并且欧姆接触所述纳米线的顶面。
另一实施例涉及制造半导体纳米线器件的方法，包括：形成至少一根半导体纳米线，所述半导体纳米线具有位于所述半导体纳米线的顶面的催化剂粒子或包括顶面的牺牲部分；围绕所述半导体纳米线形成绝缘材料；去除所述催化剂粒子或所述牺牲部分以在所述绝缘材料的顶面下方对所述纳米线的顶面形成凹槽；以及形成与所述纳米线的顶面欧姆接触的电极。
附图说明
图1a-1d是示出(a)顶部具有催化剂粒子、部分由绝缘体覆盖并且全部由透明电极覆盖的现有技术的纳米线，(b)顶部没有催化剂粒子、部分由绝缘体覆盖并且全部由透明电极覆盖的纳米线，(c)顶部具有催化剂粒子、纳米线的全长和催化剂粒子的一部分由绝缘体覆盖并且全部由透明电极覆盖的现有技术的纳米线以及(d)顶部没有催化剂粒子、绝缘体延伸超过纳米线的顶部并且全部由透明电极覆盖的纳米线的示意图。
图2a-2b是示出(a)图1a的纳米线在低偏压/低照明条件下的耗尽区以及(b)图1a的纳米线在高偏压/高照明条件下的耗尽区的示意图。
图3a-3d是(a)图1b或图1d的纳米线并联连接的纳米线器件的电路图，(b)图3a的电路的电流对电压曲线图，(c)图1a或图1c的纳米线并联连接的纳米线器件的电路图，(d)图3c的电路的电流对电压曲线图。
图4a-4d是示出实施例对于传统的纳米线器件的(a)效率、(b)填充因子、(c)开路电压以及(d)电流密度的增加的标绘图。
图5a-5g是示出根据实施例的制造纳米线器件的方法的示意图。
图5h和5i是示出根据可替代实施例制造的纳米线器件的示意性侧横截面视图。
图6a-6b是(a)顶部具有催化剂粒子的纳米线阵列以及(b)去除催化剂粒子并且在纳米线的顶部留下凹槽的纳米线阵列的扫描电子显微镜(SEM)显微图。
图7是对比在纳米线的顶部具有金催化剂粒子和不具有金催化剂粒子的纳米线的作为波长函数的反射率的曲线图。
图8a-8b是示出根据可替代实施例的制造纳米线器件的方法的示意图。
具体实施方式
为了本申请的目的，纳米线是直径(对于圆柱形纳米线而言)或宽度(对于非圆柱形纳米线而言，诸如在垂直于其轴线的平面内具有六边形横截面形状的纳米线)小于1微米，诸如2到500nm，诸如100到300nm的纳米级结构。然而，长度可以为至少0.5微米，诸如0.5到3微米，诸如1到2微米。
高效的太阳能电池由IV族或III-V族材料，诸如但不限于Si、InP和GaAs制成，具有非常接近顶面的pn结。优选地，该pn结从表面的顶部起仅为几个100nm的数量级。这对于半导体纳米线器件也是如此。建模和实验两者都表明，最高效的半导体纳米线太阳能电池具有至少180nm的线径。这样，从接触的角度而言，半导体纳米线可被视为一块小平面材料。
为了从半导体纳米线阵列制成光电器件，诸如LED或太阳能电池，顶部接触优选包含透明的导电氧化物(TCO)。TCO与有源器件之间的接触优选具有尽可能低的电阻，最好是欧姆的。在太阳能电池的情况下，也优选接触本身不具有光学活性，即，接触不应从器件的开路电压(VOC)中减去。
在从诸如Au等金属催化剂生长半导体纳米线的情况下，传统常识是，Au种子粒子有利于形成对纳米线的欧姆接触。因此，通常不去除Au粒子，特别是因为去除将需要额外的处理步骤。然而，已知金属催化剂种子粒子由于遮光性而会降低效率。除了遮光性之外并且与传统常识相反，集成金属粒子也可提供差的电接触。Au被发现对III-V半导体形成肖特基型接触。除可能存在于半导体纳米线中的任何二极管之外，肖特基型接触在电流-电压特性中显示为反向二极管。因此，总器件典型地包括如图1a所示且在下面更详细地讨论的与反向肖特基二极管串联的半导体纳米线二极管。
图1a和1b分别示出了现有技术和本发明第一实施例的纳米线器件。如图1a所示，现有技术的半导体纳米线101是轴向纳米线，其包括具有第一导电类型(例如p型或n型)的第一部分102和具有不同于第一导电类型的第二导电类型(例如n型或p型)的第二部分104。在半导体纳米线101的第一部分102与第二部分104之间的界面处形成pn结103。pn结103具有如图中的二极管附图标记120所指示的二极管的电特性。如果需要，纳米线可包括p-i-n结器件，其中结合区103包括本征半导体或第一或第二导电类型的半导体，其具有一定的掺杂浓度，该掺杂浓度的大小至少为低于区域102和104的的掺杂浓度的大小的数量级。
另外，绝缘或介电层包围半导体纳米线101的侧壁的至少一部分，由此形成围绕半导体纳米线101的绝缘外壳108。在一个实施例中，绝缘外壳108由诸如SiO2的透明材料制成。如果半导体纳米线101通过VLS工艺或使用金属催化剂粒子的其他工艺生长，诸如AerotaxyTM工艺(如已公布的PCT申请WO11/142,717(‘717公布文本)所述的那样，其被让予Qunano AB并且其全部内容在此以引用的方式并入本文)，则金属催化剂粒子106位于半导体纳米线101的第二部分104的顶部上。
如上所述，可在金属催化剂粒子106和半导体纳米线101的第二部分104之间形成反向肖特基二极管122。TCO电极110将包括绝缘外壳108在内的半导体纳米线101封装。在半导体纳米线101的未被绝缘外壳108覆盖的那些部分，可在TCO电极110与半导体纳米线101之间形成直接接触。这种接触通常是欧姆的，如附图标记124所示。另外的欧姆接触可在金属催化剂粒子106与TCO电极110之间形成，如附图标记126所示。欧姆接触连接124与金粒子-纳米线肖特基连接122并联。作为替代，这种接触可形成另一个肖特基二极管，其具有不同于二极管120或反向肖特基二极管122的电特性。
图2a-2b示意性示出了图1a的纳米线在低偏压/低照明条件下的耗尽区140、142(图2a)以及图1a的纳米线在高偏压/高照明条件下的耗尽区(图2b)。如图2a所示，第一耗尽区140形成在半导体纳米线101中的pn结103处。第二耗尽区142由于反向肖特基二极管122而形成。也就是说，反向肖特基二极管122在半导体纳米线101的上部诱导耗尽区142。此外，如图2b所示，耗尽区140、142的厚度随着所施加的电压和/或照明而变化。这样，反向肖特基二极管122可对纳米线侧上的接触产生影响，使接触不仅依赖于工艺变量(例如，Δh1)而且还可能依赖于外力。
图1b示出了在沉积TCO电极110之前去除金属催化剂粒子106的实施例。在此实施例中，在半导体纳米线101的顶面与TCO电极110之间形成欧姆接触128而不是如图1a所示的在半导体纳米线101中形成的反向肖特基二极管122。绝缘外壳108的顶部与半导体纳米线101的顶面101a之间的高度是Δh1，其中Δh1指示对于纳米线末端露出长度的长度而言的典型工艺变量。
在第一实施例的一方面中，半导体纳米线101具有直径或宽度并且TCO电极110在顶面101a的下方接触半导体纳米线101的侧部101b使得侧部101b的长度Δh1小于半导体纳米线101的直径/宽度101c。例如，直径/宽度101c可比侧部101b的长度Δh1大10％-500％，诸如大50-100％。在第一实施例的另一方面中，Δh1等于零，并且没有纳米线的侧部被外壳108露出，使得纳米线与外壳具有大约相同的高度。在这种构造中，电极110仅(排外地)接触纳米线的顶面101a而不接触纳米线的侧部101b。
这样，在第一实施例中，电极110与纳米线的半导体材料的接触由与顶面101a的接触占主导，其中Δh1小于纳米线101的顶面101a的直径或宽度101c(即，其中在第一实施例中Δh1＝0或0＜Δh1<101c＝。
为了允许工艺变量，包括不均匀的纳米线高度，纳米线的侧部101b的所露出的比否则将是必要的更长，以免意外地留下一些纳米线未被接触。这样，当形成顶部电接触/电极110时，纳米线的末端的不同部分与电极101形成接触。也就是说，与在较短的纳米线(其中在较短的纳米线中Δh1可等于零，并且电极110仅接触顶面101a)上相比，在较长的纳米线上沿较长的侧部101b形成顶部电极110。较长的纳米线和较短的纳米线与电极110之间的接触面积的差异导致在相同器件中不同纳米线之间在输出和性能中的不期望的非均匀性。
图1c和1d分别示出了现有技术的纳米线器件和第二实施例的纳米线器件。第二实施例器件类似于如图1b所示的第一实施例器件。然而，在第二实施例中，绝缘外壳108完全覆盖半导体纳米线101的侧壁。此外，绝缘外壳108的高度典型地比半导体纳米线101的长度超出高度Δh2，其中Δh2是从半导体纳米线101的顶面到绝缘外壳108的顶面的距离。相比于第一实施例，顶部电极110仅接触纳米线的顶面101a，且因此，纳米线表面与顶部电极之间的接触面积对于同一支撑物(例如，以下将更详细描述的生长衬底或其他支撑物)上的所有纳米线而言基本是相同的(例如，基本上取决于纳米线截面的变化，并且变化小于40％，例如小于20％，诸如少于10％，包括小于5％)，无论纳米线高度如何或不同纳米线之间的Δh2的变化如何。如图1d所示，当从半导体纳米线101的顶部去除催化剂纳米粒子106时，纳米线103以上超出的绝缘外壳108在纳米线103上方形成凹槽130。当形成TCO电极110时，凹槽由电极110TCO材料填充。
这样，如上文所描述的那样，电极与纳米线101的接触优选为仅接触每根半导体纳米线101的顶面，或尽可能少地接触半导体纳米线101的侧面。此外，在最终的器件结构中，允许绝缘外壳108延伸超过半导体纳米线101的顶端的益处降低了或由于变化的纳米线长度引起的或由于其他工艺变量而引起的工艺变量的影响。通过结合在加工过程中被去除的金属催化剂粒子106来得到如图1d所示的结构。在作为替代的实施例中，延伸超过半导体纳米线101顶端的绝缘外壳108也可用于芯-壳纳米线中。
如图3a-3d所示，多根纳米线101可并联连接以形成纳米线器件，诸如光电器件，例如发光二极管(LED)或太阳能电池。具体而言，图3a示出了图1b/1d的实施例的具有纳米线101而不具有催化剂粒子106的器件的电路图150。图3c示出了图1a/图1c的具有纳米线101且具有催化剂粒子106的现有技术器件的电路图154。图3b示出了图3a的电路的仿真的电流对电压特性，而图3d示出了图3c的电路的仿真的电流对电压特性。
具体而言，图3b示出了操作为二极管(例如LED)151和操作为太阳能电池152的电路150的I-V特性。图3d示出了操作为二极管155和操作为太阳能电池156的电路154的I-V特性。如图3c所示，反向肖特基二极管122导致在电路154中对于具有催化剂纳米粒子106的每根半导体纳米线101产生电压降Vsh(在照明下产生的反向电压)。此外，如图3d所示，电压Vsh使器件154相对于器件150而言其I-V特性失真，导致I-V曲线155和156在开路电压Voc(在没有附加负载的情况下在照明下产生的电压)与电压Vsh之间的差值为零处交叉。也就是说，电压Vsh降低了开路电压Voc。相反，图3a和3b中所示的本发明实施例的电路150的曲线151、152显示了改善的器件行为和Voc。
从1×1mm2的InP纳米线太阳能电池的实验结果表明，当在纳米线101上存在Au催化剂粒子106时，其平均Voc(500-700mV)显著低于标准的平面InP太阳能电池的平均Voc(880mV)。除了平均Voc较低之外，Voc的分布通常是大的，具有若干100mV的标准偏差。
图4a-4d示出了对比在纳米线101的顶部具有金属催化剂纳米粒子106和不具有金属催化剂纳米粒子106的纳米线器件的实验结果。图4a示出了在从半导体纳米线101去除催化剂纳米粒子106的情况下，纳米线器件的效率的增加(例如，>60％，诸如67％的改进)。图4b示出了填充因子的增加(2％)。图4c示出了开路电压的提升(例如，>40％，诸如42％的改进)。图4d示出了实施例相对于传统纳米线器件的电流密度的改进(例如，>10％，诸如16％的改进)。图4a-4d示出了各个器件的测量值，每个器件包含具有二氧化硅壳的4百万根纳米线。除了Au粒子去除步骤，对各器件的加工相同。左边三个样品留有Au粒子，右边两个不具有Au粒子。
对效率改进的主要贡献相信是由于较高的Voc，其中实施例的器件还表现出较小的分布Voc，表明更均匀的接触。改进的第二根源是短路电流Jsc的改进。这一改进由于器件较低的遮光性和反射率而可预见，如图7所示。如图7所示，去除了催化剂粒子106的纳米线在370-1170nm的波长范围内表现出很少或没有反射率。与之相反的是，没有去除纳米粒子106的纳米线101在几乎整个波长范围内表现出5％-20％的反射率。
图5a-5g示出了根据实施例的制造纳米线器件的方法。如图5a所示，纳米线101d、101e在支撑物100上生长或沉积，支撑物100诸如为衬底或将在下面讨论的其他支撑物。例如，可利用VLS方法和催化剂纳米粒子在半导体衬底100上生长纳米线。
可替代地，如下，可将所生长的纳米线沉积在支持物上。通过AerotaxyTM工艺(如上面提到的PCT公开的申请WO 11/142,717所描述的那样)利用催化剂纳米粒子在气体或蒸汽相中生长纳米线。然后将聚集的纳米线定位在支撑物100上，支撑物100诸如为半导体、导电的(例如，金属)或绝缘的(例如，玻璃、陶瓷或塑料)衬底。可通过任何合适的方法使纳米线与大体上垂直于下方支撑物的顶面的这些纳米线的轴线对准。
例如，可通过选择性的化学功能作用来对准纳米线。具体而言，该方法包括用带电有机功能化化合物选择性地将纳米线101的部分(例如，第一部分102)功能化，将多根纳米线分散在极性或半极性溶剂中，并且在支撑物100上对准纳米线101使得纳米线的纵向轴线的朝向大体垂直于支撑物的主要表面。也可典型地通过形成共价键以与功能化化合物形成绑定对的有机附件配位体对支撑物100的主要表面功能化。也就是说，功能化化合物共价绑定到附件配位体上来将多根纳米线固定于支撑物。
替代地，可通过在纳米线的群体上施加电场来对准纳米线，由此纳米线中的电极化使得它们沿着电场对准，如在2011年6月30日公布的PCT公开的申请WO 11/078,780及其序列号为13/518,259的美国国家阶段申请中所述的那样，这两个申请的全部公开内容均通过引用的方式并入本文。优选地，在提供支撑物和在支撑物上对准的步骤期间将纳米线分散在流体中(气体或液体)中。除了极化使纳米线在电场中对准之外，可在包含纳米线的pn结中诱导可选的电偶极来进一步提供方向性并且在对准期间通过用辐射(例如，可见光)照射纳米线来加强纳米线的对准，在纳米线的端部之间有效地引起开路光伏电压。
优选地，纳米线101d、101e包括具有第一导电类型(例如，p型)的第一部分102和具有第二导电类型(例如，n型)的第二部分104。如果需要，每个部分可包括两个或更多个子区域。例如，第二部分可包含相邻于pn结103的重掺杂的上部子区域(例如，n+)和下部较轻的或轻掺杂的下部子区域(例如，n或n-)。每个子区域可以是75-150nm的长度(即，在平行于纳米线的轴线的方向上)。
如果下部子区域是本征的，则该器件包括p-i-n结而不是pn结103。pn结103优选平行于支撑物(例如，衬底)100的主要表面并且垂直于纳米线的轴线延伸。pn结优选定位在半导体纳米线101d、101e的顶面的300nm之内。
如图5a中所示，纳米线101d、101e形成有金属催化剂粒子106b。此外，如图5a中所示，纳米线101d、101e具有不同的长度，这代表在实际的纳米线器件中纳米线长度的可变性。纳米线可以是IV组纳米线(例如，硅)或III-V组纳米线(例如，InP或GaAs)。纳米线101d或101e也可以在线材的不同轴向或径向部分由多种材料组成。例如，为了钝化的目的，线材可以是GaAs，其中外壳层可以为AlGaAs或InGaP合金。
接下来，如图5b中所示，在包括纳米粒子106的纳米线101d、101e的表面之上形成绝缘外壳108。绝缘外壳108可由任何合适的绝缘材料制成，诸如氧化物或氮化物，诸如氧化硅或氮化硅。此外，可以由任何合适的方法形成绝缘外壳108，诸如原子层沉积法(ALD)。除了使相邻的纳米线101d、101e彼此电绝缘之外，绝缘外壳108也优先使纳米线101d、101e的表面钝化。
如果ALD工艺用于形成绝缘外壳108并且绝缘外壳108由SiO2制成，则用于ALD沉积的前驱体可以是三(三级丁氧基)硅醇(TTBS)和三甲基铝(TMAl)。TTBS和TMAl可以被用脉冲输送到含有纳米线器件的反应室中。优选地，将反应室加热。TTBS和TMAl化学吸附到被加热的纳米线101d、101e并且形成SiO2的薄的共形层。通过用N2清洗该室，可去除多余的前驱体和配位体/分子。在一个实施例中，反应室中的基准压强为2mTorr并且温度是255℃。在一个实施例中，通过进行3个脉冲的TTBS接着进行1个脉冲的TMAl来实施ALD SiO2工艺。此工艺可根据需要被重复以获得所期望的层厚度。例如，该工艺可被重复20-24次以得到围绕NW的50纳米SiO2的期望厚度。脉冲的数目可以增加或减少来产生更厚的或更薄的绝缘外壳108。
除了ALD工艺之外，也可使用其他对纳米线涂层/钝化的方法，诸如旋布玻璃、等离子体增强化学气相沉积(PECVD)或低压化学气相沉积(LPCVD)、正硅酸乙酯(TEOS)的固化以及溅射。除了SiO2之外，其他合适的绝缘/钝化材料包括聚合物，诸如苯并环丁烯(BCB)、Al2O3和HfOx。
接下来，如图5c中所示，在纳米线101d、101e之上和之间沉积可选的牺牲层502。牺牲层502可以是任何合适的材料，诸如聚合物或光刻胶层并且可以由任何合适的方法形成，诸如，自旋沉积。
接下来，如图5d中所示，通过蚀刻或抛光将牺牲层502平面化以露出纳米线101d、101e的末端。如图5d中所示，在一个实施例中，进行蚀刻使得在较高的纳米线101d上完全露出金属催化剂粒子106。也就是说，进行蚀刻直到牺牲层502和绝缘外壳108降低到较高的半导体纳米线101d的顶面为止。在这个层面上，牺牲层502和绝缘外壳108均高过较短纳米线101e的顶面。
为了打开并露出纳米线末端以形成接触，可以使用任何合适的蚀刻技术，诸如反应离子蚀刻(RIE)。在一个实施例中，用CF4、CHF3和Ar的混合气体以5-50sccm的流速，诸如分别为20、20和10sccm的流速进行RIE。在一个实施例中，可在200-400mTorr的压强，诸如300mTorr的压强下，以200-300W的RF等离子体功率，诸如250W的功率进行RIE。RIE的高度各向异性的性质导致在纳米线101d、101e顶部上的绝缘外壳108被优先蚀刻。RIE参数可以按期望改变。在可替代的实施例中，使用湿法蚀刻代替RIE。可通过控制蚀刻速率和牺牲层502的厚度来使用湿法蚀刻。
接下来，如图5e中所示，从纳米线101d、101e上去除金属催化剂粒子106。对于较短的纳米线101e，当金属催化剂粒子106被去除时在纳米线101e的顶部上形成由绝缘外壳108包围的凹槽130。在一个实施例中，通过选择性蚀刻，诸如通过碘基蚀刻，去除金属催化剂粒子106。当蚀刻金粒子脱离InP纳米线时会发现碘化物蚀刻的益处。在一个实施例中，碘化物蚀刻包括以下步骤：
步骤1：在H2SO4:H2O 1:25中沉浸10s
步骤2：在H2O中沉浸10s
步骤3：在KI:I2:H2O 4g:1g:40ml中10s
步骤4：在包含DI水的第四烧杯中清洗10s
步骤5：在包含DI水的第五烧杯中清洗2min
步骤5：用N2枪吹干样品
步骤6：重复步骤1-5直到去除催化剂粒子为止。对于GaAs纳米线，氰基蚀刻可以被用于去除催化剂粒子106。在一个实施例中，氰化物蚀刻包括以下步骤：
步骤1：预先混合的Zn和氰化钾(例如，TFAC金蚀刻)：H2O6.1g:100ml持续10min
步骤2：在H2O中沉浸30s
步骤3：在H2O中清洗10min
步骤4：用N2枪吹干样品对于从除了Au的种子粒子(例如，Cu、Ag、Al、Fe、Ni、In、Ga、及它们的合金，包括与金的合金)生长的纳米线，可以使用其他蚀刻化学过程。
如图5f中所示，在从纳米线101d、101e上去除金属催化剂粒子106之后，去除剩余的牺牲层502。如果牺牲材料是聚合物，则可以通过在有机溶剂，诸如去除剂1165中浸泡器件来去除牺牲材料。优选地，然后清洗纳米线101d、101e，诸如用O2RIE等离子体来去除任何有机残留物。在一个实施例中，以40-60W(诸如50W)的功率、200-300mTorr(诸如250mTorr)的压强以及40-60sccm(诸如50sccm O2)的氧气流速来进行RIE。
接下来，如图5g中所示，在纳米线101d、101e之上形成顶部电极110。优选地，顶部电极110由透明材料制成，诸如透明导电氧化物(TCO)。在一个实施例中，TCO层是在室温处溅射的铟锡氧化物(ITO)。在可替代的实施例中，TCO层是通过溅射或ALD形成的掺杂Al的氧化锌(AZO)。
在图5h中示出的替代性实施例，省略了绝缘外壳108。换而言之，省略了图5b中所示的外壳沉积步骤108。取代图5c中示出的可选的牺牲层502，在纳米线101d、101e之间和之上形成图5h中示出的永久整体绝缘材料层602。绝缘材料602可包括任何合适的绝缘材料，诸如聚合物材料、氧化硅、氮化硅以及其他合适的材料。
处理然后如上关于图5d和5e所述的那样继续进行，其中通过蚀刻或抛光将绝缘层602平面化以露出纳米线101d、101e的末端。然后如上文所描述的那样去除催化剂粒子106，并且在露出的纳米线110d、101e和绝缘层602之上形成顶部电极110，如图5h中所示。因此，绝缘层602在最终的器件中保留并且不会像在图5f中所示的去除步骤中的牺牲层502那样被清除。如图5h中留下绝缘层602的附加益处在于随后的透明导电层不环绕pn结，其在某些配置中会对线材引起不良的栅场效应。
图5i示出了另一个可替代的实施例。在这个实施例中，纳米线101不位于支撑物100上(即，省略了在纳米线的底部的支撑物)。反之，所生长的纳米线101被嵌入在绝缘基体702中。例如，可利用AerotaxyTM工艺生长纳米线101，然后被聚集并嵌入在绝缘基体702中，诸如聚合物基体。
可选择地，可利用以上关于图5b-5g所述的方法使顶部电极110和底部电极510均接触到纳米线101。因此，如图5i中所示，在绝缘基体702的顶面和底面都露出了纳米线101。至少一些纳米线101相对于它们各自的外壳108的顶面和/或底面凹进，以在一些纳米线101的顶部和底部形成凹槽130。顶部电极110和底部电极510然后沉积在绝缘基体702的各自的顶面和底面上来接触纳米线101露出的顶面和底面。底部电极510可以包括金属基板、反射镜(例如，反射金属层)或透明接触(例如，TCO)。如果需要的话，类似于如以上关于图5h所述的方法，也可在本实施例中省略外壳108。
图6a和6b示出了在去除Au粒子之前(a)和去除Au粒子之后(b)纳米线101的SEM图像。在图6b中围绕线材的明亮边缘显示出大部分线材在末端具有凹槽130，如在图1d中示意性示出的纳米线那样。
图8a-b示出了半导体纳米线101生长的可替代的第三实施例。可以通过VLS用催化剂粒子生长纳米线，或它们可以不用催化剂生长，诸如通过选择性生长，如图8a-8b中所示的那样。在这个实施例中，可在半导体纳米线101的第二部分104的上部设置牺牲部分116。例如，如果半导体纳米线101由GaAs制成，那么半导体纳米线101的上部可由Si、InAs、InAsP、InP、AlGaAs或AlAs制成，其可以相对于GaAs被选择性地蚀刻。
如图8a所示，该方法通过在衬底105上提供生长掩膜111开始。衬底可以是任何衬底，诸如GaAs或硅，并且生长掩膜可以是诸如SiNx或SiOx的介电质。
然后，在生长掩膜111中形成开口113。开口优选在它们的直径和它们的相对定位方面被良好地控制。本领域中已知的若干技术可被用于此程序，包括，但不限于，光刻技术，诸如电子束光刻(EBL)、纳米压印、光学光刻，然后进行蚀刻，诸如反应离子蚀刻(RIE)或湿式化学蚀刻法。优选地开口具有与纳米线101的直径101c(例如，500nm或更小)大约相同的直径，并且间隔0.5-5μm。开口限定了将要产生的纳米线101的位置和直径101c。
然后，如图8b中所示，通过基于CVD的工艺继续纳米线生长过程，其中前驱体源流优选为连续的。调节前驱体源流的流速以在生长区实现低过饱和度。V/III比率应该在范围1-100内，优选地在范围1-50内，甚至更优选地在5-50内。应该注意的是此V/III比率大大低于用于薄生长的比率。前驱体在生长期间改变以在纳米线101的顶部形成牺牲区域116。例如，在MOCVD纳米线生长期间对于Ga前驱体转换Al或Al+Ga前驱体(例如，TMAl或TMG)以在AlGaAs或AlAs牺牲半导体区域116生长与基GaAs纳米线区域102、104生长之间转换。类似的步骤可用于Si、InP或其他半导体材料纳米线和牺牲区域。可以利用金属有机前驱体通过MOCVD或利用氢化物源(诸如硅烷或乙硅烷)通过传统的CVD生长硅纳米线。
第三实施例的处理然后以与图5a-5g中相同的方式继续，除了取代催化剂粒子106的牺牲区域116位于纳米线101上之外。因此，通过利用和去除牺牲区域116获得如同利用和去除催化剂粒子106相似的效果。因此，可利用图8a-b的方法接着是图5a-5g的方法形成图1d的纳米线。
在另一个实施例中，利用上述任方法中的一种利用催化剂粒子生长半导体纳米线，稍后去除纳米线的牺牲部分(例如，牺牲区域)116和催化剂粒子。在本实施例的一个非限制性方面，利用催化剂粒子生长轴向GaAs纳米线芯和径向AlGaAs覆层(一层或多层)组成的GaAs芯壳纳米线。这之后是生长牺牲的Si、InP或InAs区域116。然后，如上所述，去除催化剂粒子和牺牲区域两者。在处理中在后期阶段可利用任何合适的蚀刻介质选择性地去除牺牲区域，诸如对于InP的HCl、对于InAs的NH4OH或对于Si的KOH，提供比仅单独去除催化剂粒子的情况下更深的凹槽。
尽管前面提及了特别优选的实施例，但将理解的是本发明不限于此。本领域普通技术人员将意识到，可对所公开的实施例进行各种变型并且这些变型意在本发明的范围之内。本文所引用的所有公开文本、专利申请以及专利的全部内容以引用的方式并入本文。

Claims (40)

1.一种半导体纳米线器件，包括：
至少一根半导体纳米线，其具有底面和顶面；
绝缘材料；以及
电极，其欧姆接触所述半导体纳米线的顶面，其中，所述电极与所述半导体纳米线的半导体材料的接触由与所述半导体纳米线的顶面的接触占主导；
其中，所述绝缘材料延伸到所述半导体纳米线的顶面以上以在所述绝缘材料的侧壁与所述半导体纳米线的顶面之间产生凹槽；以及
所述电极填充所述凹槽并且仅接触所述半导体纳米线的顶面而不接触所述半导体纳米线的侧壁。
2.根据权利要求1所述的器件，其中，
所述半导体纳米线的顶面具有直径或宽度；
所述电极接既触纳米线的顶面又接触位于顶面以下的侧部；以及
所述侧部的长度小于所述至少一根半导体纳米线的直径或宽度使得所述电极与所述半导体纳米线的半导体材料的接触由与所述半导体纳米线的顶面的接触占主导。
3.根据权利要求1所述的器件，其中，所述电极和所述纳米线的顶面形成欧姆接触并且所述电极在所述绝缘材料的顶面之上延伸。
4.根据权利要求1所述的器件，其中，所述电极包括透明材料。
5.根据权利要求4所述的器件，其中，所述电极包括透明导电氧化物。
6.根据权利要求1所述的器件，还包括多根半导体纳米线和位于相邻纳米线之间的介电材料。
7.根据权利要求6所述的器件，其中，所述介电材料包括透明材料。
8.根据权利要求6所述的器件，其中，所述多根纳米线中的一些在绝缘材料与纳米线的顶面之间不具有凹槽。
9.根据权利要求1所述的器件，其中，所述绝缘材料选自以下至少之一：绝缘外壳、绝缘层以及绝缘基体。
10.根据权利要求1所述的器件，其中，
所述半导体纳米线包括硅或III-V半导体；以及
所述半导体纳米线以其底面定位于支撑物上或者所述半导体纳米线嵌入在绝缘基体中而不具有底部支撑物。
11.根据权利要求1所述的器件，其中，所述半导体纳米线是具有pn结的轴向纳米线，其中具有第一导电类型的第一层在具有相反的第二导电类型的第二层之上。
12.根据权利要求11所述的器件，其中，所述pn结垂直于所述半导体纳米线的轴线延伸并且所述pn结位于所述半导体纳米线的顶面的300nm之内。
13.根据权利要求1所述的器件，其中，所述半导体纳米线不包括位于顶面上的催化剂粒子。
14.根据权利要求1所述的器件，其中，所述器件是发光二极管器件、光电器件或光伏器件。
15.一种制造半导体纳米线器件的方法，包括：
形成至少一根半导体纳米线，所述半导体纳米线具有位于半导体纳米线的顶面的催化剂粒子或包括所述顶面的牺牲部分；
形成包围所述半导体纳米线的绝缘材料；
去除所述催化剂粒子或牺牲部分以使所述纳米线的顶面凹进至所述绝缘材料的顶面以下；以及
形成与所述纳米线的顶面欧姆接触的电极。
16.根据权利要求15所述的方法，其中，所述绝缘材料选自以下至少之一：绝缘外壳、绝缘层以及绝缘基体。
17.根据权利要求16所述的方法，其中，
所述绝缘材料包括绝缘外壳；以及
形成所述绝缘外壳包括在所述半导体纳米线之上和周围通过原子层沉积、旋布玻璃、等离子体增强化学气相沉积、低压化学气相沉积、或溅射沉积绝缘层。
18.根据权利要求17所述的方法，其中，通过利用三(三级丁氧基)硅醇(TTBS)和三甲基铝(TMAl)前驱体沉积SiO2的原子层沉积或沉积Al2O3或HfOx的原子层沉积形成所述绝缘外壳。
19.根据权利要求15所述的方法，其中，在去除所述催化剂粒子或牺牲部分之前形成所述绝缘材料并且形成所述绝缘材料导致绝缘材料覆盖所述催化剂粒子或牺牲部分。
20.根据权利要求19所述的方法，还包括：去除覆盖所述催化剂粒子或牺牲部分的所述绝缘材料。
21.根据权利要求15所述的方法，还包括：在形成所述电极之前清洗所述至少一根纳米线。
22.根据权利要求15所述的方法，其中，所述半导体纳米线器件包括多根半导体纳米线并且所述方法还包括在围绕所述半导体纳米线形成绝缘材料之后在半导体纳米线之上和之间沉积牺牲层。
23.根据权利要求22所述的方法，还包括：通过如下方法去除所述牺牲层和绝缘材料以露出所述半导体纳米线的顶面：
用包括CF4、CHF3和Ar的气氛的反应离子蚀刻；或
湿法蚀刻。
24.根据权利要求15所述的方法，其中，
所述半导体纳米线包括硅或III-V半导体；以及
所述半导体纳米线以其底面定位于支撑物上或者所述半导体纳米线嵌入在绝缘基体中而不具有底部支撑物。
25.根据权利要求15所述的方法，其中，所述电极延伸超过所述绝缘材料的顶面。
26.根据权利要求15所述的方法，其中，所述电极包括透明材料。
27.根据权利要求26所述的方法，其中，所述电极包括透明导电氧化物。
28.根据权利要求27所述的方法，其中，所述透明导电氧化物包括铟锡氧化物(ITO)或掺杂Al的氧化锌(AZO)。
29.根据权利要求15所述的方法，还包括多根半导体纳米线和位于相邻纳米线之间的介电材料。
30.根据权利要求29所述的方法，其中，所述介电材料包括透明材料。
31.根据权利要求29所述的方法，其中，所述多根纳米线中的一些在绝缘材料与纳米线的顶面之间不具有凹槽。
32.根据权利要求15所述的方法，其中，所述半导体纳米线是具有pn结的轴向纳米线，其中具有第一导电类型的第一层在具有相反的第二导电类型的第二层之上。
33.根据权利要求32所述的方法，其中，所述pn结垂直于所述半导体纳米线的轴线延伸并且所述pn结位于所述半导体纳米线的顶面的300nm之内。
34.根据权利要求15所述的方法，其中，所述器件是发光二极管器件或光伏器件。
35.根据权利要求15所述的方法，其中，
形成至少一根半导体纳米线的步骤包括利用所述催化剂粒子在支撑物上生长所述半导体纳米线；以及
所述去除步骤包括去除所述催化剂粒子。
36.根据权利要求35所述的方法，其中，通过用包括碘或氰化物的溶液蚀刻来去除所述催化剂粒子。
37.根据权利要求15所述的方法，其中，
形成至少一根半导体纳米线的步骤包括在气体或气相中利用所述催化剂粒子生长所述半导体纳米线，然后将所生长的纳米线置于支撑物上或将所生长的纳米线嵌入在绝缘基体中；以及所述去除步骤包括去除所述催化剂粒子。
38.根据权利要求15所述的方法，其中，
形成至少一根半导体纳米线的步骤包括在衬底上生长包含穿过掩膜中的开口的牺牲部分的纳米线而不使用所述催化剂粒子；以及
所述去除步骤包括去除所述牺牲部分。
39.根据权利要求15所述的方法，其中，
形成至少一根半导体纳米线的步骤包括利用所述催化剂粒子生长所述半导体纳米线；以及所述去除步骤包括去除所述牺牲部分和所述催化剂粒子。
40.一种半导体纳米线器件，包括：
至少一根半导体纳米线，其具有底面和顶面；
绝缘材料，其包围所述半导体纳米线并且延伸超过所述纳米线的顶面以在所述绝缘材料的侧壁与所述纳米线的顶面之间产生凹槽；以及
电极，其填充所述凹槽并且欧姆接触所述纳米线的顶面。
CN201380073253.5A 2012-12-21 2013-12-06 半导体纳米线的凹槽式接触 Expired - Fee Related CN104995741B (zh)

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9012883B2 (en) 2012-12-21 2015-04-21 Sol Voltaics Ab Recessed contact to semiconductor nanowires
WO2016069831A1 (en) * 2014-10-30 2016-05-06 President And Fellows Of Harvard College Nanoscale wires with tip-localized junctions
CN111725339A (zh) * 2014-11-07 2020-09-29 索尔伏打电流公司 密堆积胶体晶体膜的壳赋能垂直对准和精密组装
DE102015205230B4 (de) * 2015-03-23 2023-01-19 Universität Duisburg-Essen Verfahren zur Herstellung von Bauelementen aufweisend eine Schottky-Diode mittels Drucktechnik und Bauelement
KR101787435B1 (ko) * 2016-02-29 2017-10-19 피에스아이 주식회사 나노 로드 제조방법
EP3260414A1 (en) 2016-06-21 2017-12-27 Sol Voltaics AB Method for transferring nanowires from a fluid to a substrate surface
FR3064109A1 (fr) * 2017-03-20 2018-09-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Structure a nanofils et procede de realisation d'une telle structure
KR101919487B1 (ko) * 2017-09-14 2018-11-19 한국과학기술연구원 반도체 기판을 텍스쳐링하는 방법과, 이 방법에 의해 제조된 반도체 기판, 그리고, 이러한 반도체 기판을 포함하는 태양 전지
JP7371366B2 (ja) * 2019-06-27 2023-10-31 富士通株式会社 半導体デバイス、及びこれを用いた無線受信器
US11101744B2 (en) * 2019-12-27 2021-08-24 Michael Junior Spruill Capacitive engine featuring an extrinsic semiconductor
CN111180554B (zh) * 2020-01-08 2023-01-03 燕山大学 一种混合结构太阳能电池的制备方法
JP7384273B2 (ja) * 2020-04-15 2023-11-21 富士通株式会社 半導体装置、リザバーコンピューティングシステム及び半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101842909A (zh) * 2007-07-19 2010-09-22 加利福尼亚技术学院 半导体的有序阵列结构

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3870459B2 (ja) * 1996-10-28 2007-01-17 ソニー株式会社 量子細線の製造方法
JP4235440B2 (ja) 2002-12-13 2009-03-11 キヤノン株式会社 半導体デバイスアレイ及びその製造方法
US6933222B2 (en) * 2003-01-02 2005-08-23 Intel Corporation Microcircuit fabrication and interconnection
US20060207647A1 (en) 2005-03-16 2006-09-21 General Electric Company High efficiency inorganic nanorod-enhanced photovoltaic devices
US7230286B2 (en) * 2005-05-23 2007-06-12 International Business Machines Corporation Vertical FET with nanowire channels and a silicided bottom contact
EP1804286A1 (en) 2005-12-27 2007-07-04 Interuniversitair Microelektronica Centrum Elongate nanostructure semiconductor device
KR100721020B1 (ko) * 2006-01-20 2007-05-23 삼성전자주식회사 콘택 구조체를 포함하는 반도체 소자 및 그 형성 방법
DE102006013245A1 (de) * 2006-03-22 2007-10-04 Infineon Technologies Ag Verfahren zur Ausbildung von Öffnungen in einer Matrizenschicht und zur Herstellung von Kondensatoren
AU2008264257A1 (en) * 2007-06-19 2008-12-24 Qunano Ab Nanowire-based solar cell structure
US20080315430A1 (en) * 2007-06-22 2008-12-25 Qimonda Ag Nanowire vias
EP2019313B1 (en) * 2007-07-25 2015-09-16 Stichting IMEC Nederland Sensor device comprising elongated nanostructures, its use and manufacturing method
EP2183789A1 (en) * 2007-08-28 2010-05-12 California Institute of Technology Method for reuse of wafers for growth of vertically-aligned wire arrays
KR20090058952A (ko) * 2007-12-05 2009-06-10 삼성전자주식회사 나노로드를 이용한 발광소자 및 그 제조 방법
EP2419938A2 (en) * 2009-04-15 2012-02-22 Sol Voltaics AB Multi-junction photovoltaic cell with nanowires
KR101663200B1 (ko) * 2009-09-30 2016-10-06 국립대학법인 홋가이도 다이가쿠 터널 전계 효과 트랜지스터 및 그 제조 방법
CN105347297B (zh) 2009-12-22 2018-01-09 昆南诺股份有限公司 用于制备纳米线结构的方法
JP2011187901A (ja) * 2010-03-11 2011-09-22 Canon Inc 半導体デバイスの製造方法
US7906354B1 (en) * 2010-03-30 2011-03-15 Eastman Kodak Company Light emitting nanowire device
KR101777894B1 (ko) 2010-05-11 2017-09-13 큐나노 에이비 와이어의 기상 합성
WO2012035243A1 (fr) 2010-09-14 2012-03-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif optoelectronique a base de nanofils pour l'émission de lumière
GB201015411D0 (en) 2010-09-15 2010-10-27 Univ Leuven Kath Anti-cancer activity of novel bicyclic heterocycles
WO2013126432A1 (en) * 2012-02-21 2013-08-29 California Institute Of Technology Axially-integrated epitaxially-grown tandem wire arrays
US9012883B2 (en) 2012-12-21 2015-04-21 Sol Voltaics Ab Recessed contact to semiconductor nanowires

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101842909A (zh) * 2007-07-19 2010-09-22 加利福尼亚技术学院 半导体的有序阵列结构

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