CN104992942B - Stacked vertical strain Si/SiGe Heterojunction CMOS devices structures and preparation method thereof - Google Patents
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Abstract
The invention discloses a kind of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures and preparation method thereof, the device includes silicon substrate, Relaxed SiGe Buffer, relaxation Si successively from the bottom up0.7Ge0.3Empty substrate, n+Delta doping layer, relaxation Si0.7Ge0.3Wall, strained Si channel, relaxation Si0.7Ge0.3Intermediate layer, strain Si0.5Ge0.5Raceway groove, relaxation Si0.7Ge0.3Cap layers and strain Si cap layers.The present invention makees n MOSFET channels using tensile strain Si materials, compressive strain sige material makees p MOSFET channels, n MOSFET and p MOSFET use vertical stacked, the two shares a polycrystal SiGe gate electrode, the mobility in electronics and hole improves a lot, integrated level, the speed of chip are improved, new technological approaches is opened up for the high speed of Si base devices and integrated circuit, high frequency development.
Description
Technical field
The present invention relates to technical field of semiconductor device preparation, and in particular to a kind of stacked vertical strain Si/SiGe is heterogeneous
Tie cmos device structure and preparation method thereof.
Background technology
Semiconductor integrated circuit is the basis of electronics industry, and people promote the field to the great demand of electronics industry
Development is very rapid.In the past few decades, the fast development of electronics industry generates huge to social development and national economy
Big influence.At present, electronics industry turns into worldwide largest industry, in occupation of very big part in world market
Volume, the output value have been over 1,000,000,000,000 dollars.
Si CMOS integrated circuits have the advantages that low-power consumption, high integration, low noise and high reliability, in semiconductor collection
Ascendancy is occupied into circuit industry.Further increase, device feature size however as footprint subtract
The increase of small, integrated level and complexity, especially device feature size enter after nanoscale, the material of Si cmos devices,
The limitation of physical features has progressively shown out, limits the further development of Si integrated circuits and its manufacturing process.Although
Research of the microelectronics in terms of compound semiconductor and other new materials and the application in some fields have made great progress,
It is but remote not possess the condition for substituting silicon-based technology.And according to science and technology the rule of development, a kind of new technology from be born to
The time in twenty or thirty year is generally required as main force's technology.So in order to meet the needs of traditional performance raising, strengthen SiCMOS
Performance be considered as microelectronics industry developing direction.
It is to improve mobility by introducing stress in traditional body Si devices using strain Si, SiGe technologies, improves
Device performance.The properties of product that can produce silicon chip improve 30%~60%, and process complexity and cost only increase by 1%~
3%.For existing many integrated circuit production lines, if using strain SiGe material not only throwing can not be being increased substantially
The Si CMOS ic core piece performances for making to produce in the case of money are obviously improved, but also can greatly prolong cost
The service life for the integrated circuit production line that huge investment is built up.
As device feature size enters the sub- 50 nm stage, in the research to strain Si, SiGe CMOS planar structures
Also many problems are encountered in journey：Short-channel effect, hot carrier's effect etc. cause device size not reduce further；Grid oxygen
Changing the thinned of thickness degree causes oxide layer breakdown, and tunnel electric current makes threshold voltage shift；Poly-Si depletion effect and polysilicon
Influence of the resistance to threshold voltage is also increasing etc., and these all make device and circuit performance can not continue according to Moore's Law
Rule of development development is gone down, and the device for studying new construction just becomes particularly important.
Existing mainstream technology is the CMOS integrated circuit techniques based on Si materials.With integrated circuit integrated level
Improve constantly, characteristic size constantly reduces, and a series of materials, device physicses, device architecture and technology etc. occurs
The problem of, it is particularly due to that the hole mobility of body Si materials is lower than electron mobility, the performance of Si cmos circuits is in very great Cheng
Restricted on degree by p-MOSFET, limit the further lifting of device performance.
The content of the invention
To solve the above problems, the invention provides a kind of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures
And preparation method thereof, n-MOSFET raceway grooves are made using tensile strain Si materials, compressive strain sige material makees p-MOSFET raceway grooves, n-
MOSFET and p-MOSFET uses vertical stacked, and the two shares a polycrystal SiGe gate electrode, the migration in electronics and hole
Rate improves a lot, the limitation for overcoming traditional Si CMOS technology mobil-ity degradation to lift device performance, improves chip speed
Degree, n-MOSFET and p-MOSFET use vertical stacked, and area reduces half than body Si CMOS, reduces traditional Si
CMOS technology version area on map, integrated level, the speed of chip are improved, enhance current driving ability and n-MOSFET and p-
MOSFET Rotating fields design is completely the same, and the two shares a polycrystal SiGe gate electrode, is advantageous to adjust work function and HCMOS
Threshold voltage etc., open up new technological approaches for the high speed of Si base devices and integrated circuit, high frequency development.
To achieve the above object, the technical scheme taken of the present invention is：
A kind of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures, include silicon substrate, relaxation successively from the bottom up
Si1-xGexCushion, relaxation Si0.7Ge0.3Empty substrate, n+Delta doping layer, relaxation Si0.7Ge0.3Wall, strained Si channel, relaxation
Si0.7Ge0.3Intermediate layer, strain Si0.5Ge0.5Raceway groove, relaxation Si0.7Ge0.3Cap layers and strain Si cap layers；Relaxation Si0.7Ge0.3Interval
Layer upper left side is provided with source electrode, and right side is provided with drain electrode, and source electrode and drain electrode are located at by strained Si channel, relaxation Si respectively0.7Ge0.3It is middle
Layer, strain Si0.5Ge0.5Raceway groove, relaxation Si0.7Ge0.3The both sides for the cube structure that cap layers and strain Si cap layers are formed by connecting, should
Become at the upper side of Si cap layers and be provided with SiO2Layer and polycrystal SiGe grid.
To solve the above problems, present invention also offers a kind of stacked vertical strain Si/SiGe Heterojunction CMOS devices knots
The preparation method of structure, comprises the following steps：
S1, doping concentration is chosen as 1 × 1015~1 × 1016cm-3P-type Si substrates；
S2, at 600~800 DEG C, using high vacuum chemical vapor deposition method, grow relaxation Si on a silicon substrate1- xGexCushion；
S3, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S2 is obtained1-xGexIt is slow
Rush and relaxation Si is grown on layer0.7Ge0.3Empty substrate；
S4, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S3 is obtained0.7Ge0.3It is empty
Grown n+Delta doping layer；
S5, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the n that S4 is obtained+It is raw on delta doping layer
Long relaxation Si0.7Ge0.3Wall；
S6, at 350~400 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S5 is obtained0.7Ge0.3Between
Growth strain Si raceway grooves on interlayer；
S7, at 600~800 DEG C, using high vacuum chemical vapor deposition method, on the strained Si channel that S6 is obtained,
Grow relaxation Si0.7Ge0.3Intermediate layer；
S8, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S7 is obtained0.7Ge0.3In
Growth strain Si on interbed0.5Ge0.5Raceway groove；
S9, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the strain Si that S8 is obtained0.5Ge0.5Ditch
Relaxation Si is grown on road0.7Ge0.3Cap layers；
S10, at 350~400 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S9 is obtained0.7Ge0.3
Growth strain Si cap layers in cap layers；
S11, make active area by lithography in the structure that S10 is obtained；
S12, source, leakage are prepared in the active area that S11 is obtained；
S13, grow grid oxygen in the structure that S12 is obtained；
S14, prepare p in the structure that S13 is obtained+Polycrystal SiGe gate；
S15, it is passivated in the structure that S14 is obtained；
S16, the lithography fair lead in the structure that S15 is obtained；
S17, alloying technology is carried out in the structure that S16 is obtained；
S18, the photoetching lead in the structure that S17 is obtained.
Wherein, the relaxation Si1-xGexBuffer layer thickness is 1.8 μm and Ge components are slowly varying by X=0 to X=0.3
's.
Wherein, relaxation Si0.7Ge0.3As empty substrate, thickness is 0.3 μm.
Wherein, relaxation Si0.7Ge0.3The n of empty Grown+Delta doping layer thickness is 4nm, doping concentration 1018cm-3。
Wherein, relaxation Si0.7Ge0.3Space layer is 8nm；Strained si-channel layers thickness is 8nm；Relaxation Si0.7Ge0.3In
Interbed thickness be 4nm and with relaxation Si0.7Ge0.3Empty substrate has identical Ge components；Strain Si0.5Ge0.5Channel layer thickness is
8nm；Relaxation Si0.7Ge0.3Cap layers thickness is 2nm, and strain Si cap layers thickness is 2nm.
Wherein, p+The doping concentration of polycrystal SiGe gate is 1020cm-3。
The invention has the advantages that：
N-MOSFET raceway grooves are made using tensile strain Si materials, compressive strain sige material makees p-MOSFET raceway grooves, n-MOSFET
Vertical stacked is used with p-MOSFET, the two shares a polycrystal SiGe gate electrode, and the mobility in electronics and hole has
Larger raising, the limitation for overcoming traditional Si CMOS technology mobil-ity degradation to lift device performance, improve chip speed, n-
MOSFET and p-MOSFET uses vertical stacked, and area reduces half than body Si CMOS, reduces traditional Si CMOS
Technology version area on map, integrated level, the speed of chip are improved, enhance current driving ability and n-MOSFET and p-MOSFET
Rotating fields design it is completely the same, the two shares a polycrystal SiGe gate electrode, is advantageous to adjust work function and HCMOS threshold value
Voltage etc., new technological approaches is opened up for the high speed of Si base devices and integrated circuit, high frequency development.
Brief description of the drawings
Fig. 1 is a kind of technological process of stacked vertical strain Si/SiGe Heterojunction CMOS devices of the embodiment of the present invention.
Fig. 2 is a kind of structural representation of stacked vertical strain Si/SiGe Heterojunction CMOS devices of the embodiment of the present invention.
Embodiment
In order that objects and advantages of the present invention are more clearly understood, the present invention is carried out with reference to embodiments further
Describe in detail.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to limit this hair
It is bright.
As shown in Fig. 2 the embodiments of the invention provide a kind of stacked vertical strain Si/SiGe Heterojunction CMOS devices knots
Structure, include silicon substrate, relaxation Si successively from the bottom up1-xGexCushion, relaxation Si0.7Ge0.3Empty substrate, n+Delta doping layer, relaxation
Si0.7Ge0.3Wall, strained Si channel, relaxation Si0.7Ge0.3Intermediate layer, strain Si0.5Ge0.5Raceway groove, relaxation Si0.7Ge0.3Cap
Layer and strain Si cap layers；Relaxation Si0.7Ge0.3Wall upper left side is provided with source electrode, and right side is provided with drain electrode, source electrode and drain electrode difference position
In by strained Si channel, relaxation Si0.7Ge0.3Intermediate layer, strain Si0.5Ge0.5Raceway groove, relaxation Si0.7Ge0.3Cap layers and strain Si cap
The both sides for the cube structure that layer is formed by connecting, strain Si cap layers upper side are provided with SiO2Layer and polycrystal SiGe grid.
As shown in figure 1, the embodiment of the present invention additionally provides above-mentioned stacked vertical strain Si/SiGe Heterojunction CMOS devices knots
The preparation method of structure, comprises the following steps：
S1, doping concentration is chosen as 1 × 1015~1 × 1016cm-3P-type Si substrates；
S2, at 600~800 DEG C, using high vacuum chemical vapor deposition method, growth thickness is 1.8 μ on a silicon substrate
M and Ge components are by relaxation Si slowly varying X=0 to X=0.31-xGexCushion；
S3, at 600~800 DEG C, using high vacuum chemical vapor deposition method, grown on the relaxation SiGe that S2 is obtained
The relaxation Si that thickness is 0.3 μm, Ge components are 0.30.7Ge0.3Empty substrate；
S4, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S3 is obtained0.7Ge0.3It is empty
On substrate, by doping way in situ, growth a layer thickness is 4nm, doping concentration 1018cm-3Relaxation Si0.7Ge0.3n+δ mixes
Diamicton；
S5, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the n that S4 is obtained+It is raw on delta doping layer
Long thickness is 8nm relaxation Si0.7Ge0.3Wall；
S6, at 350~400 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S5 is obtained0.7Ge0.3Between
Growth thickness is 8nm strained Si channels on interlayer；
S7, at 600~800 DEG C, using high vacuum chemical vapor deposition method, on the strained Si channel that S6 is obtained,
Growth thickness is 4nm relaxation Si0.7Ge0.3Intermediate layer；
S8, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S7 is obtained0.7Ge0.3In
Growth thickness is 8nm strain Sis on interbed0.5Ge0.5Raceway groove；
S9, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the strain Si that S8 is obtained0.5Ge0.5Ditch
Growth thickness is 2nm relaxation Si on road0.7Ge0.3Cap layers；
S10, at 350~400 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S9 is obtained0.7Ge0.3
Growth thickness is 2nm strain Si cap layers in cap layers；
S11, make active area by lithography in the structure that S10 is obtained；
S12, source, leakage are prepared in the active area that S11 is obtained；
S13, grow grid oxygen in the structure that S12 is obtained；
S14, prepare p in the structure that S13 is obtained+Polycrystal SiGe gate；
S15, it is passivated in the structure that S14 is obtained；
S16, the lithography fair lead in the structure that S15 is obtained；
S17, alloying technology is carried out in the structure that S16 is obtained；
S18, the photoetching lead in the structure that S17 is obtained.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures, it is characterised in that include silicon successively from the bottom up
Substrate, relaxation Si1-xGexCushion, relaxation Si0.7Ge0.3Empty substrate, n+Delta doping layer, relaxation Si0.7Ge0.3Wall, strain Si
Raceway groove, relaxation Si0.7Ge0.3Intermediate layer, strain Si0.5Ge0.5Raceway groove, relaxation Si0.7Ge0.3Cap layers and strain Si cap layers；Relaxation
Si0.7Ge0.3Wall upper left side is provided with source electrode, and right side is provided with drain electrode, and source electrode and drain electrode are located at by strained Si channel, relaxation respectively
Si0.7Ge0.3Intermediate layer, strain Si0.5Ge0.5Raceway groove, relaxation Si0.7Ge0.3The cube that cap layers and strain Si cap layers are formed by connecting
The both sides of structure, strain Si cap layers upper side are provided with SiO2Layer and polycrystal SiGe grid.
2. the preparation method of a kind of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures, it is characterised in that including as follows
Step：
S1, doping concentration is chosen as 1 × 1015~1 × 1016cm-3P-type Si substrates；
S2, at 600~800 DEG C, using high vacuum chemical vapor deposition method, grow relaxation Si on a silicon substrate1-xGexBuffering
Layer；
S3, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S2 is obtained1-xGexOn cushion
Grow relaxation Si0.7Ge0.3Empty substrate；
S4, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S3 is obtained0.7Ge0.3Empty substrate
Upper growth n+Delta doping layer；
S5, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the n that S4 is obtained+Relaxation is grown on delta doping layer
Si0.7Ge0.3Wall；
S6, at 350~400 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S5 is obtained0.7Ge0.3Wall
Upper growth strain Si raceway grooves；
S7, at 600~800 DEG C, utilize high vacuum chemical vapor deposition method, on the strained Si channel that S6 is obtained, growth
Relaxation Si0.7Ge0.3Intermediate layer；
S8, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S7 is obtained0.7Ge0.3Intermediate layer
Upper growth strain Si0.5Ge0.5Raceway groove；
S9, at 600~800 DEG C, using high vacuum chemical vapor deposition method, in the strain Si that S8 is obtained0.5Ge0.5On raceway groove
Grow relaxation Si0.7Ge0.3Cap layers；
S10, at 350~400 DEG C, using high vacuum chemical vapor deposition method, in the relaxation Si that S9 is obtained0.7Ge0.3Cap layers
Upper growth strain Si cap layers；
S11, make active area by lithography in the structure that S10 is obtained；
S12, source, leakage are prepared in the active area that S11 is obtained；
S13, grow grid oxygen in the structure that S12 is obtained；
S14, prepare p in the structure that S13 is obtained+Polycrystal SiGe gate；
S15, it is passivated in the structure that S14 is obtained；
S16, the lithography fair lead in the structure that S15 is obtained；
S17, alloying technology is carried out in the structure that S16 is obtained；
S18, the photoetching lead in the structure that S17 is obtained.
3. a kind of preparation method of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures according to claim 2,
Characterized in that, the relaxation Si1-xGexBuffer layer thickness is 1.8 μm and Ge components are slowly varying by x=0 to x=0.3.
4. a kind of preparation method of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures according to claim 2,
Characterized in that, relaxation Si0.7Ge0.3As empty substrate, thickness is 0.3 μm.
5. a kind of preparation method of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures according to claim 2,
Characterized in that, relaxation Si0.7Ge0.3The n of empty Grown+Delta doping layer thickness is 4nm, doping concentration 1018cm-3。
6. a kind of preparation method of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures according to claim 2,
Characterized in that, relaxation Si0.7Ge0.3Space layer is 8nm；Strained si-channel layers thickness is 8nm；Relaxation Si0.7Ge0.3It is middle
Thickness degree be 4nm and with relaxation Si0.7Ge0.3Empty substrate has identical Ge components；Strain Si0.5Ge0.5Channel layer thickness is
8nm；Relaxation Si0.7Ge0.3Cap layers thickness is 2nm, and strain Si cap layers thickness is 2nm.
7. a kind of preparation method of stacked vertical strain Si/SiGe Heterojunction CMOS devices structures according to claim 2,
Characterized in that, p+The doping concentration of polycrystal SiGe gate is 1020cm-3。
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| CN106816684A (en) * | 2016-12-20 | 2017-06-09 | 西安科锐盛创新科技有限公司 | For the Ge base plasma pin diode preparation methods of restructural multilayer holographic antenna |
| CN106654520A (en) * | 2016-12-20 | 2017-05-10 | 西安科锐盛创新科技有限公司 | Manufacturing method of solid-state plasma diode for preparing holographic antenna |
| CN106816686A (en) * | 2016-12-20 | 2017-06-09 | 西安科锐盛创新科技有限公司 | The preparation method of the restructural dipole antenna based on heterogeneous SiGeSPiN diodes |
| CN106816683A (en) * | 2016-12-20 | 2017-06-09 | 西安科锐盛创新科技有限公司 | For the manufacture method of the SPIN diodes of U wave band restructural loop aerial |
| CN106783559B (en) * | 2016-12-20 | 2019-09-24 | 西安科锐盛创新科技有限公司 | Frequency reconfigurable sleeve-dipole antenna preparation method based on SPiN diode |
| CN106876871A (en) * | 2016-12-20 | 2017-06-20 | 西安科锐盛创新科技有限公司 | The preparation method of SiGe fundamental frequency restructural sleeve-dipole antennas |
| CN106654521A (en) * | 2016-12-20 | 2017-05-10 | 西安科锐盛创新科技有限公司 | Preparation method of heterogeneous Ge-based SPiN diode strings for reconfigurable dipole antenna |
| CN106785334A (en) * | 2016-12-20 | 2017-05-31 | 西安科锐盛创新科技有限公司 | With SiO2Pin diodes of protective effect and preparation method thereof |
| CN106602216A (en) * | 2016-12-20 | 2017-04-26 | 西安科锐盛创新科技有限公司 | A preparation method of reconstructing a holographic antenna on the basis of SiGe base heterojunction frequency |
| CN106602215A (en) * | 2016-12-20 | 2017-04-26 | 西安科锐盛创新科技有限公司 | Method for preparing SiGe-based plasma pin diode for reconstructing holographic antennas |
| CN106602214A (en) * | 2016-12-20 | 2017-04-26 | 西安科锐盛创新科技有限公司 | Preparation method for frequency reconfigurable holographic antenna based on GaAs/Ge/GaAs heterostructure |
| CN116583109B (en) * | 2023-06-27 | 2024-02-02 | 北京超弦存储器研究院 | 3D memory, preparation method thereof and electronic equipment |
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| US7057216B2 (en) * | 2003-10-31 | 2006-06-06 | International Business Machines Corporation | High mobility heterojunction complementary field effect transistors and methods thereof |
| US20060292776A1 (en) * | 2005-06-27 | 2006-12-28 | Been-Yih Jin | Strained field effect transistors |
| CN102214694B (en) * | 2011-05-30 | 2013-05-08 | 西安电子科技大学 | Heterogeneous metal stacked grid strained silicon-germanium on insulator p-channel metal oxide semiconductor field effect tube (SSGOI pMOSFET) device structure |
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