CN106876871A - The preparation method of SiGe fundamental frequency restructural sleeve-dipole antennas - Google Patents
The preparation method of SiGe fundamental frequency restructural sleeve-dipole antennas Download PDFInfo
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- CN106876871A CN106876871A CN201611184362.6A CN201611184362A CN106876871A CN 106876871 A CN106876871 A CN 106876871A CN 201611184362 A CN201611184362 A CN 201611184362A CN 106876871 A CN106876871 A CN 106876871A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 238000001259 photo etching Methods 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 230000009191 jumping Effects 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 18
- 239000007787 solid Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005404 monopole Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
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- 210000002421 cell wall Anatomy 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q5/00—Arrangements for simultaneous operation of antennas on two or more different wavebands, e.g. dual-band or multi-band arrangements
- H01Q5/30—Arrangements for providing operation on different wavebands
- H01Q5/307—Individual or coupled radiating elements, each element being fed in an unspecified way
- H01Q5/314—Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors
- H01Q5/321—Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors within a radiating element or between connected radiating elements
Abstract
The present invention relates to a kind of preparation method of SiGe fundamental frequencies restructural sleeve-dipole antenna.The method includes：Choose SiGeOI substrates；According to the structure fabrication multiple SPiN diode strings of sleeve-dipole antenna on SiGeOI substrates；Direct current biasing line is made to connect SPiN diodes string and DC bias supplies；Make SPiN diodes antenna arm, a SPiN diodes sleeve and the 2nd SPiN diode sleeves；Coaxial feeder is made to connect SPiN diodes antenna arm, a SPiN diodes sleeve and the 2nd SPiN diode sleeves, sleeve-dipole antenna is ultimately formed.The sleeve-dipole antenna of the embodiment of the present invention, by metal direct current biasing line traffic control SPiN diode current flows, form the adjustable of plasma antenna arm and length sleeve, so as to realize the restructural of operating frequency of antenna, with it is easy of integration, can stealthy, frequency can rapid jumping the characteristics of.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of SiGe fundamental frequencies restructural sleeve-dipole antenna
Preparation method.
Background technology
Develop swift and violent today in antenna technology, traditional sleeve monopole antenna is with its broadband, high-gain, structure letter
Singly, many advantages, such as feeding easy and longitudinal size, azimuth plane omnidirectional is widely used in the communication systems such as vehicle-mounted, carrier-borne and remote sensing
In.But the electrical feature of the sleeve monopole antenna for commonly using depends not only upon tube-in-tube structure, and has very big pass with ground
System, this is difficult to meet frame antenna pair broadband high and the demand of miniaturization in carrier-borne communication engineering.
Sleeve-dipole antenna is the oscillator for a co-axial metal sleeve being added outside antenna radiator and being formed
Antenna.Sleeve antenna introduces asymmetric feed while overstriking oscillator, serves staggered tuning effect in similar circuit,
And then more effectively broadening impedance bandwidth.Meanwhile, it is difficult to meet various to break through the changeless service behaviour of traditional antenna
System requirements and applied environment complicated and changeable, the concept of reconfigurable antenna paid attention to and developed.Restructural micro-strip
Because of its small volume, the low advantage of section turns into the focus of reconfigurable antenna research to antenna.Based on this, the skirt dipole of restructural
Antenna turns into one of preferable product of Vehicles Collected from Market prospect.
With the development of microelectric technique, current technological development is had become using semi-conducting material manufacturing reconfigurable antenna
Trend.Therefore, how simple structure is designed using semiconductor process technique, it is easy to accomplish frequency reconfigurable sleeve idol
Pole sub-antenna, is the problem of those skilled in the art's urgent need to resolve.
The content of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides a kind of SPiN diodes restructural etc. from
Sub-sleeve dipole antenna.The technical problem to be solved in the present invention is achieved through the following technical solutions：
The embodiment provides a kind of preparation method of SiGe fundamental frequencies restructural sleeve-dipole antenna, its
In, the antenna includes semiconductor chip, SPiN diodes antenna arm, a SPiN diodes sleeve, the 2nd SPiN diodes
Sleeve, coaxial feeder, direct current biasing line；Wherein, the preparation method includes：
Choose SiGeOI substrates；
According to the structure fabrication multiple SPiN diode strings of the sleeve-dipole antenna on the SiGeOI substrates；
Direct current biasing line is made to connect the SPiN diodes string and DC bias supplies；
Make the SPiN diodes antenna arm, a SPiN diodes sleeve and the 2nd SPiN banks of diodes
Cylinder；
The coaxial feeder is made to connect the SPiN diodes antenna arm, a SPiN diodes sleeve and institute
The 2nd SPiN diode sleeves are stated, the sleeve-dipole antenna is ultimately formed.
In one embodiment of the invention, according to the structure of the sleeve-dipole antenna on the SiGeOI substrates
Multiple SPiN diode strings are made, including：
A () is on the SiGeOI substrates according to the structure setting isolated area of the sleeve-dipole antenna；
B () etches the SiGeOI substrates and forms p-type groove and N-type groove；
C () forms the first p-type active area and the first N-type in the p-type groove and the N-type groove using ion implanting
Active area；
D () fills the p-type groove and the N-type groove, and use ion implanting in the top layer of the SiGeOI substrates
The second p-type active area and the second N-type active area are formed in SiGe；
E () forms lead to form horizontal SPiN diodes on the SiGeOI substrates；
F () photoetching PAD is realizing the serial connection of multiple horizontal SPiN diodes so as to form multiple SPiN
Diode string.
In one embodiment of the invention, step (a) includes：
(a1) the first protective layer is formed in the SiGeOI substrate surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) the specified location etching described first using dry etch process in the first isolated area figure is protected
Layer and the SiGeOI substrates to form isolation channel, and the isolation channel top layer of the depth more than or equal to the SiGeOI substrates
The thickness of SiGe；
(a4) isolation channel is filled to form the isolated area.
In one embodiment of the invention, step (c) includes：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall shape of the p-type groove and the N-type groove
Into oxide layer；
(c2) oxide layer of the p-type groove and the N-type trench wall is etched to complete using wet-etching technology
State the planarizing of p-type groove and the N-type trench wall；
(c3) the p-type groove and the N-type groove are carried out ion implanting to form the first p-type active area and institute
State the first N-type active area.
In one embodiment of the invention, the first N-type active area is away from the N-type groove along ion dispersal direction
The region of side wall and bottom depth less than 1 micron, the first p-type active area is away from the p-type groove along ion dispersal direction
The region of side wall and bottom depth less than 1 micron.
In one embodiment of the invention, step (d), including：
(d1) fill the p-type groove and N-type groove to form P+ areas (27) and N+ areas (26) using polysilicon；
(d2) after SiGeOI substrates described in planarizing process, polysilicon layer is formed on the SiGeOI substrates；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the P+ areas (27) and the N+ areas
(26) implanting p-type impurity and N-type impurity are forming the second p-type active area and the second N-type active area and form p-type contact zone simultaneously
With N-type contact zone；
(d4) photoresist) is removed；
(d5) polysilicon beyond P-type electrode and N-type electrode is removed using wet etching.
In one embodiment of the invention, step (e) includes：
Silica is generated on the SiGeOI substrates；
The impurity in the p-type active area and N-type active area is activated using annealing process；
In the P+ areas (27) and N+ areas (26) lithography fair lead forming lead.
In one embodiment of the invention, direct current biasing line is prepared, including：
Prepare to form the direct current biasing line using copper, aluminium or highly doped polysilicon using CVD techniques.
In one embodiment of the invention, the SPiN diodes antenna arm, a SPiN diodes sleeve and
The SPiN diodes string of same number of the 2nd SPiN diodes sleeve including serial connection, and correspondence position
The SPiN diodes string includes the horizontal SPiN diodes of same number.
In one embodiment of the invention, the coaxial feeder is made, including：
The internal core wire of the coaxial feeder is connected to the SPiN diodes antenna arm and by outside the coaxial feeder
Conductor is connected to a SPiN diodes sleeve and the 2nd SPiN diode sleeves.
Compared with prior art, beneficial effects of the present invention：
Frequency reconfigurable sleeve-dipole antenna based on SiGe base SPiN diodes prepared by the present invention, small volume, cuts open
Face is low, simple structure, it is easy to process, without complicated feed structure, frequency can rapid jumping, and antenna close when will be in electromagnetic wave
Stealthy state, can be used for various frequency hopping radio sets or equipment；It is plane because its all constituents is in semiconductor chip side
Structure, it is easy to organize battle array, can be used as the basic component units of phased array antenna.
Brief description of the drawings
Fig. 1 is a kind of structural representation of SiGe fundamental frequencies restructural sleeve-dipole antenna provided in an embodiment of the present invention
Figure；
Fig. 2 is that a kind of preparation method of SiGe fundamental frequencies restructural sleeve-dipole antenna provided in an embodiment of the present invention is shown
It is intended to；
Fig. 3 is a kind of preparation method schematic diagram of SPiN diodes string provided in an embodiment of the present invention；
Fig. 4 is a kind of structural representation of horizontal SPiN diodes provided in an embodiment of the present invention；
Fig. 5 is a kind of structural representation of SPiN diodes string provided in an embodiment of the present invention；And
Fig. 6 a- Fig. 6 s are the preparation method schematic diagram of a kind of horizontal SPiN diodes of the embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of SiGe fundamental frequencies restructural sleeve-dipole antenna provided in an embodiment of the present invention
Structural representation.The antenna includes semiconductor chip 1, SPiN diodes antenna arm 2, a SPiN diodes sleeve 3, second
SPiN diodes sleeve 4, coaxial feeder 5, direct current biasing line 9,10,11,12,13,14,15,16,17,18,19；
The SPiN diodes antenna arm 2, the SPiN diodes sleeve 3, the 2nd SPiN diodes sleeve 4
And the direct current biasing line 9,10,11,12,13,14,15,16,17,18,19 is made on the semiconductor chip 1；It is described
SPiN diodes antenna arm 2 is with the SPiN diodes sleeve 3 and the 2nd SPiN diodes sleeve 4 by described same
Feeder shaft 5 is connected, and the internal core wire 7 of the coaxial feeder 5 connects the SPiN diodes antenna arm 2 and the coaxial feeder 5
Outer conductor 8 connects the SPiN diodes sleeve 3 and the 2nd SPiN diodes sleeve 4；
Wherein, the SPiN diodes antenna arm 2 includes SPiN diodes w1, w2, w3 of serial connection, described first
SPiN diodes sleeve 3 includes SPiN diodes w4, w5, w6 of serial connection, and the 2nd SPiN diodes sleeve 4 includes string
SPiN diode w7, w8, w9 of row connection, each described SPiN diodes string w1, w2, w3, w4, w5, w6, w7, w8, w9 pass through
The corresponding direct current biasing line 9,10,11,12,13,14,15,16,17,18,19 is connected to DC bias supplies.
Plasma antenna arm and set that the antenna is formed when being by metal direct current biasing line traffic control SPiN diode current flows
Tube length degree realizes the restructural of operating frequency of antenna, antenna of the invention have it is easy of integration, can stealthy, frequency can rapid jumping
Feature.
Refer to Fig. 2, a kind of Fig. 2 systems of SiGe fundamental frequencies restructural sleeve-dipole antenna provided in an embodiment of the present invention
Preparation Method schematic diagram.The preparation method of the antenna can include：
Choose SiGeOI substrates；
According to the structure fabrication multiple SPiN diode strings of the sleeve-dipole antenna on the SiGeOI substrates；
Direct current biasing line is made to connect the SPiN diodes string and DC bias supplies；
Make the SPiN diodes antenna arm, a SPiN diodes sleeve and the 2nd SPiN banks of diodes
Cylinder；
The coaxial feeder is made to connect the SPiN diodes antenna arm, a SPiN diodes sleeve and institute
The 2nd SPiN diode sleeves are stated, the sleeve-dipole antenna is ultimately formed.
Wherein, using SiGeOI substrates the reason for, is, for solid plasma antenna due to the good microwave of its needs
Characteristic, and solid plasma pin diodes are in order to meet this demand, it is necessary to possess good isolation characteristic and carrier i.e. solid
The restriction ability of state plasma, and SiGeOI substrates due to its have can with isolation channel be conveniently formed pin area of isolation,
Silica (SiO2) also can be that solid state plasma is limited in top layer silicon by carrier, it is advantageous to be made using SiGeOI
It is the substrate of solid plasma pin diodes.And the carrier mobility of sige material is than larger, therefore device performance can be improved.
Wherein, direct current biasing line is prepared, can be included：
Prepare to form the direct current biasing line using copper, aluminium or highly doped polysilicon using CVD techniques.
Preferably, the coaxial feeder is made, can be included：
The internal core wire of the coaxial feeder is connected to the SPiN diodes antenna arm and by outside the coaxial feeder
Conductor is connected to a SPiN diodes sleeve and the 2nd SPiN diode sleeves.
It should be noted that above-mentioned steps not have specific production order, can be according to reality in actually preparing
Situation is adjusted, and is not limited herein.
In the present embodiment, SPiN diodes antenna arm and SPiN diodes sleeve include N sections of SPiN diode string, N's
Span is N >=2.And the number of the SPiN diodes in every section of SPiN diode string can be chosen according to actual needs, herein
Any limitation is not done.
Preferably, N=3.I.e. described SPiN diodes antenna arm 2 includes three sections of SPiN diode strings w1, w2, w3.It is described
First SPiN diodes sleeve 3 and the 2nd SPiN diodes sleeve 4 include three sections of SPiN diode strings respectively, wherein, institute
Stating a SPiN diodes sleeve 3 includes three sections of SPiN diodes string w4, w5, w6, and the 2nd SPiN diodes sleeve 4 includes
Three sections of SPiN diode strings w7, w8, w9.And the SPiN diodes string w1 and the SPiN diodes string w6, the SPiN bis-
The equal length of pole pipe string w9, the SPiN diodes string w2 and the SPiN diodes string w5, the SPiN diodes string w8
Equal length, the SPiN diodes string w3 and SPiN diodes string w4, the length phase of the SPiN diodes string w7
Deng.Each SPiN diodes string also has direct current biasing line external voltage positive pole.
Antenna manufactured in the present embodiment, its frequency reconfigurable dipole antenna small volume, section are low, simple structure, are easy to
Processing, without complicated feed structure, frequency can rapid jumping, and antenna close when will in the stealthy state of electromagnetic wave, can be used for respectively
Plant frequency hopping radio set or equipment；It is planar structure, it is easy to organize battle array because its all constituents is in semiconductor chip side, can
Basic component units as phased array antenna.
Embodiment two
Fig. 3 is referred to, Fig. 3 is a kind of preparation method schematic diagram of SPiN diodes string provided in an embodiment of the present invention.Should
Preparation method may include steps of：
A () is on the SiGeOI substrates according to the structure setting isolated area of the sleeve-dipole antenna；
B () etches the SiGeOI substrates and forms p-type groove and N-type groove；
C () forms the first p-type active area and the first N-type in the p-type groove and the N-type groove using ion implanting
Active area；
D () fills the p-type groove and the N-type groove, and use ion implanting in the top layer of the SiGeOI substrates
The second p-type active area and the second N-type active area are formed in SiGe；
E () forms lead to form horizontal SPiN diodes on the SiGeOI substrates；
F () photoetching PAD is realizing the serial connection of multiple horizontal SPiN diodes so as to form multiple SPiN
Diode string.
Wherein, step (a) can include：
(a1) the first protective layer is formed in the SiGeOI substrate surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) the specified location etching described first using dry etch process in the first isolated area figure is protected
Layer and the SiGeOI substrates to form isolation channel, and the isolation channel top layer of the depth more than or equal to the SiGeOI substrates
The thickness of SiGe；
(a4) isolation channel is filled to form the isolated area.
Wherein, step (c) can include：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall shape of the p-type groove and the N-type groove
Into oxide layer；
(c2) oxide layer of the p-type groove and the N-type trench wall is etched to complete using wet-etching technology
State the planarizing of p-type groove and the N-type trench wall；Specifically, planarizing process can use following steps：Oxidation p-type
Groove and N-type groove are so that the inwall of p-type groove and N-type groove forms oxide layer；P-type groove is etched using wet-etching technology
With the oxide layer of N-type trench wall completing the planarizing of p-type groove and N-type trench wall.This have the advantage that：Can be with
Prevent the projection of trenched side-wall from forming electric field concentrated area, cause Pi and Ni junction breakdowns.
(c3) the p-type groove and the N-type groove are carried out ion implanting to form the first p-type active area and institute
State the first N-type active area.The first N-type active area is away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron, the first p-type active area is away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron.
The purpose for forming the first active area is：One layer of uniform heavily doped region, the region are formed in the side wall of groove
Heavily doped region in as Pi and Ni knots, and the formation of the first active area has following several benefits, to insert polysilicon in groove
Illustrated as a example by electrode, first, avoid hetero-junctions between polysilicon and Si and tied with Pi and Ni and overlap, caused performance
It is uncertain；Secondth, the diffusion velocity of impurity in the polysilicon characteristic faster than in Si can be utilized, is further expanded to P and N areas
Dissipate, further improve the doping concentration in P and N areas；3rd, this prevents during polysilicon process, polycrystalline silicon growth
The polysilicon that causes of inequality and cell wall between form cavity, the cavity can cause polysilicon bad with the contact of side wall, shadow
Ring device performance.
Wherein, step (d) can include：
(d1) fill the p-type groove and N-type groove to form P+ areas (27) and N+ areas (26) using polysilicon；
(d2) after SiGeOI substrates described in planarizing process, polysilicon layer is formed on the SiGeOI substrates；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the P+ areas (27) and the N+ areas
(26) implanting p-type impurity and N-type impurity are forming the second p-type active area and the second N-type active area and form p-type contact zone simultaneously
With N-type contact zone；
(d4) photoresist) is removed；
(d5) polysilicon beyond P-type electrode and N-type electrode is removed using wet etching.
Wherein, step (e) can include：
(e1) silica is generated on the SiGeOI substrates；
(e2) impurity in the p-type active area and N-type active area is activated using annealing process；
(e3) in the P+ areas (27) and N+ areas (26) lithography fair lead forming lead.
Show please also refer to the structure that Fig. 4 and Fig. 5, Fig. 4 are a kind of horizontal SPiN diodes provided in an embodiment of the present invention
It is intended to；Fig. 5 is a kind of structural representation of SPiN diodes string provided in an embodiment of the present invention.Wrapped in each SPiN diode string
Multiple transverse direction SPiN diodes are included, and these SPiN diodes are connected in series.Horizontal SPiN bis- in the SPiN diodes string
Pole pipe is made up of P+ areas 27, N+ areas 26 and intrinsic region 22, and metal contact zone 23 is located at P+ areas 27, and metal contact zone 24 is located at N+
At area 26, the metal contact zone 23 of the horizontal SPiN diodes of the one end in SPiN diode strings is being connected to direct current biasing just
Pole, the metal contact zone 24 of the horizontal SPiN diodes of the other end in SPiN diode strings is connected to the negative of direct current biasing
Pole, can make all horizontal SPiN diodes in whole SPiN diodes string be in forward conduction state by applying DC voltage.
Embodiment three
Refer to the preparation method of a kind of horizontal SPiN diodes that Fig. 6 a- Fig. 6 s, Fig. 6 a- Fig. 6 s are the embodiment of the present invention
Schematic diagram.The present embodiment on the basis of above-described embodiment, to prepare the SiGeOI bases SPiN that ion plasma length of field is 100 μm
Preparation as a example by diode (solid plasma PiN diodes) to SPiN diodes is described in detail, and comprises the following steps that：
Step 1, backing material preparation process：
(1a) as shown in Figure 6 a, chooses (100) crystal orientation, and doping type is p-type, and doping concentration is 1014cm-3SiGeOI
Substrate slice 101, the thickness of top layer Si Ge is 50 μm；
(1b) as shown in Figure 6 b, using chemical vapor deposition (Chemical vapor deposition, abbreviation CVD)
Method, deposits one layer of SiO of 40nm thickness on SiGeOI substrates2Layer 201；Using the method for chemical vapor deposition,
SiO2One layer of 2 Si of μ m thick of layer deposit3N4/ SiN layer 202；
Step 2, isolates preparation process：
(2a) as fig. 6 c, isolated area, wet etching isolated area is formed by photoetching process on above-mentioned protective layer
One Si3N4/ SiN layer 202, forms isolated area figure；Using dry etching, form wide 5 μm in isolated area, depth be 50 μm it is deep every
From groove 301；
(2b) as shown in fig 6d, using the method for CVD, deposits SiO2401 fill up the deep isolation trench；
(2c) as shown in fig 6e, using chemically mechanical polishing (Chemical Mechanical Polishing, referred to as
CMP) method, removes the Si of surface the3N4The SiO of/SiN layer 202 and the2Layer 201, makes SiGeOI substrate surfaces smooth；
Step 3, P, N area deep trouth preparation process：
(3a) as shown in Figure 6 f, using CVD method, the consecutive deposition materials at two layers on substrate, ground floor is 300nm thickness
The 2nd SiO2Layer 601, the second layer is the 2nd Si of 600nm thickness3N4/ SiN layer 602；
(3b) as shown in figure 6g, photoetching P, N areas deep trouth, the Si of wet etching P, N areas the 2nd3N4The SiO of/SiN layer 602 and the 2nd2
Layer 601, forms P, N area figure；Using dry etching, form wide 4 μm in P, N area, deep 5 μm deep trouth 701, the length of P, N area groove
Degree determines according to the applicable cases in prepared antenna；
(3c) as shown in figure 6h, at 850 DEG C, high-temperature process 10 minutes, oxidation trough inwall forms oxide layer 801；
(3d) removes the oxide layer 801 of P, N area groove inwall using wet-etching technology, so that P, N area groove as shown in Fig. 6 i
Inwall is smooth.
Step 4, P, N contact zone preparation process：
(4a) as shown in Fig. 6 j, photoetching P areas deep trouth carries out p using the method with glue ion implanting to P areas groove sidewall+Note
Enter, make to form thin p on the wall of side+Active area 1001, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4b) photoetching N areas deep trouth, n is carried out using the method with glue ion implanting to N areas groove sidewall+Injection, makes on the wall of side
Form thin n+Active area 1002, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4c) using the method for CVD, the depositing polysilicon 1101 in P, N area groove, and groove is filled up as shown in Fig. 6 k；
(4d), using CMP, removes the Si of surface polysilicon 1101 and the 2nd as shown in Fig. 6 l3N4/ SiN layer 602, puts down surface
It is whole；
(4e) as shown in Fig. 6 m, using the method for CVD, in one layer of polysilicon 1301 of surface deposition, thickness is 200~
500nm；
(4f) as shown in Fig. 6 n, photoetching P areas active area carries out p using band glue ion injection method+Injection, makes P areas active
Area's doping concentration reaches 0.5 × 1020cm-3, photoresist is removed, form P contacts 1401；
(4g) photoetching N areas active area, n is carried out using band glue ion injection method+Injection, makes N areas active area doping concentration
It is 0.5 × 1020cm-3, photoresist is removed, form N contacts 1402；
(4h), using wet etching, etches away the polysilicon 1301 beyond P, N contact zone as shown in Fig. 6 o, forms P, N and connects
Touch area；
(4i) as shown in Fig. 6 p, using the method for CVD, in surface deposition SiO21601, thickness is 800nm；
(4j) anneals 1 minute at 1000 DEG C, makes the impurity activation of ion implanting and advances impurity in polycrystalline germanium；
Step 5, constitutes PIN diode step：
(5a) as shown in Fig. 6 q, the lithography fair lead 1701 in P, N contact zone；
(5b) as shown in Fig. 6 r, substrate surface splash-proofing sputtering metal forms metal silicide 1801, and etch in 750 DEG C of alloys
Fall the metal on surface；
(5c) substrate surface splash-proofing sputtering metal, photoetching lead；
(5d) deposits Si as shown in Fig. 6 s3N4/ SiN forms passivation layer 1901, and photoetching PAD forms PIN diode, as
Prepare solid plasma antenna material.
In the present embodiment, above-mentioned various technological parameters are for example, according to the conventional meanses of those skilled in the art
The conversion done is the protection domain of the application.
The SPiN diodes for being applied to solid plasma reconfigurable antenna prepared by the present invention, first, the SiGe for being used
Material, due to its high mobility and the characteristic of big carrier lifetime, improves the solid plasma bulk concentration of SPiN diodes；Separately
Outward, the P areas of SPiN diodes employ the polysilicon damascene technique of the deep etching based on etching with N areas, and the technique can be carried
Tied for abrupt junction pi and ni, and pi knots, the junction depth of ni knots can be effectively improved, make the concentration of solid state plasma and distribution
Controllability enhancing, be conducive to preparing high performance plasma antenna；Again, what prepared by the present invention is applied to solid plasma
The SPiN diodes of reconfigurable antenna employ a kind of Deep trench isolation technique based on etching, are effectively improved device
Breakdown voltage, it is suppressed that influence of the leakage current to device performance.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to assert
Specific implementation of the invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should be all considered as belonging to of the invention
Protection domain.
Claims (10)
1. a kind of preparation method of SiGe fundamental frequencies restructural sleeve-dipole antenna, it is characterised in that the antenna includes
It is SiGeOI substrates, SPiN diodes antenna arm, a SPiN diodes sleeve, the 2nd SPiN diodes sleeve, coaxial feeder, straight
Stream offset line；Wherein, the preparation method includes：
Choose SiGeOI substrates；
According to the structure fabrication multiple SPiN diode strings of the sleeve-dipole antenna on the SiGeOI substrates；
Direct current biasing line is made to connect the SPiN diodes string and DC bias supplies；
Make the SPiN diodes antenna arm, a SPiN diodes sleeve and the 2nd SPiN diode sleeves；
The coaxial feeder is made to connect the SPiN diodes antenna arm, a SPiN diodes sleeve and described
Two SPiN diode sleeves, ultimately form the sleeve-dipole antenna.
2. preparation method according to claim 2, according to the sleeve-dipole antenna on the SiGeOI substrates
Structure fabrication multiple SPiN diode strings, including：
A () is on the SiGeOI substrates according to the structure setting isolated area of the sleeve-dipole antenna；
B () etches the SiGeOI substrates and forms p-type groove and N-type groove；
C () forms the first p-type active area using ion implanting in the p-type groove and the N-type groove and the first N-type is active
Area；
D () fills the p-type groove and the N-type groove, and use ion implanting in the top layer Si Ge of the SiGeOI substrates
It is interior to form the second p-type active area and the second N-type active area；
E () forms lead to form horizontal SPiN diodes on the SiGeOI substrates；
F () photoetching PAD is realizing the serial connection of multiple horizontal SPiN diodes so as to form multiple poles of the SPiN bis-
Pipe string.
3. preparation method according to claim 2, it is characterised in that step (a) includes：
(a1) the first protective layer is formed in the SiGeOI substrate surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) using dry etch process the specified location of the first isolated area figure etch first protective layer and
The SiGeOI substrates to form isolation channel, and the isolation channel top layer Si Ge of the depth more than or equal to the SiGeOI substrates
Thickness；
(a4) isolation channel is filled to form the isolated area.
4. preparation method according to claim 2, it is characterised in that step (c) includes：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall of the p-type groove and the N-type groove forms oxygen
Change layer；
(c2) etch the oxide layer of the p-type groove and the N-type trench wall to complete the p-type using wet-etching technology
The planarizing of groove and the N-type trench wall；
(c3) carry out ion implanting to the p-type groove and the N-type groove to form the first p-type active area and described
One N-type active area.
5. preparation method according to claim 3, it is characterised in that the first N-type active area is along ion diffused sheet
To the region away from the N-type trenched side-wall and bottom depth less than 1 micron, the first p-type active area is along ion diffused sheet
To the region away from the p-type trenched side-wall and bottom depth less than 1 micron.
6. preparation method according to claim 3, it is characterised in that step (d), including：
(d1) fill the p-type groove and N-type groove to form P+ areas (27) and N+ areas (26) using polysilicon；
(d2) after SiGeOI substrates described in planarizing process, polysilicon layer is formed on the SiGeOI substrates；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the P+ areas (27) and the N+ areas (26)
Implanting p-type impurity and N-type impurity are forming the second p-type active area and the second N-type active area and form p-type contact zone and N simultaneously
Type contact zone；
(d4) photoresist) is removed；
(d5) polysilicon beyond P-type electrode and N-type electrode is removed using wet etching.
7. preparation method according to claim 2, it is characterised in that step (e) includes：
Silica is generated on the SiGeOI substrates；
The impurity in the p-type active area and N-type active area is activated using annealing process；
In the P+ areas (27) and N+ areas (26) lithography fair lead forming lead.
8. preparation method according to claim 1, it is characterised in that prepare direct current biasing line, including：
Prepare to form the direct current biasing line using copper, aluminium or highly doped polysilicon using CVD techniques.
9. preparation method according to claim 1, it is characterised in that the SPiN diodes antenna arm, described first
SPiN diodes sleeve and the 2nd SPiN diodes sleeve include the poles of the SPiN bis- of the same number of serial connection
Pipe string, and the SPiN diodes string of correspondence position includes the horizontal SPiN diodes of same number.
10. preparation method according to claim 1, it is characterised in that make the coaxial feeder, including：
The internal core wire of the coaxial feeder is connected to the SPiN diodes antenna arm and by the outer conductor of the coaxial feeder
It is connected to a SPiN diodes sleeve and the 2nd SPiN diode sleeves.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102903736A (en) * | 2011-07-27 | 2013-01-30 | 中国科学院微电子研究所 | Diode and manufacturing method thereof |
| US20130025785A1 (en) * | 2009-01-07 | 2013-01-31 | Lam Research Corporation | Profile and cd uniformity control by plasma oxidation treatment |
| CN103871900A (en) * | 2014-03-06 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Groove field effect transistor and forming method thereof |
| CN104992942A (en) * | 2015-07-03 | 2015-10-21 | 西安电子科技大学 | Vertically-stacked strain Si/SiGe heterojunction CMOS device structure and preparation method thereof |
-
2016
- 2016-12-20 CN CN201611184362.6A patent/CN106876871A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130025785A1 (en) * | 2009-01-07 | 2013-01-31 | Lam Research Corporation | Profile and cd uniformity control by plasma oxidation treatment |
| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102903736A (en) * | 2011-07-27 | 2013-01-30 | 中国科学院微电子研究所 | Diode and manufacturing method thereof |
| CN103871900A (en) * | 2014-03-06 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Groove field effect transistor and forming method thereof |
| CN104992942A (en) * | 2015-07-03 | 2015-10-21 | 西安电子科技大学 | Vertically-stacked strain Si/SiGe heterojunction CMOS device structure and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| DA-JIN KIM等: "Optomization of the Intrinsic Length of a PIN Diode for a Reconfigurable Antenna", 《2016 INTERNATIONAL CONFERENCE ON ELECTRONICS，INFORMATION，AND COMMUNICATIONS》 * |
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