CN103871900A - Groove field effect transistor and forming method thereof - Google Patents

Groove field effect transistor and forming method thereof Download PDF

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Publication number
CN103871900A
CN103871900A CN201410081140.6A CN201410081140A CN103871900A CN 103871900 A CN103871900 A CN 103871900A CN 201410081140 A CN201410081140 A CN 201410081140A CN 103871900 A CN103871900 A CN 103871900A
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tagma
gate dielectric
grid
epitaxial loayer
trench fet
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楼颖颖
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

Abstract

The invention relates to a groove field effect transistor and a forming method thereof. The groove field effect transistor comprises a semiconductor substrate, an epitaxial layer located on the first surface of the semiconductor substrate, multiple independent grid electrodes located in the epitaxial layer, grid medium layers located in the epitaxial layer and at the peripheries of the grid electrodes, and body areas located in the epitaxial layer and between each two adjacent grid electrodes, wherein the upper surfaces of the grid medium layers and those of the grid electrodes are flush with the upper surface of the epitaxial layer, the body areas and the grid electrodes are isolated by the grid medium layers, and the depth of each body area is gradually increased from the middle to the corresponding grid electrode. The depth of each body area is gradually increased from the middle to the corresponding grid electrode, i.e., the minimum depth of each body area is located in the middle of the body area, so that the resistance of each body area is favorably reduced, the break-over voltage of the groove field effect transistor is reduced along with the reduction of the resistance of each body area, and thus the tolerance performance of the groove field effect transistor is improved.

Description

Trench FET and forming method thereof
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of trench FET and forming method thereof.
Background technology
Along with developing rapidly of microelectric technique, the research of integrated circuit has entered SOC (system on a chip) (SOC) epoch with application.Integrated level and the frequency of operation of single-chip are more and more higher, and integrated level has reached every chip the more than one hundred million transistor of the order of magnitude, and is improving constantly, and this has just caused the characteristic size of device constantly to reduce.Research and production goes out as the small size of integrated circuit primary element, at a high speed, the needs of the power device microelectric technique development of low-power consumption.In order to meet the demand of high power transistor, there is having the MOS transistor of vertical trench, representational have a trench FET.Trench FET has not only been inherited the advantages such as the input impedance of horizontal channel MOS transistor is high, drive current is little, also has the advantages such as high pressure resistant, operating current is large, power output is high, switching speed is fast.
But the poor problem of tolerance performance (ruggedness) of existing trench FET, is easily burnt while work in load circuit.
Please refer to Fig. 1, show trench FET and apply to load and have the circuit of inductance.In described circuit; conventionally by supply voltage VDD(unipolar device), K switch, trench FET M and inductance L loop in series; and conventionally also can be connected with a diode D2; diode D2 is simultaneously in parallel with trench FET M and inductance L, can form an inherence (built-in) diode D1 and trench FET M self is inner.When in circuit, in the transfer process of K switch from ON state to OFF state, inductance L can make the electric current in circuit suddenly increase, thereby affect trench FET M, concrete, inductance L can be discharged into trench FET M by the electric current larger than common operating current, if the tolerance poor-performing of trench FET M, trench FET M is just probably burnt.
For this reason, need a kind of new trench FET and forming method thereof, prevent that trench FET from easily being burnt.
Summary of the invention
The problem that the present invention solves is to provide a kind of trench FET and forming method thereof, to improve the tolerance performance of trench FET.
For addressing the above problem, the invention provides a kind of trench FET, comprising:
Semiconductor substrate;
Be positioned at the epitaxial loayer on described Semiconductor substrate first surface;
Be arranged in the multiple discrete grid of described epitaxial loayer;
Be positioned at described epitaxial loayer and be positioned at the gate dielectric layer of described grid periphery, described gate dielectric layer upper surface, described gate upper surface and described epitaxial loayer upper surface flush;
Tagma in described epitaxial loayer and between adjacent two grids, described tagma and described grid are isolated by described gate dielectric layer;
The degree of depth in described tagma increases gradually from centre position to grid direction.
Optionally, the minimum-depth in described tagma is 0.2 μ m～0.4 μ m.
Optionally, described trench FET also comprises: be arranged in the source region in described tagma, described source region upper surface and described epitaxial loayer upper surface flush.
Optionally, described Semiconductor substrate has the second surface relative with described first surface, on described second surface, has drain region.
For addressing the above problem, the present invention also provides a kind of formation method of trench FET, comprising:
Semiconductor substrate is provided;
On the first surface of described Semiconductor substrate, form epitaxial loayer;
In described epitaxial loayer, form multiple discrete grooves;
Form gate dielectric layer at described grooved inner surface;
On described gate dielectric layer, form grid, common full described groove, described gate dielectric layer upper surface, described gate upper surface and the described epitaxial loayer upper surface flush of filling of described gate dielectric layer and described grid;
On described epitaxial loayer, form mask layer, the width of described mask layer is less than the distance between adjacent two described gate dielectric layers, and described mask layer equates to the distance between adjacent two described gate dielectric layers;
Taking described mask layer as mask, the described epitaxial loayer between adjacent two described gate dielectric layers to be adulterated and forms tagma, the degree of depth in described tagma increases gradually from centre position to grid direction.
Optionally, the minimum-depth in described tagma is 0.2 μ m～0.4 μ m.
Optionally, the width range of described mask layer is 0.3 times～0.5 times of distance between adjacent two described gate dielectric layers, and the thickness range of described mask layer is 0.5 μ m～1.5 μ m.
Optionally, after forming described grid, and before forming described mask layer, described formation method also comprises: on described grid, described gate dielectric layer and described epitaxial loayer, form insulating protective layer, described mask layer is formed on described insulating protective layer surface.
Optionally, after forming described tagma, described formation method also comprises: carry out heavy doping formation source region to being positioned at the described epitaxial loayer of top, described tagma.
Optionally, after forming described source region, described formation method also comprises:
On described insulating protective layer, form interlayer dielectric layer;
Interlayer dielectric layer, insulating protective layer and source region described in etching are until form through hole, and described through hole, between adjacent two described gate dielectric layers, and is divided into remaining two parts by described source region;
Fill described through hole and form conductive plunger.
Optionally, the material of described mask layer is negative photoresist.
Optionally, in the process in the described tagma of formation of adulterating, when N-type doping is carried out in described tagma, the ion of doping is boron ion, and the ion concentration scope of doping is 1E12/cm 3～1E13/cm 3, the energy range of employing is 40KeV～80KeV; When the doping of P type is carried out in described tagma, the ion of doping is phosphonium ion, and the ion concentration scope of doping is 1E13/cm 3～1E14/cm 3, the energy range of employing is 100KeV～160KeV.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, provide a kind of trench FET, described trench FET comprises: Semiconductor substrate; Be positioned at the epitaxial loayer on described Semiconductor substrate first surface; Be arranged in the multiple discrete grid of described epitaxial loayer; Be positioned at described epitaxial loayer and be positioned at the gate dielectric layer of described grid periphery, described gate dielectric layer upper surface, described gate upper surface and described epitaxial loayer upper surface flush; Tagma in described epitaxial loayer and between adjacent two grids, described tagma and described grid are isolated by described gate dielectric layer; Wherein, the degree of depth in described tagma increases gradually from centre position to grid direction.Because the degree of depth in described tagma increases gradually from centre position to grid direction, the minimum-depth that is tagma is positioned at centre position, tagma, and tagma resistance is directly proportional to the degree of depth in centre position, tagma, therefore, in the time that the minimum-depth in tagma is positioned at centre position, tagma, tagma resistance reduces, the conducting voltage of trench FET equals electric current in circuit and the product of tagma resistance and plug resistance sum, therefore the conducting voltage sat-zone resistance of trench FET reduces and reduces, the tolerance performance of trench FET improves along with the reduction of the conducting voltage of trench FET.
Further, in the time forming described trench FET, adopt negative photoresist to form mask layer, described mask layer is positioned on the described epitaxial loayer in adjacent two described gate dielectric layer centre positions.Now, form mask layer and can directly adopt the follow-up mask that applies to make through hole (conductive plunger).Same mask applies to two different process steps in trench FET forming process, can save the usage quantity of mask, cost-saving.
Further, the scope of the width of mask layer is 0.3 times～0.5 times of distance between adjacent two gate dielectric layers.If the width of mask layer exceedes 0.5 times of distance between two grooves,, after adulterating, the degree of depth in the whole tagma of formation all can be too little, causes that follow-up to be formed on channel length in tagma too short, and short-channel effect easily occurs transistor.If the width of mask layer is less than 0.3 times of distance between two grooves,, after adulterating, the tagma degree of depth of formation is too large, causes tagma resistance to be reduced to required, and transistorized tolerance performance cannot be brought up to desired level.
Brief description of the drawings
Fig. 1 is that trench FET applies to load and has the circuit diagram of inductance;
Fig. 2 is the cross-sectional view of existing trench FET;
Fig. 3 is the cross-sectional view of the trench FET that provides of the embodiment of the present invention;
Fig. 4 to Figure 13 is the cross-sectional view corresponding to the each step of formation method of the trench FET that provides of further embodiment of this invention.
Embodiment
Please refer to Fig. 2, show existing trench FET.Existing trench FET comprises Semiconductor substrate 100, on the first surface (not mark) of Semiconductor substrate 100, has epitaxial loayer 110.On epitaxial loayer 110, there is tagma 120, gate dielectric layer 140 and grid 150.Tagma 120 is between adjacent gate dielectric layer 140.Grid 150 is surrounded by gate dielectric layer 140.120 tops, tagma have source region 130.On tagma 120, also there is conductive plunger 160.Respectively there is a source region 130 conductive plunger 160 both sides.On the second surface relative with first surface in Semiconductor substrate 100 (not mark), also there is drain electrode 170.
Please continue to refer to Fig. 2, in trench FET, tagma 120 has tagma resistance R p, and conductive plunger 160 has plug resistance Rc.In the time that trench FET is connected in the circuit that electric current is I, the conducting voltage (Vbe) of trench FET meets: Vbe=I (Rp+Rc).
Conducting voltage is the important measurement index of trench FET tolerance performance, and conducting voltage is lower conventionally, and the tolerance performance of trench FET is better.Trench FET conventionally can be by reducing conducting voltage (Vbe) to improve the tolerance performance of trench FET.Improve the tolerance performance of trench FET, be greater than 0.7V if must control conducting voltage lower than 0.7V(conducting voltage, trench FET is easily burnt).Due to the normally steady job electric current in circuit of electric current I, Rc is conventionally less for plug resistance, and the two is all more difficult changes conventionally.Therefore conventionally adopt the tolerance performance of the method raising trench FET that reduces tagma resistance R p.
But existing method is conventionally by increasing the doping content in tagma 120 to reduce tagma resistance R p, thereby the conducting voltage of trench FET is reduced to below 0.7V.But the doping that increases tagma 120 can affect trench FET and can produce other adverse effect, the problems such as such as threshold of appearance threshold voltage (Vth) rising and drain-source breakdown voltage (BVDss) reduction.
For this reason, the invention provides a kind of new trench FET and forming method thereof, described trench FET comprises Semiconductor substrate, be positioned at the epitaxial loayer on described Semiconductor substrate first surface, be arranged in the multiple discrete grid of described epitaxial loayer, be positioned at described epitaxial loayer and be positioned at the gate dielectric layer of described grid periphery, described gate dielectric layer upper surface, described gate upper surface and described epitaxial loayer upper surface flush, tagma in described epitaxial loayer and between adjacent two grids, described tagma and described grid are isolated by described gate dielectric layer, the degree of depth in described tagma increases gradually from centre position to grid direction.The degree of depth in described tagma increases gradually from centre position to grid direction, be that described trench FET is less the closer to adjacent two described gate dielectric layer centre position degree of depth, therefore, the centre position in described tagma has minimum-depth, and (for the minimum-depth of existing trench FET tagma) trench FET provided by the invention tagma minimum-depth reduces, thereby tagma resistance is reduced, the conducting voltage that ensures trench FET is reduced to below 0.7V, improve the tolerance performance of trench FET, and prevent the problem that trench FET threshold of appearance threshold voltage raises or drain-source breakdown voltage reduces.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Please refer to Fig. 3, show the trench FET that the embodiment of the present invention provides.
As shown in Figure 3, the trench FET that the present embodiment provides comprises Semiconductor substrate 200, be positioned at the epitaxial loayer 210 on Semiconductor substrate 200 first surfaces (not mark), be arranged in the multiple discrete grid 250 of epitaxial loayer 210, be positioned at epitaxial loayer 210 and be positioned at the gate dielectric layer 240 of grid 250 peripheries.Gate dielectric layer 240 upper surfaces, grid 250 upper surfaces and epitaxial loayer 310 upper surface flush.Tagma 220 in epitaxial loayer 310 and between adjacent two grids 250, tagma 220 isolates by gate dielectric layer 240 with grid 250.Wherein, the degree of depth in tagma 220 increases gradually from centre position to grid 250 directions, and tagma 220 is less the closer to the adjacent gate dielectric layer 240 centre position degree of depth.
In the present embodiment, also have source region 230 in tagma 220, source region 230 is positioned at the position of 220 the tops, tagma, and the upper surface in source region 230 and grid 250 upper surface flush.
In the present embodiment, Semiconductor substrate 200 also has the second surface relative with first surface (not mark), has drain region 270 on described second surface.
In the present embodiment, gate dielectric layer 240 is " U " type, and grid 250 is surrounded by gate dielectric layer 240, and therefore, tagma 220 isolates by gate dielectric layer 240 with grid 250.Be arranged in the region, channel region of a trench FET of the tagma 220 each formation of meeting in gate dielectric layer 240 outsides, and these two trench FETs share a grid 250, a grid 250 is simultaneously for controlling two trench FETs that are positioned at its both sides.
In the present embodiment, tagma 220 is between adjacent gate dielectric layer 240.Source region 230 is positioned at the position of 220 the tops, tagma, between source region 230 and grid 250, is also isolated by gate dielectric layer 240.On tagma 220, also there is conductive plunger 260, two source regions 230 of conductive plunger 260 space between adjacent, a conductive plunger 260 is electrically connected two source regions 230 simultaneously.And for different source region 230, it is alternately separated by gate dielectric layer 240 and conductive plunger 260.Another source region 230 being separated by gate dielectric layer 240 in Fig. 3 is not shown, but can know by inference, wherein two source regions 230 that are not illustrated be arranged in Fig. 3 leftmost side with left (not shown) and the rightmost side with right (not shown).
In the present embodiment, the material of Semiconductor substrate 200 can be silicon substrate, germanium substrate or germanium silicon substrate etc., and the present embodiment is taking silicon substrate as example.Semiconductor substrate 200 provides a carrier for forming various semiconductor device.Semiconductor substrate 200 can be carried out light dope, for example, can carry out N-type doping, and now epitaxial loayer 210 is also N-type doping, and tagma 220 is the doping of P type, and source region 230 is N-type (weight) doping.Semiconductor substrate 200 also can be carried out the doping of P type, and now epitaxial loayer 210 is also the doping of P type, and tagma 220 is N-type doping, and source region 230 is P type (weight) doping.
In the present embodiment, the material of epitaxial loayer 210 is identical with Semiconductor substrate 200, and in the time that the material of Semiconductor substrate 200 is silicon, the material of epitaxial loayer 210 is also silicon, and can adopt epitaxial growth method to form epitaxial loayer 210, and epitaxial loayer 210 is generally mono-crystalline structures.
In the present embodiment, the material of gate dielectric layer 240 can be the insulating material such as silica, silicon nitride or silicon oxynitride, corresponding, can form gate dielectric layer 240 by thermal oxidation method or sedimentation.
In the present embodiment, the material of grid 250 can be polysilicon, can adopt deposition process to form grid 250, and can carry out Implantation to improve its electric conductivity to grid 250.
In the present embodiment, tagma 220 is that epitaxial loayer 210 forms through overdoping.And the degree of depth in tagma 220 increases gradually from centre position to grid 250 directions, tagma 220 is less the closer to adjacent two gate dielectric layers, the 240 centre position degree of depth.Therefore, the minimum-depth in tagma 220 there will be in the middle of adjacent two gate dielectric layers 240.
The minimum-depth in existing trench FET tagma is conventionally more than 0.5 μ m, and therefore, its tagma resistance is large (can with reference to figure 2 related contents) conventionally.
In the present embodiment, the minimum-depth in tagma 220 is 0.2 μ m～0.4 μ m.Concrete, upwards cave in 220 centre positions, tagma that the present embodiment forms, and therefore the minimum-depth in tagma 220 appears at 220 centre positions, tagma, and the scope of this minimum-depth is 0.2 μ m～0.4 μ m.Have according to resistance formula: R=ρ L/S, wherein L is the minimum-depth in tagma 360, tagma resistance is directly proportional to the minimum-depth in tagma 360, in the present embodiment, the scope of tagma 360 minimum-depths is 0.2 μ m～0.4 μ m, therefore the minimum-depth that, tagma resistance can be reduced to the original tagma 360 of 0.4 original～0.8(is more than 0.5 μ m).
Known according to above analysis, in the present embodiment, resistance R b in tagma can be reduced to original 0.4～0.8.For trench FET, that its conducting voltage equals tagma resistance and plug resistance and be multiplied by electric current, that is: the formula of conducting voltage (Vbe): Vbe=I (Rb+Rct).And plug resistance Rct is conventionally much smaller than tagma resistance R b, therefore, can think that conducting voltage is directly proportional to tagma resistance R b, in the present embodiment, because tagma resistance R b can be reduced to original 0.4～0.8, therefore, conducting voltage also can be reduced to approximately 0.4～0.8, thereby ensures that conducting voltage is reduced to 0.7V following (the originally about 0.7V of conducting voltage).Known according to above analysis, in the present embodiment, conducting voltage can remain and be less than 0.7V, and therefore, the tolerance performance of trench FET is improved, and trench FET is difficult for burning.And the trench FET of the present embodiment does not need to change the doping content in tagma 220, therefore, the performance such as threshold voltage and drain-source breakdown voltage of trench FET is unaffected.
Incorporated by reference to reference to figure 4 to Figure 13, further embodiment of this invention also provides a kind of formation method of trench FET, and Fig. 4 to Figure 13 shows the cross-sectional view corresponding to the each step of formation method of the trench FET that the present embodiment provides.
Please refer to Fig. 4, Semiconductor substrate 300 is provided.
In the present embodiment, the material of Semiconductor substrate 300 can be silicon, germanium or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, also can be mixed semiconductor's material, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide or their combination in any can be still silicon-on-insulator (SOI), germanium or SiGe (SiGe).
Please continue to refer to Fig. 4, at the upper epitaxial loayer 310 that forms of first surface (not mark) of Semiconductor substrate 300.
In the present embodiment, the material of epitaxial loayer 310 is identical with the material of Semiconductor substrate 300, and epitaxial loayer 310 can adopt epitaxial growth method to be formed on the first surface of Semiconductor substrate 300, and epitaxial loayer 310 is generally mono-crystalline structures.
Please continue to refer to Fig. 4, epitaxial loayer 310 is carried out to etching and form multiple discrete grooves 311, adjacent two grooves 311 wherein shown in Fig. 4.
In the present embodiment, the detailed process that forms groove 311 can be: on epitaxial loayer 310, form etching barrier layer (not shown), then on etching barrier layer, form photoresist layer (not shown), adopt afterwards the mask plate with groove 311 figures to expose to photoresist layer, develop again, obtain having the photoresist layer of groove 311 figures.Taking the photoresist layer with groove 311 figures as mask, adopt the lithographic methods such as reactive ion etching method, on etching barrier layer, etching forms groove 311 figure opening (not shown).Then taking the etching barrier layer with groove 311 figure openings as mask, adopt the methods such as wet etching or dry etching, remove the epitaxial loayer 310 that the barrier layer that is not etched covers, in 310 layers of described epitaxial loayers, form groove 311.After this can adopt the methods such as chemical cleaning to remove photoresist layer and etching barrier layer.In said process, in order to ensure exposure accuracy, also can between photoresist layer and etching barrier layer, form anti-reflecting layer (not shown).
Please refer to Fig. 5, form gate dielectric layer 320 at groove 311 inner surfaces.
In the present embodiment, groove 311 inner surfaces comprise bottom and sidewall, and the gate dielectric layer 320 that is formed on groove 311 inner surfaces is " U " type.The groove 311 that in Fig. 5, " U " type gate dielectric layer 320 inside still exist, groove 311 is follow-up forms grid (please refer to Fig. 6) for filling.And the each region, channel region that forms a trench FET of extended meeting behind two outsides of " U " type gate dielectric layer 320,, in the final trench FET forming, two trench FETs share a gate dielectric layer 320.
In the present embodiment, gate dielectric layer 320 can be the insulating material such as silica, silicon nitride or silicon oxynitride.In the time that the material of gate dielectric layer 320 is silica, can adopt the thermal oxidation technology gate dielectric layer 320 of growing on groove 311 bottoms and sidewall.
Please refer to Fig. 6, fill the grid 330 of full groove 311 in the interior formation of gate dielectric layer 320, gate dielectric layer 320 upper surfaces, grid 330 upper surfaces and epitaxial loayer 310 upper surface flush.
In the present embodiment, as noted earlier, grid 330 is surrounded by gate dielectric layer 320, and two trench FETs share a grid 330.
In the present embodiment, can adopt the method such as chemical vapour deposition technique or plasma enhanced CVD method at the certain thickness original position heavily doped polysilicon of gate dielectric layer 320 surface deposition, then carry out planarization, form the grid 330 of filling full groove 311.The doping content of described heavily doped polysilicon region can be greater than 1E19/cm 3thereby, ensure that grid 330 resistance are less.Described planarization process can make gate dielectric layer 320 upper surfaces, grid 330 upper surfaces and epitaxial loayer 310 upper surface flush simultaneously.
Please refer to Fig. 7, on grid 330, gate dielectric layer 320 and epitaxial loayer 310, form insulating protective layer 340.
In the present embodiment, the material of insulating protective layer 340 can be silica, can adopt CVD (Chemical Vapor Deposition) method to form insulating protective layer 340.
The meaning that forms insulating protective layer 340 is: in the process in follow-up formation tagma, and (Implantation) technique and propelling (driving) technique of conventionally need to adulterating, advancing technique object is to activate the ion adulterating; Conventionally advancing technique is to adopt the high temperature anneal to complete, and therefore, in propelling technical process, transistor is conventionally under hot conditions and keeps long period of time; If do not form insulating protective layer 340, now the ion in grid 330 very likely spreads, thereby causes transistorized performance to be damaged; The present embodiment forms insulating protective layer 340, can prevent that in propelling technical process, ion diffusion occurs the grid 330 of high-dopant concentration, thereby improves transistorized reliability, improves and produces yield.
It should be noted that, when in the process of follow-up formation tagma, advance lower and time of technological temperature more in short-term, can form this insulating protective layer, now mask layer can be formed directly on epitaxial loayer.
Please refer to Fig. 8, form mask layer 350 on insulating protective layer 340 surfaces, mask layer 350 is positioned on the epitaxial loayer 310 in adjacent two grid 330 centre positions.
In the present embodiment, as shown in Figure 8, the width W of mask layer 350 is less than the distance B between adjacent two gate dielectric layers 320, and mask layer 350 is equal to the distance between adjacent two gate dielectric layers 320 (not mark), mask layer 350 is positioned on the middle epitaxial loayer 310 of adjacent two gate dielectric layers 320.
In the present embodiment, the scope of the width W of mask layer 350 can be 0.3 times～0.5 times of distance B between adjacent two gate dielectric layers 320.Conventionally between adjacent two gate dielectric layers 320, distance B can be controlled in 0.4 μ m～1.5 μ m conventionally.The width W of mask layer 350 should not exceed 0.5 times of distance B between two grooves 311.If the width W of mask layer 350 exceedes 0.5 times of distance B between two grooves 311,, after adulterating, the tagma degree of depth of follow-up formation can be too little, causes follow-up channel length too short, and short-channel effect easily occurs transistor.If the width W of mask layer 350 is less than 0.3 times of distance B between two grooves 311,, after adulterating, the tagma degree of depth of follow-up formation is too large, causes tagma resistance to be reduced to required, and transistorized tolerance performance cannot be brought up to desired level.
In the present embodiment, the thickness T scope of mask layer 350 is 0.5 μ m～1.5 μ m.Same, the thickness T of mask layer 350 is too large, the tagma degree of depth of follow-up formation can be too little, even cannot form complete tagma, and the thickness of mask layer 350 is too little, the minimum-depth that cannot ensure the tagma of follow-up formation reaches necessary requirement, thereby cannot reduce tagma resistance, and then cannot improve transistorized tolerance performance.
In the present embodiment, the material of mask layer 350 can be negative photoresist.Now, can directly adopt the mask (not shown) for making through hole (please refer to Figure 12) to make mask layer 350.This be because, the position of follow-up conductive plunger (please refer to Figure 13) is also between adjacent two gate dielectric layers 320, the width of conductive plunger also can be arranged on 0.3 times～0.5 times of distance B between two grooves 311, therefore, can directly adopt the mask that forms through hole (that is forming conductive plunger) to be used to form mask layer 350.Concrete, adopt this mask negative photoresist is exposed and develop, form the mask layer 350 of on the epitaxial loayer 310 between adjacent two gate dielectric layers 320 (and being on insulating protective layer 340 surfaces).In the present embodiment, two processing steps adopt same mask, can save the usage quantity of mask, cost-saving.
It should be noted that, in other embodiments of the invention, also can adopt separately a mask to be used to form mask layer 350, now the material of mask layer 350 can not be defined as negative photoresist, and can be positive photoresist or other applicable material.
Please refer to Fig. 9, taking mask layer 350 shown in Fig. 8 as mask, epitaxial loayer 310 between adjacent two gate dielectric layers 320 is adulterated and forms tagma 360.After forming tagma 360, can remove mask layer 350 shown in Fig. 8.
In the present embodiment, after adulterating, proceed to advance technique, to activate the ion that injects tagma 360.Only carry out doping process, the ion of doping may also can not be positioned at mask layer 350(and please refer to Fig. 8) under position, but advance just technique, ion is spread, form the tagma of real meaning.Concrete, described propelling technique can adopt thermal anneal process to carry out, and the temperature range that thermal annealing adopts is 900 DEG C～1050 DEG C, and advancing the duration (annealing time) of technique can be 10min～60min.After advancing technique, having there is abundant diffusion in the ion of doping, has formed tagma 360 as shown in Figure 9.The degree of depth in tagma 360 increases gradually from centre position to grid 330 directions, and, the closer to adjacent two grid 330 centre positions, tagma 360 degree of depth are less.
In the present embodiment, if the doping type in tagma 360 is N-type, doping ion can be phosphorus or other pentads, if doping type is P type, doping ion can be boron or other triads.Concrete, when N-type doping is carried out in tagma 360, the ion of doping can be boron ion, the concentration range of the ion of doping can be 1E12/cm 3～1E13/cm 3, the energy range of employing can be 40KeV～80KeV.When the doping of P type is carried out in tagma 360, the ion of doping can be phosphonium ion, and the concentration range of doping ion can be 1E13/cm 3～1E14/cm 3, the energy range of employing can be 100KeV～160KeV.
In the present embodiment, after carrying out above-mentioned doping and advancing technique, the tagma 360 forming has such profile: the degree of depth in tagma 360 increases gradually from centre position to grid 330 directions, and tagma 360 is less the closer to adjacent two grids, the 330 centre position degree of depth.This be because, mask layer 350 is blocked on the epitaxial loayer 310 between adjacent two gate dielectric layers 320, due to stopping of mask layer 350, the ion that epitaxial loayer 310 under mask layer 350 adulterates is little, in propelling technical process, the ion that injects epitaxial loayer 310 spreads, and the result after actual dispersion is exactly to form the upwards tagma 360 of indent, centre position.
In existing trench FET, in the time forming tagma, do not have mask layer to block on epitaxial loayer, therefore it is after advancing technique, tagma profile is the shape protruded downwards in centre position (can with reference to figure 2) conventionally, just in time contrary with the shape (upwards caving in centre position) in the present embodiment tagma 360.In existing trench FET, tagma profile is conventionally centre position and protrudes downwards, and its minimum-depth is conventionally more than 0.5 μ m, and therefore its tagma resistance is larger.Upwards cave in 360 centre positions, tagma that the present embodiment forms, therefore the minimum-depth in tagma 360 appears at 360 centre positions, tagma.
In the present embodiment, the scope of the minimum-depth in tagma 360 is 0.2 μ m～0.4 μ m.Have according to resistance formula: R=ρ L/S, wherein L is the minimum-depth in tagma 360.Tagma resistance is directly proportional to the minimum-depth in tagma 360, and in the present embodiment, the scope of tagma 360 minimum-depths is 0.2 μ m～0.4 μ m, and therefore, tagma resistance can be reduced to the minimum-depth in the original tagma 360 of 0.4 original～0.8(more than 0.5 μ m).
Known according to above analysis, in the present embodiment, tagma resistance can be reduced to original 0.4～0.8.For trench FET, that its conducting voltage equals tagma resistance and plug resistance and be multiplied by electric current, that is: the formula of conducting voltage (Vbe): Vbe=I (Rb+Rct).Plug resistance (Rct), it is conventionally much smaller than tagma resistance (Rb), therefore, can think that conducting voltage is directly proportional to tagma resistance (Rb), in the present embodiment, because tagma resistance (Rb) can be reduced to original 0.4～0.8, therefore, conducting voltage also can be reduced to approximately 0.4～0.8, thereby ensures that conducting voltage is reduced to below 0.7V, improves the tolerance performance of trench FET.And, in whole process, do not need to increase the doping content in tagma 360, therefore, can prevent the problems such as the rising of trench FET threshold of appearance threshold voltage and drain-source breakdown voltage reduction.
Please refer to Figure 10, carry out heavy doping formation source region 370 to being positioned at the epitaxial loayer 310 of 360 tops, tagma, in the present embodiment, source region 370 upper surfaces and grid 330 upper surfaces and gate dielectric layer 320 upper surface flush.
In the present embodiment, if tagma 360 is N-type doping, source region 370 is the heavy doping of P type, if tagma 360 is the doping of P type, source region 370 is N-type heavy doping.
Please refer to Figure 11, on insulating protective layer 340, form interlayer dielectric layer 380.
In the present embodiment, the material that the material of interlayer dielectric layer 380 can insulating protective layer 340 is identical, and the material of interlayer dielectric layer 380 is also silica, and can adopt equally chemical gaseous phase depositing process to form interlayer dielectric layer 380.
Please refer to Figure 12; etching interlayer dielectric layer 380, insulating protective layer 340 and source region 370 are until form through hole 371; through hole 371 is between two gate dielectric layers 320; and source region 370 is divided into remaining two parts by through hole 371, two parts source region 370 belongs to respectively two different trench FETs.
In the present embodiment, the mask that formation through hole 371 adopts and the mask of above-mentioned formation mask layer 350 are same mask.As mentioned above, two processing steps adopt same mask can save the usage quantity of mask, cost-saving.
Please refer to Figure 13, filling vias 371 forms conductive plunger 390.
In the present embodiment, the material of conductive plunger 390 can be aluminium, copper or tungsten, in the time adopting copper, can adopt copper plating process to form conductive plunger 390.
It should be noted that, the present embodiment is follow-up can also carry out attenuate to the second surface of Semiconductor substrate 300, then on second surface, forms drain region (not shown).
In the formation method of the trench FET that the present embodiment provides, by form mask layer 350 on epitaxial loayer 310, and then the formation tagma 360 of adulterating, the degree of depth in the tagma 360 forming increases gradually from centre position to grid 330 directions, be that tagma 360 is less the closer to adjacent two grids, the 330 centre position degree of depth, therefore, tagma resistance reduces, the conducting voltage of trench FET decreases, thereby ensure that conducting voltage is reduced to below 0.7V, improve the tolerance performance of trench FET.And, in whole forming process, do not need to increase the doping content in tagma 360, therefore, can prevent the problems such as the rising of trench FET threshold of appearance threshold voltage and drain-source breakdown voltage reduction.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (12)

1. a trench FET, comprising:
Semiconductor substrate;
Be positioned at the epitaxial loayer on described Semiconductor substrate first surface;
Be arranged in the multiple discrete grid of described epitaxial loayer;
Be positioned at described epitaxial loayer and be positioned at the gate dielectric layer of described grid periphery, described gate dielectric layer upper surface, described gate upper surface and described epitaxial loayer upper surface flush;
Tagma in described epitaxial loayer and between adjacent two grids, described tagma and described grid are isolated by described gate dielectric layer;
It is characterized in that,
The degree of depth in described tagma increases gradually from centre position to grid direction.
2. trench FET as claimed in claim 1, is characterized in that, the minimum-depth in described tagma is 0.2 μ m～0.4 μ m.
3. trench FET as claimed in claim 1, is characterized in that, also comprises: be arranged in the source region in described tagma, described source region upper surface and described epitaxial loayer upper surface flush.
4. trench FET as claimed in claim 1, is characterized in that, described Semiconductor substrate has the second surface relative with described first surface, on described second surface, has drain region.
5. a formation method for trench FET, is characterized in that, comprising:
Semiconductor substrate is provided;
On the first surface of described Semiconductor substrate, form epitaxial loayer;
In described epitaxial loayer, form multiple discrete grooves;
Form gate dielectric layer at described grooved inner surface;
On described gate dielectric layer, form grid, common full described groove, described gate dielectric layer upper surface, described gate upper surface and the described epitaxial loayer upper surface flush of filling of described gate dielectric layer and described grid;
On described epitaxial loayer, form mask layer, the width of described mask layer is less than the distance between adjacent two described gate dielectric layers, and described mask layer equates to the distance between adjacent two described gate dielectric layers;
Taking described mask layer as mask, the described epitaxial loayer between adjacent two described gate dielectric layers to be adulterated and forms tagma, the degree of depth in described tagma increases gradually from centre position to grid direction.
6. the formation method of trench FET as claimed in claim 5, is characterized in that, the minimum-depth in described tagma is 0.2 μ m～0.4 μ m.
7. the formation method of trench FET as claimed in claim 5, it is characterized in that, the width range of described mask layer is 0.3 times～0.5 times of distance between adjacent two described gate dielectric layers, and the thickness range of described mask layer is 0.5 μ m～1.5 μ m.
8. the formation method of trench FET as claimed in claim 5; it is characterized in that; after forming described grid; and before forming described mask layer; described formation method also comprises: on described grid, described gate dielectric layer and described epitaxial loayer, form insulating protective layer, described mask layer is formed on described insulating protective layer surface.
9. the formation method of trench FET as claimed in claim 8, is characterized in that, after forming described tagma, described formation method also comprises: carry out heavy doping formation source region to being positioned at the described epitaxial loayer of top, described tagma.
10. the formation method of trench FET as claimed in claim 9, is characterized in that, after forming described source region, described formation method also comprises:
On described insulating protective layer, form interlayer dielectric layer;
Interlayer dielectric layer, insulating protective layer and source region described in etching are until form through hole, and described through hole, between adjacent two described gate dielectric layers, and is separated into two parts by described source region;
Fill described through hole and form conductive plunger.
The formation method of 11. trench FETs as claimed in claim 5, is characterized in that, the material of described mask layer is negative photoresist.
The formation method of 12. trench FETs as claimed in claim 5, is characterized in that, in the process in the described tagma of formation of adulterating, when N-type doping is carried out in described tagma, the ion of doping is boron ion, and the ion concentration scope of doping is 1E12/cm 3～1E13/cm 3, the energy range of employing is 40KeV～80KeV; When the doping of P type is carried out in described tagma, the ion of doping is phosphonium ion, and the ion concentration scope of doping is 1E13/cm 3～1E14/cm 3, the energy range of employing is 100KeV～160KeV.
CN201410081140.6A 2014-03-06 2014-03-06 Groove field effect transistor and forming method thereof Pending CN103871900A (en)

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CN106602215A (en) * 2016-12-20 2017-04-26 西安科锐盛创新科技有限公司 Method for preparing SiGe-based plasma pin diode for reconstructing holographic antennas
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CN106816684A (en) * 2016-12-20 2017-06-09 西安科锐盛创新科技有限公司 For the Ge base plasma pin diode preparation methods of restructural multilayer holographic antenna
CN106816683A (en) * 2016-12-20 2017-06-09 西安科锐盛创新科技有限公司 For the manufacture method of the SPIN diodes of U wave band restructural loop aerial
CN106876871A (en) * 2016-12-20 2017-06-20 西安科锐盛创新科技有限公司 The preparation method of SiGe fundamental frequency restructural sleeve-dipole antennas
CN109065603A (en) * 2018-08-02 2018-12-21 深圳市福来过科技有限公司 A kind of transistor and preparation method thereof

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Publication number Priority date Publication date Assignee Title
CN106602214A (en) * 2016-12-20 2017-04-26 西安科锐盛创新科技有限公司 Preparation method for frequency reconfigurable holographic antenna based on GaAs/Ge/GaAs heterostructure
CN106602215A (en) * 2016-12-20 2017-04-26 西安科锐盛创新科技有限公司 Method for preparing SiGe-based plasma pin diode for reconstructing holographic antennas
CN106602216A (en) * 2016-12-20 2017-04-26 西安科锐盛创新科技有限公司 A preparation method of reconstructing a holographic antenna on the basis of SiGe base heterojunction frequency
CN106654520A (en) * 2016-12-20 2017-05-10 西安科锐盛创新科技有限公司 Manufacturing method of solid-state plasma diode for preparing holographic antenna
CN106654521A (en) * 2016-12-20 2017-05-10 西安科锐盛创新科技有限公司 Preparation method of heterogeneous Ge-based SPiN diode strings for reconfigurable dipole antenna
CN106785334A (en) * 2016-12-20 2017-05-31 西安科锐盛创新科技有限公司 With SiO2Pin diodes of protective effect and preparation method thereof
CN106816686A (en) * 2016-12-20 2017-06-09 西安科锐盛创新科技有限公司 The preparation method of the restructural dipole antenna based on heterogeneous SiGeSPiN diodes
CN106816684A (en) * 2016-12-20 2017-06-09 西安科锐盛创新科技有限公司 For the Ge base plasma pin diode preparation methods of restructural multilayer holographic antenna
CN106816683A (en) * 2016-12-20 2017-06-09 西安科锐盛创新科技有限公司 For the manufacture method of the SPIN diodes of U wave band restructural loop aerial
CN106876871A (en) * 2016-12-20 2017-06-20 西安科锐盛创新科技有限公司 The preparation method of SiGe fundamental frequency restructural sleeve-dipole antennas
CN109065603A (en) * 2018-08-02 2018-12-21 深圳市福来过科技有限公司 A kind of transistor and preparation method thereof

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Application publication date: 20140618