CN104979400A - 使用硅化物源极和本体接触区的封闭式晶胞横向mosfet - Google Patents

使用硅化物源极和本体接触区的封闭式晶胞横向mosfet Download PDF

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Publication number
CN104979400A
CN104979400A CN201510126045.8A CN201510126045A CN104979400A CN 104979400 A CN104979400 A CN 104979400A CN 201510126045 A CN201510126045 A CN 201510126045A CN 104979400 A CN104979400 A CN 104979400A
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structure cell
source
source electrode
electrode structure
joint
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雪克·玛力卡勒强斯瓦密
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种封闭式晶胞横向MOSFET器件包括尺寸最小的源极/本体接头，形成在一个或多个源极晶胞中，硅化物源极和本体接触区形成在其中。在这种情况下，晶胞式晶体管的晶胞间距始终很小，同时确保晶体管的强度。在其他实施例中，利用硅化物源极和本体接触区，制备封闭式晶胞横向MOSFET器件，自对准接头和无边界接头作为源极/本体接头。可以利用最小的多晶硅-多晶硅间距，制备多晶硅栅极网孔，使晶胞式晶体管阵列的晶胞间距最小。

Description

使用硅化物源极和本体接触区的封闭式晶胞横向MOSFET
技术领域
本发明涉及半导体器件，更确切地说，是提供使用硅化物源极和本体接触区的封闭式晶胞横向金属氧化物半导体场效应晶体管及其制备方法。
背景技术
将功率金属氧化硅场效应晶体管(MOSFET)配置在需要高电压和高电流的应用中。封闭式晶胞或晶胞式阵列结构，因其电流密度很高，即半导体单位面积上通道宽度很宽，减小了导通电阻，因此常常成为制备横向功率MOSFET器件的首选。人们非常需要低导通电阻MOSFET器件的低功率损耗以及传导高电流的能力。
图1来自美国专利号7956384中的图1B，表示利用配有多晶硅栅极(G)网孔的晶胞式晶体管阵列，制备横向MOSFET器件的一个示例。在美国专利号5355008中也提出了晶胞式晶体管阵列结构。如图1所示，通过拉长多晶硅线条的网孔，交替形成通过金属带(M1)并联的源极(S)和漏极(D)晶胞，正方形晶胞阵列增大了单位面积上的通道宽度(W/面积)。另外，通过在多晶硅网孔中形成菱形(即具有长轴和相对于长轴而显得较短的短轴)的开口，在短轴方向上的源极和漏极金属带可以做得更宽，从而降低了晶体管的导通电阻，而不会增加晶体管的面积。
在NMOS横向MOSFET器件中，晶体管通常包括一个P-阱区以及重掺杂N+区，其中P-阱形成在衬底中，作为晶体管的本体，重掺杂N+区形成在P-阱中，作为源极和漏极区。NMOS晶体管的本体通常短接至晶体管的源极。为了确保横向MOSFET器件的强度，需要在晶体管的源极和本体之间进行强电连接。
包括图2(a)和图2(b)，表示一种传统的封闭式晶胞MOSFET器件的剖面图。参见图2(a)，利用多晶硅栅极网孔12限定形成在阱中的扩散区的晶胞式阵列，制成封闭式晶胞MOSFET器件10。在本示例中，MOSFET器件10为NMOS晶体管，N+扩散区形成在P-阱中，扩散区的交替行构成晶体管的源极和漏极区。例如，N+扩散区14构成晶体管的源极区(也称为“源极晶胞”)，而N+扩散区16构成晶体管的漏极区(也称为“漏极晶胞”)。在本示例中，本体到源极的连接由P+本体扩散区18提供，P+本体扩散区18形成在某些或全部源极晶胞内，作为本体接触区。对接接头20用于电连接到N+源极区和P+本体扩散区。图2(b)为沿着图2(a)中线A-A’的晶胞阵列的剖面图。参见图2(b)，由于对接接头20需要覆盖源极晶胞中的N+源极扩散区14和P+本体扩散区18，因此接头20的尺寸很大。对接接头20的尺寸大于用于连接到漏极扩散区16的尺寸最小的接头17。用于构成源极晶胞内的源极/本体接触所使用的对接接头20，增大了晶胞式晶体管的晶胞间距，这会引起晶体管的导通电阻值不必要的增加。
当不需要增加晶胞间距时，可以利用最小的尺寸，来制备源极和漏极晶胞，其中本体接头形成在晶体管器件周围的晶胞式晶体管阵列之外。在这种情况下，可以利用最小的接头—多晶硅间距以及最小的金属—金属间距，制备晶胞式晶体管阵列。然而，只在晶胞式晶体管周围接触晶体管的本体，会降低晶体管器件的强度，尤其是当晶体管的漏极和源极端上加载快速电压瞬变时。其主要原因在于，该NMOS横向晶体管的本体构成了寄生双极晶体管的基极，在发生快速瞬变时可以接通该基极，以进行热耗散，从而避免对晶体管器件造成永久性损坏。
发明内容
在本发明提供的一种封闭式晶胞横向MOS晶体管中，主要包括：一个第一导电类型轻掺杂的半导体层，半导体层构成晶体管的本体；一个导电栅极在半导体层的顶面上方，并通过栅极电介质层与半导体层的顶面绝缘，导电栅极构成具有多个开口的网孔，多个开口限定源极晶胞和漏极晶胞的晶胞式阵列；多个与第一导电类型相反的第二导电类型的扩散区，形成在被网孔中的开口裸露出来的半导体层中，多个扩散区构成源极晶胞和漏极晶胞的晶胞式阵列，其中扩散区的交替行构成晶体管的源极区和漏极区，源极区和漏极区之间的导电栅极下方的半导体层构成晶体管的通道；一个第一导电类型的本体接触区，形成在源极和漏极晶胞的晶胞式阵列中的一个或多个源极晶胞中，本体接触区的重掺杂程度比半导体层更大，本体接触区被一个或多个源极晶胞中的源极区包围；一个金属硅化物层，形成在多个扩散区的顶面上，金属硅化物层形成在一个或多个源极晶胞中，以便电连接形成在一个或多个源极晶胞中的源极区和本体接触区；以及一个源极/本体接头，形成在一个或多个源极晶胞中，并且与金属硅化物层接触，源极/本体接头通过金属硅化物层，电连接到一个或多个源极晶胞中的源极区和本体接触区。
上述的封闭式晶胞横向MOS晶体管，半导体层包括一个第一导电类型的阱区，形成在半导体衬底上，该阱区构成晶体管的本体。
上述的封闭式晶胞横向MOS晶体管，半导体层包括一个第一导电类型的阱区，形成在半导体衬底上的外延层中，阱区构成晶体管的本体。
上述封闭式晶胞横向MOS晶体管，本体接触区位于被源极区包围的源极晶胞中心。上述封闭式晶胞横向MOS晶体管，本体接触区和源极区作为重叠的扩散区。上述封闭式晶胞横向MOS管，源极/本体接头位于源极晶胞中的本体接触区上方。上述封闭式晶胞横向MOS晶体管，其中源极/本体接头的尺寸小于源极晶胞中的本体接触区尺寸。
上述封闭式晶胞横向MOS晶体管，一个或多个源极晶胞中的源极/本体接头包括一个接头，接头具有最小尺寸，到导电栅极的间距最小，导电栅极包围着各自的源极晶胞。
上述的封闭式晶胞横向MOS晶体管，导电栅极构成一个网孔，网孔中具有多个尺寸基本一致的开口。
上述的封闭式晶胞横向MOS晶体管，由网孔形成的多个开口，包括具有第一外围长度的多个第一开口，用于制备源极晶胞，以及具有第二外围长度的多个第二开口，用于制备漏极晶胞，第一外围长度大于第二外围长度。
上述的封闭式晶胞横向MOS晶体管，在一个或多个源极晶胞中的源极/本体接头包括一个自对准接头，其中接头的至少一部分自对准到各自源极晶胞的外围或周边。
上述的封闭式晶胞横向MOS晶体管，在一个或多个源极晶胞中的源极/本体接头包括一个自对准条形接头，其中接头的至少两个拐角自对准到各自源极晶胞的外围或周边。
上述的封闭式晶胞横向MOS晶体管，在一个或多个源极晶胞中的源极/本体接头包括一个具有交叉形状的自对准条形接头，其中交叉形接头的至少四个末端自对准到各自源极晶胞的外围或周边。
上述的封闭式晶胞横向MOS晶体管，在一个或多个源极晶胞中的源极/本体接头都包括一个金属钨材质插头。
上述的封闭式晶胞横向MOS晶体管，第一导电类型为P导电类型以及第二导电类型为N导电类型。
在本方面提供的一种用于制备封闭式晶胞横向MOS晶体管的方法中，主要包括以下步骤：制备一个第一导电类型轻掺杂的半导体层，半导体层构成晶体管的本体；制备一个导电栅极在半导体层的顶面上方，并通过栅极电介质层与半导体层的顶面绝缘，导电栅极构成具有多个开口的网孔，多个开口限定源极晶胞和漏极晶胞的晶胞式阵列；制备多个与第一导电类型相反的第二导电类型的扩散区，形成在被网孔中的开口裸露出来的半导体层中，多个扩散区构成源极晶胞和漏极晶胞的晶胞式阵列，其中扩散区的交替行构成晶体管的源极区和漏极区，源极区和漏极区之间的导电栅极下方的半导体层构成晶体管的通道；制备一个第一导电类型的本体接触区，形成在源极和漏极晶胞的晶胞式阵列中的一个或多个源极晶胞中，本体接触区的重掺杂程度比半导体层更大，本体接触区被一个或多个源极晶胞中的源极区包围；制备一个金属硅化物层，形成在多个扩散区的顶面上，金属硅化物层形成在一个或多个源极晶胞中，以便电连接形成在一个或多个源极晶胞中的源极区和本体接触区；并且制备一个源极/本体接头，形成在一个或多个源极晶胞中，并且与金属硅化物层接触，源极/本体接头通过金属硅化物层，电连接到一个或多个源极晶胞中的源极区和本体接触区。
上述方法，制备第一导电类型的半导体层的步骤包括：制备第一个第一导电类型的阱区，形成在半导体衬底上，阱构成晶体管的本体。
上述方法，在一个或多个源极晶胞中制备一个第一导电类型的本体接触区的步骤，包括：在被源极区包围的源极晶胞中制备本体接触区。
上述方法，在一个或多个源极晶胞中制备一个第一导电类型的本体接触区的步骤，包括：制备本体接触区和源极区，作为重叠的扩散区。
上述方法，制备源极/本体接头的步骤，包括：制备一个源极/本体接头，其尺寸小于源极晶胞中本体接触区的尺寸。
上述方法，制备源极/本体接头包括的步骤：制备一个源极/本体接头，其开口具有最小尺寸，并且到各自源极晶胞周围的导电栅极的间距最小。
附图说明
以下的详细说明及附图提出了本发明的各个实施例。
图1是美国专利号7956384中的原始图1B，表示利用配有多晶硅栅极网孔的晶胞式晶体管阵列，制备横向MOSFET器件的一个示例。
图2(a)至图2(b)表示传统的封闭式晶胞MOSFET器件的俯视图和剖面图。
图3(a)至图3(d)表示在本发明的实施例中，含有源极晶胞引入硅化物源极/本体接触区的封闭式晶胞横向MOSFET器件的俯视图和剖面图。
图4表示在本发明的可选实施例中，含有源极晶胞引入硅化物源极/本体接触区的封闭式晶胞横向MOSFET器件的俯视图和剖面图。
图5(a)至图5(b)表示在本发明的可选实施例中，利用重叠源极/本体接触区的封闭式晶胞横向MOSFET器件的俯视图和剖面图。
图6(a)至图6(c)表示在本发明的可选实施例中，利用自对准接头的封闭式晶胞横向MOSFET器件的俯视图和剖面图。
图7表示在本发明的可选实施例中，含有源极晶胞引入自对准接头的封闭式晶胞横向MOSFET器件的俯视图。
图8表示在本发明的可选实施例中，含有源极晶胞引入自对准接头的封闭式晶胞横向MOSFET器件的俯视图。
具体实施方式
本发明可以以各种方式实现，包括作为一个工艺；一种装置；一个系统；和/或一种物质合成物。在本说明书中，这些实现方式或本发明可能采用的任意一种其他方式，都可以称为技术。一般来说，可以在本发明的范围内变换所述工艺步骤的顺序。
本发明的一个或多个实施例的详细说明以及附图解释了本发明的原理。虽然，本发明与这些实施例一起提出，但是本发明的范围并不局限于任何实施例。本发明的范围仅由权利要求书限定，本发明包含多种可选方案、修正以及等效方案。在以下说明中，所提出的各种具体细节用于全面理解本发明。这些细节用于解释说明，无需这些详细细节中的部分细节或全部细节，依据权利要求书，就可以实现本发明。为了条理清晰，本发明相关技术领域中众所周知的技术材料并没有详细说明，以免对本发明产生不必要的混淆。
在本发明的实施例中，一种封闭式晶胞横向金属-氧化硅场效应晶体管(MOSFET)器件包括形成在一个或多个源极晶胞中尺寸最小的源极/本体接头，硅化物源极和本体扩散区形成在源极晶胞中。在这种情况下，晶胞式晶体管阵列的晶胞间距(cell pitch)一直很小，同时确保了晶体管的强度。由于金属硅化层在源极晶胞中的源极和本体接触区之间提供电接触，因此利用源极晶胞中的硅化物扩散区，尺寸最小的源极/本体接头可以在源极晶胞内的任意位置，以便与源极和本体接触区电接触。在一些实施例中，尺寸最小的源极/本体接头位于硅化物本体接触区的边界内，金属硅化层提供到源极区的电接触。
在本发明的其他实施例中，利用硅化物源极和本体扩散区，以及自对准接头或无边界接头作为源极/本体接头，制备封闭式晶胞横向MOSFET器件。利用最小的多晶硅-多晶硅间距，可以制成多晶硅栅极网孔，使晶胞式晶体管阵列的晶胞间距最小。本申请提及的晶体管的晶胞可以被单元等用语替代。
在本申请的说明书中，“硅化物扩散区”或“硅化物区”是指在半导体器件的扩散区的裸露顶面上，形成一个导电的金属硅化层。在本说明中，“扩散区”是指半导体器件中的重掺杂区，通常利用掺杂物的离子注入，然后热退火使掺杂物扩散和激活制成。在本说明中，“源极扩散区”也称为“源极区”，“漏极扩散区”也称为“漏极区”，以及“本体扩散区”也称为“本体接触区”。在本申请的说明书中，MOSFET器件有时也称为MOS晶体管、晶体管器件或晶体管。
在某些硅化物工艺中，金属硅化层只形成在接触开口的底部，用于制备金属硅化物接头。然而，在本发明的实施例中，金属硅化层形成在源极和本体扩散区的裸露顶面上，形成一个导电层，将源极和本体扩散区电连接起来，源极和本体扩散区相互邻近，形成在封闭式晶胞MOSFET器件的源极晶胞中。源极和本体扩散物通过金属硅化层短接起来，利用尺寸最小的接触开口，在源极/本体扩散区和上方的互连结构之间，形成电连接。之所以可以使用尺寸最小的源极/本体接头，是因为源极/本体接头无需覆盖源极晶胞中的源极扩散区和本体扩散区。事实上，可以制备尺寸最小的源极/本体接头，仅仅覆盖本体扩散区，而不覆盖源极扩散区的任意部分，同时金属硅化层在源极扩散区和本体扩散区之间提供必要的电连接。
在本申请的说明书提及的各个实施例中，通过硅化物工艺配置高导电性的耐火金属，在硅化物源极/本体扩散区上方，形成金属硅化层。在硅化物工艺中配置的耐火金属通常包括铂(Pt)、钛(Ti)、镍(Ni)和钴(Co)，每种金属都可以与硅(Si)一起形成很低电阻率相位，例如PtSi2、TiSi2、NiSi和CoSi2。在硅化物工艺中，耐火金属沉积在有源区上，以便与硅形成金属间化合物，但不会在进行硅化物工艺时与二氧化硅、氮化硅或其他电介质反应。热退火后，耐火金属层与下面的硅反应，形成金属硅化层。除去未反应的那部分耐火金属层。
在一些实施例中，利用自对准的硅化物工艺(称为“自对准多晶硅化物”工艺)，制备硅化物源极和本体扩散物。利用自对准硅化物工艺制成的金属硅化层，有时也称为“自对准多晶硅化物”层。在自对准多晶硅化物工艺中，耐火金属层可以沉积在半导体器件的整个表面上方，包括多晶硅层和有源区的裸露表面上方。热退火并除去未反应的耐火金属部分后，在多晶硅层上形成一个金属硅化物层，以制备硅化物多晶硅栅极，在有源区上形成一个金属硅化物层，以制备硅化物扩散区。
在本说明书中，“尺寸最小的接头”或“尺寸最小的接触开口”是指利用物理布局设计规则(physical layout design rules)规定/允许的尺寸最小的参数，制备接头或接触开口，物理布局设计规则是用于横向MOSFET器件制备工艺的。例如，接头的设计规则包括最小的接头尺寸，以及从接头到多晶硅之间的最小间距。在一些实施例中，“尺寸最小的接头”或“尺寸最小的接触开口”是指利用设计规则确定的最小接头尺寸和接头到多晶硅的最小间距，制备的接头或开口。然而，虽然本发明所述的横向MOSFET器件使用的是尺寸最小的接头或开口，但是也可以利用尺寸并非绝对最小的接头，制备本发明所述的横向MOSFET器件。根据具体应用，晶胞式晶体管阵列中也可以接受较大的晶胞间距，利用设计规则确定的并非最小尺寸的接头尺寸，也可以制备横向MOSFET器件。在以下说明中，使用最小尺寸的接头仅用于解释说明，不用于局限。
另外，在一些用于到扩散区接头的设计规则中，可能包括接触开口最小的扩散区叠加。最小的扩散区叠加设计规则，用于确保扩散区上方的接触开口形成在扩散区的边界内。然而，利用本发明所述的横向MOSFET器件中的硅化物源极/本体扩散区，由于源极/本体接头并不是直接形成在扩散区上方，而是形成在金属硅化物层上方，因此制备源极/本体接头时可以不考虑最小的扩散区叠加设计规则。
图3(a)至图3(d)，表示在本发明的实施例中，含有源极晶胞引入硅化物源极/本体接触区的封闭式晶胞横向MOSFET器件的俯视图和剖面图。确切地说，图3(a)表示横向MOSFET器件的一部分晶胞式晶体管阵列，图3(b)表示沿着图3(a)中虚线B-B’的那部分晶胞式晶体管阵列的剖面图，图3(c)表示晶胞式晶体管阵列中一个源极晶胞的延伸俯视图，图3(d)表示源极晶胞的延伸剖面图。参见图3(a)至图3(d)，利用多晶硅栅极网孔52限定形成在半导体层中的扩散区的晶胞式阵列，制成封闭式晶胞横向MOSFET器件50(或“晶体管50”)。半导体层包括一个或多个阱区，作为晶体管的本体。扩散区和本体接触区具有相反的导电类型。多晶硅栅极网孔52限定正方形晶胞或菱形晶胞。在本实施例中，横向MOSFET器件50为NMOS晶体管，其中N+源极/漏极区54、56形成在P-阱64中，P-阱(P-WELL)64作为晶体管的本体。P-阱64与N+源极区54/漏极区56的掺杂浓度相比，为轻掺杂。
在一些实施例中，半导体层包括一个半导体衬底(substrate)62和一个形成在衬底62上的外延层。在一些实施例中，P-阱64形成在衬底62中，或者在衬底62上的外延层中。在其他实施例中，晶体管的本体形成在半导体层中，用导电类型与源极/漏极扩散区相反的掺杂物轻掺杂半导体层。将阱区用作晶体管的本体是可选的。半导体层的具体结构对于实施本发明来说并不重要。
在晶胞式晶体管阵列中，扩散区的交替行形成晶体管的源极区和漏极区，譬如：多行的第一类扩散区与多行的第二类扩散区以交替(alternating rows)的方式设置，第一类、第二类扩散区对应分别形成晶体管的源极区和漏极区。更确切地说，N+扩散区54构成晶体管50的源极区(也称为“源极晶胞”)，而N+扩散区56构成晶体管50的漏极区(也称为“漏极晶胞”)。为了在晶体管的源极和本体之间形成电连接，要在部分或全部源极晶胞中形成一个P+本体扩散区58。用导电类型与晶体管的本体相同的掺杂物重掺杂P+本体扩散区58，以便提供到晶体管本体的欧姆接触。在本实施例中，晶体管的本体为P-阱64，重掺杂P+本体扩散区58用于提供到P-阱64的欧姆接触。在晶胞式晶体管阵列中，P+本体扩散区58通常形成在被源极扩散区54包围的源极晶胞中心处，具体而言例如P+本体扩散区58形成在源极晶胞中心处并被源极扩散区54所包围。源极扩散区54紧挨着带有多晶硅栅极网孔52的栅极下方的通道或沟道。
在本发明的实施例中，金属硅化物层68形成在N+源极扩散区54和P+本体扩散区58的裸露硅表面上，有效短接N+源极扩散区54和P+本体扩散区58。在本示例中，使用的是自对准多晶硅化物工艺，而且在N+漏极扩散区56的裸露硅表面上和在带有多晶硅栅极网孔52结构的多晶硅层的裸露顶面上，形成一个金属硅化物层。在自对准多晶硅化物工艺中，沿多晶硅栅极结构的侧壁形成垫片，防止形成在带有多晶硅栅极网孔52的多晶硅层上的金属硅化物层69电短接至有源区(扩散区54、56)上的金属硅化物层68、66。因此，金属硅化物层68形成在源极和本体扩散区54、58上方，金属硅化物层66形成在漏极扩散区56上方，金属硅化物层69形成在带有多晶硅栅极网孔52结构的多晶硅层上方。注意，为了简化示意图，在图3(a)的俯视图中省去了金属硅化物层。要理解的是，金属硅化物层覆盖了源极晶胞内的源极和本体扩散区，另一个金属硅化物层覆盖了漏极晶胞中的漏极扩散区，还有一个金属硅化物层形成在多晶硅栅极网孔上方。
通过形成在金属硅化物层68，源极区54和本体接触区58电性短接。利用小于源极扩散区54和本体扩散区58的接触开口，可以形成源极/本体电连接到互连结构上方。尤其是当需要很小的晶胞间距时，可以利用尺寸最小的接头，形成源极/本体接头。另外，为了对称，可以在源极晶胞的中心形成源极/本体接头，以便利用接头所有边缘上接头至多晶硅的最小间距。在本发明的一些实施例中，源极/本体接头60形成在P+本体扩散区58上方，并且电连接到金属硅化物层68，如图3(c)所示。在一个实施例中，源极/本体接头60形成在尺寸为d1的开口中，d1约等于或小于P+本体扩散区58的尺寸d2。因此，即使源极/本体接头60没有覆盖N+源极扩散区54，但是可以通过金属硅化物层68实现到源极扩散区54的电性连接。
在本发明的实施例中，硅化物层68形成在源极晶胞整个裸露的硅表面上，源极晶胞在沿着带有多晶硅栅极网孔52的多晶硅栅极的侧壁上形成的邻近的垫片75a、75b之间具有用于形成该硅化物层68的裸露硅表面(图3(d))。源极/本体接头60形成在尺寸为d1的开口中，d1小于相互邻近的垫片75a、75b之间的尺寸d3。另外，接触开口的侧壁与垫片75a、75b间隔开。
在本实施例中，横向MOSFET器件50使用接触插头结构，作为互连结构，将扩散区连接到金属层上方。形成金属硅化物之后，在半导体结构上方形成一个绝缘电介质层70。接触开口形成在电介质层70中，使P+本体扩散区58上方的金属硅化物层68从一部分接触开口中裸露出来，也使N+漏极区56上方的金属硅化物层66从另一部分接触开口中裸露出来。然后用钨等金属层填充接触开口。形成在金属硅化物层68上方的源极晶胞中的钨插头，成为源极/本体接头60。形成在金属硅化物层66上方的漏极晶胞中的钨插头，成为漏极接头61。利用形成的接触插头结构，可以在接触插头上方形成一个金属层，连接漏极晶胞和源极晶胞。例如，在绝缘电介质层70上方沉积一个金属层并实施图案化后形成图案，构成接触源极/本体接头60的第一金属线72连接到源极晶胞，构成接触漏极接头61的第二金属线74而连接到漏极晶胞。
在上述实施例中，源极/本体接头60形成在源极晶胞中心，源极晶胞使用接头至多晶硅最小的间距，制备具有最小晶胞间距的晶胞阵列。在其他实施例中，源极/本体接头60可以位于源极晶胞中的任意位置，不必位于源极晶胞的中心。例如，在一些应用中，晶胞间距可以适当放宽，源极晶胞具有较大的面积，使源极/本体接头形成在源极晶胞中，同时接头至多晶硅的最小间距只在接头的某些部分才能满足，而接头的其他部分大于接头至多晶硅的最小间距。
在上述实施例中，提出了一种NMOS封闭式晶胞横向MOSFET器件。在其他实施例中，利用上述硅化物源极/本体扩散区和尺寸最小的源极/本体接头，可以制备PMOS封闭式晶胞横向MOSFET器件。在那种情况下，源极和漏极扩散区为P+扩散区，而本体扩散区为N+漏极区。
图4表示在本发明的可选实施例中，含有源极晶胞引入硅化物源极/本体接触区的封闭式晶胞横向MOSFET器件的俯视图。参见图4，利用多晶硅栅极网孔82限定阱中源极扩散区84和漏极扩散区86的交替行的晶胞式阵列。本体扩散区88形成在一个或多个源极晶胞中，确切地说，是形成在源极晶胞的中心处。金属硅化物层(图中没有表示出)形成在源极晶胞中，以便电连接源极和本体扩散区。在其他实施例中，金属硅化物层(图中没有表示出)也形成在漏极晶胞中和多晶硅栅极上方。尺寸最小的接头形成在源极晶胞和漏极晶胞中，所形成在接头作为接触接头，例如钨接触接头。例如，漏极接头91形成在漏极晶胞中，源极/本体接头90形成在源极晶胞中。重要的是，利用最小的接头尺寸以及最小的接头至多晶硅间距，可以形成源极/本体接头90。在本示例中，源极/本体接头90形成在本体扩散区88的边界内。金属线97形成在半导体结构上方，以便连接到漏极接头91，金属线98形成在半导体结构上方，以便连接到源极/本体接头90。
由于晶胞式晶体管阵列增加了有效栅极宽度和晶体管的源极/漏极面积，因此封闭式晶胞横向MOSFET器件80是功率MOSFET器件的较佳结构。在封闭式晶胞横向MOSFET器件80中，通过增加源极晶胞的外围长度(periphery length)，可以在源极边缘进一步延伸晶体管的通道宽度。为了保持正方形晶胞的对称性，并且保持通道长度(源极和漏极区之间)，要缩短漏极晶胞的外围长度，如图4所示。在这种情况下，源极处的通道宽度较宽，而通道长度保持一致。增加横向MOSFET晶体管80的源极边缘处的通道宽度，导致晶体管的载流容量增大。
在图4的一个非限制性的实施例中具有以下布局特点：在带有源极扩散区84的源极晶胞阵列(假定它由第一套网孔的开口限定位置)中和在带有漏极扩散区86的漏极晶胞阵列(假定它由第二套网孔的开口限定位置)中，行源极晶胞和行漏极晶胞交替出现，也即任意一行源极晶胞和与之相邻的另一行源极晶胞之间设置有一行漏极晶胞，且列源极晶胞和列漏极晶胞交替出现，也即任意一列源极晶胞和与之相邻的另一列源极晶胞之间设置有一列漏极晶胞。同一行中所有源极晶胞(或漏极晶胞)的一组横向设置的对角位于同一条直线上，同一列中所有源极晶胞(或漏极晶胞)的一组纵向设置的对角位于同一条直线上。从整体上看，带有源极扩散区84的源极晶胞和带有漏极扩散区86的漏极晶胞相邻交叉分布，以及每个带有源极扩散区84的源极晶胞四周均为带有漏极扩散区86的漏极晶胞，反之亦然，每个漏极晶胞四周均为源极晶胞。显然，这里带有源极扩散区84的源极晶胞、带有漏极扩散区86的漏极晶胞两者的布局方式也对应表征了多晶硅栅极上第一套网孔、第二套网孔的布局方式。上文的金属线97、金属线98在一个可选实施例中设为沿其长度方向横向延伸。
包括图5(a)和图5(b)表示在本发明的可选实施例中，利用重叠的源极/本体接触区，封闭式晶胞横向MOSFET器件的俯视图和剖面图。确切地说，图5(a)表示晶胞式晶体管阵列中一个源极晶胞的扩展视图，图5(b)表示源极晶胞的剖面图。更确切地说，图5(a)和图5(b)表示用于在源极晶胞中制备源极扩散区和本体扩散区的一种可选方法和结构。因此图5(a)和图5(b)表示横向MOSFET器件的唯一源极晶胞。
参见图5(a)至图5(b)，利用多晶硅栅极网孔102限定阱中扩散区的晶胞式阵列，制备封闭式晶胞横向MOSFET器件100(或“晶体管100”)。在本实施例中，横向MOSFET器件100为NMOS晶体管，N+源极扩散区104形成在半导体衬底112上的P-阱114中。P+本体扩散区108形成在N+源极扩散区104包围的源极晶胞中。在晶胞式晶体管阵列中，扩散区的交替行构成晶体管的源极区和漏极区。为了简化起见和便于观察，在图5(b)中省去了漏极区。
在横向MOSFET器件100的源极晶胞中，N+源极扩散区104和P+本体扩散区108作为重叠的扩散区。在一个实施例中，利用覆盖在每个源极晶胞中的N+注入掩膜和P+注入掩膜，可以制备重叠的扩散区。例如，可以将P+注入掩膜拉到较宽的边界，以便与源极晶胞中的N+注入掩膜重叠。当完成P+和N+注入工艺时，可以用N+和P+掺杂物制备重叠区107。然而，由于N+掺杂物支配P+掺杂物，因此热退火后，重叠区107将转换成N-型区，使N+源极区104扩展到包含重叠区107，P+本体扩散区108变窄。
形成源极、漏极和本体扩散区之后，在N+源极扩散区104和P+本体扩散区108的裸露硅表面上，制备一个金属硅化物层118，有效的电性短接N+源极扩散区104和P+本体扩散区108区域。注意，为了简化，在图5(a)的俯视图中省去了金属硅化物层118。要理解的是，一个金属硅化物层覆盖了源极晶胞内的源极和本体扩散区，另一个金属硅化物层覆盖多晶硅栅极网孔。利用形成的金属硅化物层118，通过在源极晶胞中制备源极/本体接头110，将源极/本体电连接到互连结构上方。在本实施例中，源极/本体接头110在源极晶胞中心，位于P+本体扩散区108上方。源极/本体接头110电连接到金属硅化物层118，如图5(b)所示。利用重叠的源极和本体扩散区，能够进一步减小晶胞式晶体管阵列的晶胞间距。
在本发明的实施例中，硅化物层118形成在邻近的垫片120a、120b之间的源极晶胞中整个裸露的硅表面上，邻近的垫片120a、120b沿多晶硅栅极102的侧壁形成。源极/本体接头110形成在开口中，开口尺寸小于邻近的垫片120a、120b之间的距离。另外，接触开口的侧壁与垫片120a、120b间隔开。
在本实施例中，源极/本体接头110为接触插头(例如钨插头)形成在电介质层130中。金属线134形成在源极/本体接头110上方，构成源极/本体接触。
图6(a)至图6(c)表示在本发明的可选实施例中，使用自对准接头的封闭式晶胞横向MOSFET器件的俯视图和剖面图。图6(a)至图6(c)中的封闭式晶胞横向MOSFET器件150除了使用自对准接头(也称为“无边界接头”)之外，其他都与图5(a)至图5(b)所示的MOSFET器件100的制备方式相同。图5(a)至图5(b)和图6(a)至图6(c)中的类似元件都采用相似的参考数字，以简化论述。在图6(a)至图6(c)中，源极扩散区104和本体扩散区108与图5(a)至图5(b)所示的MOSFET器件100相同，作为重叠的扩散区。在另一个实施例中，源极扩散区和本体扩散区与图3(b)相同，作为邻近的扩散区。注意，为了简化，在图6(a)的俯视图中省去了金属硅化物层，但图6(b)至图6(c)展示了这些特征。
参见图6(a)至图6(c)，通过形成在源极晶胞中的源极和本体扩散区104、108上方的金属硅化物层118，可以利用自对准接触工艺，制备接触结构，以便将源极/本体接触区电连接到金属线。使用自对准的接头，使得利用尺寸最小的多晶硅间距，减小晶胞式晶体管阵列的晶胞间距成为可能。更确切地说，可以利用最小的多晶硅-多晶硅间距，制备多晶硅栅极电极102。垫片结构形成在多晶硅栅极102导电侧壁上。制备接触开口，覆盖垫片结构。金属层(例如钨)填充接触开口，形成自对准接头，例如源极/本体接头160。因此，源极/本体接头160基本覆盖了源极晶胞的整个区域，并通过垫片结构，与多晶硅栅极绝缘。
在本发明的实施例中，硅化物层118形成在源极晶胞中的整个裸露的硅表面上，源极晶胞在沿着带有多晶硅栅极网孔的多晶硅栅极102的侧壁上形成的邻近的垫片120a、120b之间具有用于形成该硅化物层118的裸露硅表面。源极/本体接头160形成在尺寸为d4的开口中，d4大于邻近垫片120a、120b之间的最小距离d5，但是小于邻近的栅极结构102之间的距离d6(参见图6(c))。另外，在某些实施例中，接头160的接触开口侧壁在低于垫片120a、120b高度的一半处，插入垫片。因此，邻近垫片120a、120b限定了源极/本体接头160的接触开口的底部。
使用自对准接头160时，形成在接头上方的金属线174的宽度W很宽。在一些情况下，金属-金属最小的间距防止使用宽金属线174。那样可以利用使上方金属线的宽度最小的图案，制备源极/本体接头。图7表示在本发明的可选实施例中，含有引入自对准接头的源极晶胞的封闭式晶胞横向MOSFET器件的俯视图。
参见图7，图7中的封闭式晶胞横向MOSFET器件200除了使用自对准接头之外，其他都与图3(a)至图3(d)所示的MOSFET器件50的制备方式相同。图3(a)至图3(d)和图7中的类似元件都采用相似的参考数字，以简化论述。在图7中，源极扩散区104和本体扩散区108像图3(b)那样，作为邻近的扩散区。在其他实施例中，源极扩散区和本体扩散区与图5A所示的MOSFET器件100相同，作为重叠的扩散区。金属硅化物层(图中没有表示出)形成在源极晶胞中，以便电短接源极和本体扩散区。
在封闭式晶胞横向MOSFET器件200中，源极/本体接头210和漏极接头211作为变窄的自对准条形接头。在变窄的自对准条形接头中，接头为细长形，接头末端自对准到沿带有多晶硅栅极网孔52的多晶硅栅极层的侧壁所形成的垫片。接头210、211的宽度变窄，使接头210、211上方各自的金属线72和74可以变窄，以便满足制备工艺对金属-金属最小间距的要求。在本说明中，可以利用堆栈通孔236，将金属线72、74连接到它们上方的其他金属层，例如MOSFET器件的第二金属层。
在本发明的其他实施例中，利用其他适合的形状，可以制备自对准的源极/本体接头，制成的源极/本体接头只有一部分接头自对准。由于源极和本体扩散区通过金属硅化物层短接，因此接头的形状不受需要的限制，将源极和本体扩散区作为两个区域连接起来。图7中使用条形接头仅用于解释说明，不用于局限。图8表示在本发明的可选实施例中，含有源极晶胞引入自对准接头的封闭式晶胞横向MOSFET器件的俯视图。参见图8，封闭式晶胞横向MOSFET器件250与图7所示的MOSFET器件200的制备方式相同。金属硅化物层(图中没有表示出)形成在源极晶胞中，以便电短接源极和本体扩散区。然而，在图8中，源极/本体接头260以及漏极接头261呈交叉形，其末端自对准到多晶硅栅极的垫片结构。金属线72和74分别连接到源极/本体接头和漏极接头。堆栈通孔276形成在接头260、261上，用于电连接到它们上方的其他金属层。
虽然为了表述清楚，以上内容对实施例进行了详细介绍，但是本发明并不局限于上述细节。实施本发明还有许多可选方案。文中的实施例仅用于解释说明，不用于局限。

Claims (21)

1.一种封闭式晶胞横向MOS晶体管，其特征在于，包括：
一个第一导电类型轻掺杂的半导体层，半导体层构成晶体管的本体；
一个导电栅极在半导体层的顶面上方，并通过栅极电介质层与半导体层的顶面绝缘，导电栅极构成具有多个开口的网孔，多个开口限定源极晶胞和漏极晶胞的晶胞式阵列；
多个与第一导电类型相反的第二导电类型的扩散区，形成在被网孔中的开口裸露出来的半导体层中，多个扩散区构成源极晶胞和漏极晶胞的晶胞式阵列，其中扩散区的交替行构成晶体管的源极区和漏极区，源极区和漏极区之间的导电栅极下方的半导体层构成晶体管的通道；
一个第一导电类型的本体接触区，形成在源极和漏极晶胞的晶胞式阵列中的一个或多个源极晶胞中，本体接触区的重掺杂程度比半导体层更大，本体接触区被一个或多个源极晶胞中的源极区包围；
一个金属硅化物层，形成在多个扩散区的顶面上，金属硅化物层形成在一个或多个源极晶胞中，以便电连接形成在一个或多个源极晶胞中的源极区和本体接触区；以及
一个源极/本体接头，形成在一个或多个源极晶胞中，并且与金属硅化物层接触，源极/本体接头通过金属硅化物层，电连接到一个或多个源极晶胞中的源极区和本体接触区。
2.根据权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，半导体层包括一个第一导电类型的阱，形成在半导体衬底上，阱构成晶体管的本体。
3.根据权利要求2所述的封闭式晶胞横向MOS晶体管，其特征在于，半导体层包括一个第一导电类型的阱，形成在半导体衬底上的外延层中，阱构成晶体管的本体。
4.根据权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，本体接触区位于被源极区包围的源极晶胞中心。
5.根据权利要求4所述的封闭式晶胞横向MOS晶体管，其特征在于，本体接触区和源极区作为重叠的扩散区。
6.根据权利要求4所述的封闭式晶胞横向MOS晶体管，其特征在于，源极/本体接头位于源极晶胞中的本体接触区上方。
7.根据权利要求6所述的封闭式晶胞横向MOS晶体管，其特征在于，源极/本体接头的尺寸小于源极晶胞中的本体接触区尺寸。
8.根据权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，一个或多个源极晶胞中的源极/本体接头包括一个接头，接头具有最小尺寸，到导电栅极的间距最小，导电栅极包围着各自的源极晶胞。
9.根据权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，导电栅极构成一个网孔，网孔中具有多个尺寸基本一致的开口。
10.根据权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，由网孔形成的多个开口，包括具有第一外围长度的多个第一开口，用于制备源极晶胞，以及具有第二外围长度的多个第二开口，用于制备漏极晶胞，第一外围长度大于第二外围长度。
11.根据权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，在一个或多个源极晶胞中的源极/本体接头包括一个自对准接头，其中接头的至少一部分自对准到各自源极晶胞的外围。
12.根据权利要求11所述的封闭式晶胞横向MOS晶体管，其特征在于，在一个或多个源极晶胞中的源极/本体接头包括一个自对准条形接头，其中接头的至少两个拐角自对准到各自源极晶胞的外围。
13.根据权利要求11所述的封闭式晶胞横向MOS晶体管，其特征在于，在一个或多个源极晶胞中的源极/本体接头包括一个具有交叉形状的自对准条形接头，其中交叉形接头的至少四个末端自对准到各自源极晶胞的外围。
14.根据权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，在一个或多个源极晶胞中的源极/本体接头都包括一个钨插头。
15.权利要求1所述的封闭式晶胞横向MOS晶体管，其特征在于，第一导电类型为P导电类型以及第二导电类型为N导电类型。
16.一种用于制备封闭式晶胞横向MOS晶体管的方法，其特征在于，包括：
制备一个第一导电类型轻掺杂的半导体层，半导体层构成晶体管的本体；
制备一个导电栅极在半导体层的顶面上方，并通过栅极电介质层与半导体层的顶面绝缘，导电栅极构成具有多个开口的网孔，多个开口限定源极晶胞和漏极晶胞的晶胞式阵列；
制备多个与第一导电类型相反的第二导电类型的扩散区，形成在被网孔中的开口裸露出来的半导体层中，多个扩散区构成源极晶胞和漏极晶胞的晶胞式阵列，其中扩散区的交替行构成晶体管的源极区和漏极区，源极区和漏极区之间的导电栅极下方的半导体层构成晶体管的通道；
制备一个第一导电类型的本体接触区，形成在源极和漏极晶胞的晶胞式阵列中的一个或多个源极晶胞中，本体接触区的重掺杂程度比半导体层更大，本体接触区被一个或多个源极晶胞中的源极区包围；
制备一个金属硅化物层，形成在多个扩散区的顶面上，金属硅化物层形成在一个或多个源极晶胞中，以便电连接形成在一个或多个源极晶胞中的源极区和本体接触区；并且
制备一个源极/本体接头，形成在一个或多个源极晶胞中，并且与金属硅化物层接触，源极/本体接头通过金属硅化物层，电连接到一个或多个源极晶胞中的源极区和本体接触区。
17.根据权利要求16所述的方法，其特征在于，制备第一导电类型的半导体层包括：制备第一个第一导电类型的阱，形成在半导体衬底上，阱构成晶体管的本体。
18.根据权利要求16所述的方法，其特征在于，在一个或多个源极晶胞中制备一个第一导电类型的本体接触区，包括：在被源极区包围的源极晶胞中制备本体接触区。
19.根据权利要求16所述的方法，其特征在于，在一个或多个源极晶胞中制备一个第一导电类型的本体接触区，包括：制备本体接触区和源极区，作为重叠的扩散区。
20.根据权利要求16所述的方法，其特征在于，制备源极/本体接头，包括：制备一个源极/本体接头，其尺寸小于源极晶胞中本体接触区的尺寸。
21.根据权利要求16所述的方法，其特征在于，制备源极/本体接头包括：制备一个源极/本体接头，其开口具有最小尺寸，并且到各自源极晶胞周围的导电栅极的间距最小。
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