CN104918423B - A kind of method for manufacturing circuit board of detectable internal layer orifice ring - Google Patents
A kind of method for manufacturing circuit board of detectable internal layer orifice ring Download PDFInfo
- Publication number
- CN104918423B CN104918423B CN201510345336.6A CN201510345336A CN104918423B CN 104918423 B CN104918423 B CN 104918423B CN 201510345336 A CN201510345336 A CN 201510345336A CN 104918423 B CN104918423 B CN 104918423B
- Authority
- CN
- China
- Prior art keywords
- daughter board
- copper
- orifice ring
- wiring board
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a kind of method for manufacturing circuit board of detectable internal layer orifice ring, are related to wiring board production technical field.The production method includes：It provides for pressing the daughter board for making wiring board, daughter board includes PCB units and technique edges；Line pattern in each daughter board PCB units is made, meanwhile, corresponding position etches at least two windows on each daughter board technique edges, and the outer diameter of the diameter of the window minimum orifice ring more designed than in PCB unit is small 0.05mm；Each daughter board is pressed into wiring board；The drilling in PCB units is drilled out, and via hole is drilled out in the center of technique edges surface layer window；Drilling in PCB units and via hole are fabricated to plated through-hole；Make the short-circuit test point of via hole.The detection method of the present invention can ensure the circuit inner cord orifice ring >=0.025mm produced, meet IPC3 grades of standards, the wiring board of internal layer orifice ring >=0.025mm need to be controlled suitable for specializing, can effectively avoid to complain and inspect by random samples caused by this internal layer orifice ring defect unqualified causes to retract the risk scrapped by the gross.
Description
Technical field
The invention belongs to a kind of making of the wiring board of wiring board production technical field more particularly to detectable internal layer orifice ring
Method.
Background technology
In printed wiring board manufacturing process, because of aligning accuracy, the pre- folded aligning accuracy of pressing and the pressing by inner figure
The composite factor of daughter board harmomegathus influences afterwards, can not ensure that all pcb boards meet IPC3 grades of standards after daughter board drilling：That is every layer of internal layer
Orifice ring >=0.025mm of daughter board plated through-hole.And in the application of some wiring boards, it is desirable that all circuit inner cord orifice rings are necessary >=
0.025mm detects that orifice ring is not up to IPC3 grades of standards if extracting 3-5 block plates immediately and third party laboratory being sent to do slice, will
It is determined as that wiring board is bad by the gross, therefore produces the wiring board of category alignment request in view of this, when does shipment slice as in finding
The layer inadequate 0.025mm of orifice ring then can use X-RAY detections screen one by one, choose and be not inconsistent the wiring board of standardization requirement and scrap.But
It is that, because X-RAY detections can only with the naked eye go to distinguish the partially serious plate of inclined hole or layer, each layer of internal layer orifice ring can not be quantified on earth
Have much, therefore cause to claim damages it is possible to wiring board of the internal layer orifice ring less than 0.025mm can be caused to flow into client.
Invention content
In view of the above-mentioned problems, the present invention provides a kind of method for manufacturing circuit board of detectable internal layer orifice ring, concrete scheme is such as
Under：
A kind of method for manufacturing circuit board of detectable internal layer orifice ring, which is characterized in that include the following steps：
S1 is provided for pressing the daughter board for making wiring board, and daughter board includes PCB units and technique edges；Make each daughter board PCB
Line pattern in unit, meanwhile, corresponding position etches at least two windows, the diameter of the window on each daughter board technique edges
Than in PCB unit, the outer diameter of designed minimum orifice ring is small 0.05mm；Daughter board technique edges are covered with layers of copper except the other positions of window,
Layers of copper on technique edges is not turned on the copper wire in PCB units.
Each daughter board is pressed into wiring board by S2；
S3 drills out the drilling in wiring board PCB units, and the window's position drills out via hole on assist side technique edges, described
Via hole is located at the center of the window on wiring board surface layer；
Drilling in PCB units and via hole are fabricated to plated through-hole by S4；
S5 makes the short-circuit test point of via hole.
Preferably, in the step S1, the quantity of window is three, and be arranged side by side.
Preferably, in the step S1, the quantity of window is 5, and in " ten " word arrangement.
Via hole is made on the technique edges of assist side of the present invention, short-circuit test is carried out to via hole, when via hole is tested
During point report short circuit, then illustrate the internal layer orifice ring of this wiring board Shortcomings 0.025mm.
The method of the present invention make detectable internal layer orifice ring wiring board can ensure the circuit inner cord orifice ring produced >=
0.025mm meets IPC3 grades of standards, and the wiring board of internal layer orifice ring >=0.025mm need to be controlled suitable for specializing, can effectively be kept away
Exempting to complain and inspect by random samples caused by this defect unqualified causes to retract the risk scrapped by the gross.
Description of the drawings
Fig. 1 is the vertical view of embodiment of the present invention wiring board PCB units and technique edges.
Fig. 2 is the sectional view of auxiliary hole site after the normal circuit-board drilling via hole of internal layer orifice ring.
Fig. 3 is the sectional view for assisting hole site in Fig. 2 after auxiliary hole metallization.
Sectional views of the Fig. 4 to assist hole site after the circuit-board drilling via hole of internal layer orifice ring exception.
Specific embodiment
In order to more fully understand the present invention technology contents, with reference to specific embodiment to technical scheme of the present invention into
One step introduction and explanation.
Embodiment
As shown in Figure 1, wiring board includes PCB units 1 and technique edges 2, it is desirable that internal layer orifice ring in PCB units 1 >=
0.025mm.Minimum aperture ring width is 0.125mm in PCB units 1, boring aperture 0.1mm (the i.e. orifice ring rings of corresponding minimum orifice ring
Around drilling, the outer diameter of orifice ring is 0.35mm.Technique edges 2 are set there are two window 3, and 3 position of window is without copper, the aperture of window 3
0.3mm, the window's position are equipped with via hole 4, and the aperture of via hole 4 is 0.1mm；Daughter board technique edges are covered with except the other positions of window
Layers of copper, the layers of copper on technique edges 2 are not turned on the copper wire in PCB units 1.
It if Fig. 2 wiring boards are six sandwich circuit boards, is pressed by five daughter boards, the first daughter board includes the first layers of copper 51 and the
One core plate 52, the second daughter board include the second layers of copper 61 and the second core plate 62, and third daughter board includes third layers of copper 71 and third core plate
72, the 4th daughter board includes the 4th layers of copper 81 and the 4th core plate 82, and the 5th daughter board includes the 5th layers of copper 91, the 5th core plate 92 and the 6th
Layers of copper 93.
The production method of the wiring board is：
First to the 5th daughter board is made into PCB unit line figures respectively, PCB unit line figures are made in each daughter board
Meanwhile corresponding position etches two windows 3 on daughter board technique edges, line pattern corresponds to minimum orifice ring outer diameter in PCB units 1
Bore position a diameter of 0.35mm of Xi Quan (Xi Quan positions drilling then form orifice ring), the aperture of window 3 is 0.3mm.Each son
After the completion of plate graphic making, the layers of copper on daughter board technique edges 2 is not turned on the copper wire in daughter board PCB units 1.
Each daughter board is pressed into the wiring board of six sandwich circuits with PP glue 10,3 position of window after pressing on each daughter board corresponds to；
Using the telltale mark of outer layer as target, the drilling in pressing rear board PCB units 1 is drilled out, and in 1 window of technique edges
3 positions of mouth drill out the via hole 4 that aperture is 0.1mm, and via hole 4 is located at the center of wiring board outer layer window 3；
By above-mentioned wiring board pad pasting, exposure, development, heavy copper, the drilling in PCB units and via hole are fabricated to metallization
Hole；
The short-circuit test point of via hole is finally made, the short-circuit conditions through short-circuit test point detection via hole, if short-circuit,
Wiring board is there are internal layer orifice ring less than or equal to 0.025mm；If breaking, meet internal layer orifice ring more than 0.025mm.
As shown in figure 3, the metal layer of 3 inner wall of via hole and the layers of copper on each daughter board technique edges surface are not connected to, short-circuit test
When will be shown as open circuit, illustrate that offset between each daughter board is less than 0.1mm, internal layer orifice ring minimum widith still greater than
0.025mm。
As shown in figure 4, the metal layer of 3 inner wall of via hole is connect with the third layers of copper 71 of third daughter board technique edges, illustrate
The offset of three daughter boards is more than 0.1mm, and when short-circuit test will be shown as short circuit, illustrate that internal layer orifice ring is less than or waits there are orifice ring
In 0.025mm, judge that the wiring board is unqualified.
It should be noted that the detection method of the present invention is not limited to only make two via holes, or multiple auxiliary
Hole, such as three via holes are arranged side by side or five via holes are in " ten " word arrangement.Via hole is more, and the result of open circuit detection is more smart
Really.
It is upper described only with embodiment come the technology contents that further illustrate the present invention, in order to which reader is easier to understand, but
Embodiments of the present invention are not represented and are only limitted to this, and any technology done according to the present invention extends or recreation, by the present invention
Protection.
Claims (1)
1. a kind of method for manufacturing circuit board of detectable internal layer orifice ring, which is characterized in that the wiring board is six sandwich circuit boards, by
Five daughter boards press, and the daughter board includes PCB units and technique edges；First daughter board includes the first layers of copper and the first core plate,
Second daughter board includes the second layers of copper and the second core plate, and third daughter board includes third layers of copper and third core plate, and the 4th daughter board includes the
Four layers of copper and the 4th core plate, the 5th daughter board include the 5th layers of copper, the 5th core plate and the 6th layers of copper；
The production method of the wiring board includes the following steps：
S1 makes PCB unit line figures respectively in the described first to the 5th daughter board PCB units, is set on the technique edges
There are at least two windows, the aperture of the window is 0.3mm, and the bore position of the PCB unit lines figure is equipped with Xi Quan, institute
It states Xi Quan and forms orifice ring after piercing, minimum aperture ring diameter is 0.35mm in the PCB unit lines figure；
Each daughter board is synthesized the wiring board of six sandwich circuits by S2 with PP glue laminateds, and the window's position after pressing on each daughter board corresponds to identical；
The PCB units of wiring board outer layer described in S3 are equipped with telltale mark, drill at the telltale mark, aperture is
0.1mm；The window's position of technique edges is equipped with the via hole that aperture is 0.1mm, and via hole is located at the center of wiring board outer layer window；
Drilling in PCB units and via hole are fabricated to metallization by above-mentioned wiring board pad pasting, exposure, development, heavy copper by S4
Hole, the daughter board technique edges are covered with layers of copper except the other positions of window, and the layers of copper on the daughter board technique edges and daughter board PCB are mono-
Copper wire in member is not turned on；
S5 makes the short-circuit test point of via hole, the short-circuit conditions through short-circuit test point detection via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510345336.6A CN104918423B (en) | 2015-06-19 | 2015-06-19 | A kind of method for manufacturing circuit board of detectable internal layer orifice ring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510345336.6A CN104918423B (en) | 2015-06-19 | 2015-06-19 | A kind of method for manufacturing circuit board of detectable internal layer orifice ring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104918423A CN104918423A (en) | 2015-09-16 |
| CN104918423B true CN104918423B (en) | 2018-06-15 |
Family
ID=54086992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510345336.6A Expired - Fee Related CN104918423B (en) | 2015-06-19 | 2015-06-19 | A kind of method for manufacturing circuit board of detectable internal layer orifice ring |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104918423B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105682378B (en) * | 2016-04-11 | 2018-08-31 | 广州兴森快捷电路科技有限公司 | A kind of detection method of PCB internal layers interconnection defect |
| CN105934069B (en) * | 2016-05-31 | 2019-04-05 | Oppo广东移动通信有限公司 | A kind of multiple-printed-panel for circuit board |
| CN106102317A (en) * | 2016-06-28 | 2016-11-09 | 广东欧珀移动通信有限公司 | Pcb board and there is its mobile terminal |
| CN109287082B (en) * | 2018-11-28 | 2022-02-18 | 郑州云海信息技术有限公司 | Testing method and device for circuit board easy to short circuit |
| CN212034444U (en) * | 2020-06-19 | 2020-11-27 | 昆山达卡特电子有限公司 | High-strength double-layer PCB |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2677944Y (en) * | 2003-12-03 | 2005-02-09 | 陈嘉隆 | Device for detecting circuit board |
| CN101662895A (en) * | 2008-08-25 | 2010-03-03 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board, manufacturing method thereof and method for detecting alignment of circuit board |
| CN103363885A (en) * | 2012-03-31 | 2013-10-23 | 北大方正集团有限公司 | Method measuring interlayer offset of printed circuit board (PCB) and in-process PCB |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4387292B2 (en) * | 2004-12-10 | 2009-12-16 | 日本メクトロン株式会社 | Electrical inspection apparatus and electrical inspection method for flexible printed circuit board |
| CN103983809A (en) * | 2013-02-08 | 2014-08-13 | 辉达公司 | PCB and online testing structure thereof, and manufacturing method of online testing structure |
-
2015
- 2015-06-19 CN CN201510345336.6A patent/CN104918423B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2677944Y (en) * | 2003-12-03 | 2005-02-09 | 陈嘉隆 | Device for detecting circuit board |
| CN101662895A (en) * | 2008-08-25 | 2010-03-03 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board, manufacturing method thereof and method for detecting alignment of circuit board |
| CN103363885A (en) * | 2012-03-31 | 2013-10-23 | 北大方正集团有限公司 | Method measuring interlayer offset of printed circuit board (PCB) and in-process PCB |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104918423A (en) | 2015-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104918423B (en) | A kind of method for manufacturing circuit board of detectable internal layer orifice ring | |
| US20100319979A1 (en) | Printed circuit board and method for drilling hole therein | |
| CN104717846B (en) | The preparation method of metallization slotted eye in a kind of PCB | |
| CN105517349B (en) | Back drill detection method | |
| CN104582288A (en) | PCB back drilling plate back drilling depth detecting method | |
| CN104540338B (en) | High Aligning degree HDI production methods | |
| CN104596925A (en) | Method for detecting binding force of metallized blind hole bottom and inner-layer base copper of HDI (High Density Interconnect) plate | |
| CN106961796B (en) | A kind of production method convenient for detecting the PCB of back drill hole precision | |
| CN104640380B (en) | A kind of non-heavy copper hole with orifice ring and print circuit plates making method | |
| CN105764241A (en) | Method for testing alignment of printed board product | |
| CN104284512A (en) | Multi-layer circuit board with back drill depth detection structure and back drill depth monitoring method thereof | |
| CN104880162A (en) | Method for detecting drilling hole offset degree of PCB | |
| CN107770974A (en) | A kind of design of level to level alignment degree detection module | |
| CN104582330B (en) | The production method of the ATE plates of buried blind via structure | |
| CN103517556B (en) | A kind of circuit board depth control type drilling depth determining method and circuit board | |
| CN102706267B (en) | Blind hole offset detecting method | |
| CN104378931A (en) | Method for manufacturing metallized counterbore in PCB | |
| CN103702509B (en) | Step-like wiring board and preparation method thereof | |
| CN102111961B (en) | Method for detecting process capability of inner and outer layers of circuit board | |
| CN108551731A (en) | Production method of the aperture without the exposed non-metallic hole of base material on a kind of wiring board | |
| CN106525114B (en) | The test method of production line drilling ability in a kind of positive blade technolgy | |
| CN105430906B (en) | A kind of boring method of circuit board | |
| CN103796415A (en) | Multilayer circuit board and method for manufacturing same | |
| CN205657906U (en) | Circuit board convenient to detect back drilling degree of depth | |
| CN205808341U (en) | Machinery blind drilling depth test device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180615 Termination date: 20200619 |