CN104918423A - Manufacturing method for circuit board capable of detecting inner-layer pore ring - Google Patents
Manufacturing method for circuit board capable of detecting inner-layer pore ring Download PDFInfo
- Publication number
- CN104918423A CN104918423A CN201510345336.6A CN201510345336A CN104918423A CN 104918423 A CN104918423 A CN 104918423A CN 201510345336 A CN201510345336 A CN 201510345336A CN 104918423 A CN104918423 A CN 104918423A
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- board
- pcb unit
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- circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The present invention discloses a manufacturing method for a circuit board capable of detecting an inner-layer hole ring and relates to the technical field of production of circuit boards. The manufacturing method comprises: providing a secondary board for pressing and manufacturing the circuit board, wherein the secondary board comprises a PCB unit and a technical edge; manufacturing a circuit pattern in the PCB unit of each secondary board; meanwhile, etching at least two windows at a corresponding position on the technical edge of each secondary board, wherein the diameter of each window is 0.05mm smaller than the outer diameter of a smallest hole ring designed in the PCB unit; pressing each secondary board into the circuit board; drilling a borehole in the PCB unit and drilling an auxiliary hole at the central position of the window on the surface of the technical edge; manufacturing the borehole and the auxiliary hole in the PCB unit into metallized holes; and manufacturing a short-circuit test point of the auxiliary hole. The detection method provided by the present invention can ensure that the inner-layer hole ring of the manufactured circuit board has the diameter that is more than or equal to 0.025mm and meets IPC3 stage standard, is applicable to the circuit board that is particularly indicated that the diameter of the hole ring is required to be controlled to be more than or equal to 0.025mm, so as to effectively avoid complaints resulting from the defect of the inner-layer hole ring and the risk of the whole batch being returned and scrapped due to failure in a sample test.
Description
Technical field
The invention belongs to and relate to wiring board production technical field, particularly relate to a kind of method for manufacturing circuit board detecting internal layer orifice ring.
Background technology
In printed wiring board manufacturing process, because the composite factor of daughter board harmomegathus affects after the aligning accuracy of folding in advance by the aligning accuracy of inner figure, pressing and pressing, cannot ensure that all pcb boards meet IPC3 grade standard after daughter board boring: i.e. orifice ring >=the 0.025mm in internal layer every straton sheetmetal hole.And in the application of some wiring boards, require all wiring board internal layer orifice rings necessary >=0.025mm, if extraction 3-5 block plate send third party laboratory to do section and detects that orifice ring does not reach IPC3 grade standard immediately, will be judged to be that wiring board is bad by the gross, therefore produce the wiring board being directed to this type of standard-required, when doing shipment section as found the inadequate 0.025mm of internal layer orifice ring, then X-RAY can be adopted to detect and to screen one by one, choose the wiring board not meeting standard-required and scrap.But with the naked eye can only remove because X-RAY detects the plate that distinguishes that inclined hole or layer are partially serious, the internal layer orifice ring that cannot quantize every one deck has much on earth, therefore still have the wiring board inflow client of the not enough 0.025mm of internal layer orifice ring may be caused to cause claim.
Summary of the invention
For the problems referred to above, the invention provides a kind of method for manufacturing circuit board detecting internal layer orifice ring, concrete scheme is as follows:
Detect a method for manufacturing circuit board for internal layer orifice ring, it is characterized in that, comprise the following steps:
S1 is provided for the daughter board that pressing makes wiring board, and daughter board comprises PCB unit and technique edges; Make line pattern in each daughter board PCB unit, meanwhile, on each daughter board technique edges, relevant position etches at least two windows, the diameter 0.05mm less of the external diameter of minimum orifice ring designed in PCB unit of described window; Daughter board technique edges is covered with layers of copper except other positions of window, the copper wire not conducting in the layers of copper on technique edges and PCB unit.
Each daughter board is pressed into wiring board by S2;
S3 gets out the boring in wiring board PCB unit, and the window's position gets out via hole on wiring board technique edges, and described via hole is positioned at the center of the window on wiring board top layer;
Boring in PCB unit and via hole are made into plated-through hole by S4;
S5 makes the short-circuit test point of via hole.
Preferably, in described step S1, the quantity of window is three, and is arranged side by side.
Preferably, in described step S1, the quantity of window is 5, and in " ten " word arrangement.
The present invention makes via hole on the technique edges of wiring board, carries out short-circuit test to via hole, when the report short circuit of via hole test point, then the internal layer orifice ring of this wiring board Shortcomings 0.025mm is described.
The wiring board of the detected internal layer orifice ring that the inventive method makes can ensure the wiring board internal layer orifice ring >=0.025mm produced, meet IPC3 grade standard, be applicable to specialize the wiring board that need control internal layer orifice ring >=0.025mm, the complaint can effectively avoiding this defect to cause and inspect defective causing by random samples and return the risk of scrapping by the gross.
Accompanying drawing explanation
Fig. 1 is the vertical view of embodiment of the present invention wiring board PCB unit and technique edges.
Fig. 2 is the cutaway view of via hole position after the normal circuit-board drilling via hole of internal layer orifice ring.
Fig. 3 is the cutaway view of via hole position after via hole metallization in Fig. 2.
Fig. 4 is the cutaway view of via hole position after the circuit-board drilling via hole of internal layer orifice ring exception.
Embodiment
In order to more fully understand technology contents of the present invention, below in conjunction with specific embodiment technical scheme of the present invention being introduced further and illustrating.
Embodiment
As shown in Figure 1, wiring board comprises PCB unit 1 and technique edges 2, requires the internal layer orifice ring >=0.025mm in PCB unit 1.In PCB unit 1, minimum aperture ring width is 0.125mm, and (namely orifice ring is around boring, and the external diameter of orifice ring is 0.35mm for the boring aperture 0.1mm of corresponding minimum orifice ring.Technique edges 2 is provided with two windows 3, and window 3 position is without copper, and the aperture of window 3 is 0.3mm, and the window's position is provided with via hole 4, and the aperture of via hole 4 is 0.1mm; Daughter board technique edges is covered with layers of copper except other positions of window, the copper wire not conducting in the layers of copper on technique edges 2 and PCB unit 1.
If Fig. 2 wiring board is six sandwich circuit boards, formed by five daughter board pressings, first daughter board comprises the first layers of copper 51 and the first central layer 52, second daughter board comprises the second layers of copper 61 and the second central layer 62,3rd daughter board comprises the 3rd layers of copper 71 and the 3rd central layer 72,4th daughter board comprises the 4th layers of copper 81 and the 4th central layer the 82, five daughter board comprises the 5th layers of copper 91, the 5th central layer 92 and the 6th layers of copper 93.
The manufacture method of this wiring board is:
First to the 5th daughter board is made PCB unit line figure respectively, while each daughter board makes PCB unit line figure, on daughter board technique edges, relevant position etches two windows 3, in PCB unit 1, Xi Quan (forming orifice ring after the boring of the Xi Quan position) diameter of the bore position of the corresponding minimum orifice ring external diameter of line pattern is 0.35mm, and the aperture of window 3 is 0.3mm.After each daughter board graphic making completes, the copper wire not conducting in the layers of copper on daughter board technique edges 2 and this daughter board PCB unit 1.
Each daughter board PP glue 10 is pressed into the wiring board of six sandwich circuits, window 3 position after pressing on each daughter board is corresponding;
With outer field telltale mark for target, get out the boring in pressing rear board PCB unit 1, and get out in technique edges 1 window 3 position the via hole 4 that aperture is 0.1mm, via hole 4 is positioned at the center of the outer window 3 of wiring board;
By above-mentioned wiring board pad pasting, exposure, development, heavy copper, the boring in PCB unit and via hole are made into plated-through hole;
Finally make the short-circuit test point of via hole, detect the short-circuit conditions of via hole through short-circuit test point, if short circuit, then there is internal layer orifice ring and be less than or equal to 0.025mm in wiring board; If open circuit, then meet internal layer orifice ring and be greater than 0.025mm.
As shown in Figure 3, the metal level of via hole 3 inwall is not connected with the layers of copper on each daughter board technique edges surface, and will be shown as open circuit during short-circuit test, illustrate that the side-play amount between each daughter board is less than 0.1mm, internal layer orifice ring minimum widith is still greater than 0.025mm.
As shown in Figure 4, the metal level of via hole 3 inwall is connected with the 3rd layers of copper 71 of the 3rd daughter board technique edges, illustrates that the side-play amount of the 3rd daughter board is more than 0.1mm, will be shown as short circuit during short-circuit test, illustrate that internal layer orifice ring exists orifice ring and is less than or equal to 0.025mm, judge that this wiring board is defective.
It should be noted that, detection method of the present invention is not limited to only make two via holes, also can be multiple via hole, as three via holes be arranged side by side or five via holes in " ten " word arrangement.Via hole is more, and the result that open circuit detects is more accurate.
Only further illustrate technology contents of the present invention with embodiment described in upper, so that reader is easier to understand, but does not represent embodiments of the present invention and be only limitted to this, any technology done according to the present invention extends or recreation, all by protection of the present invention.
Claims (3)
1. can detect a method for manufacturing circuit board for internal layer orifice ring, it is characterized in that, comprise the following steps:
S1 is provided for the daughter board that pressing makes wiring board, and daughter board comprises PCB unit and technique edges; Make line pattern in each daughter board PCB unit, meanwhile, on each daughter board technique edges, relevant position etches at least two windows, the diameter 0.05mm less of the external diameter of minimum orifice ring designed in PCB unit of described window;
Each daughter board is pressed into wiring board by S2;
S3 gets out the boring in wiring board PCB unit, and the window's position gets out via hole on wiring board technique edges, and described via hole is positioned at the center of the window on wiring board top layer;
Boring in PCB unit and via hole are made into plated-through hole by S4;
S5 makes the short-circuit test point of via hole.
2. the method for manufacturing circuit board detecting internal layer orifice ring according to claim 1, is characterized in that, in described step S1, the quantity of window is three, and is arranged side by side.
3. the method for manufacturing circuit board detecting internal layer orifice ring according to claim 1, is characterized in that, in described step S1, the quantity of window is 5, and in " ten " word arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510345336.6A CN104918423B (en) | 2015-06-19 | 2015-06-19 | A kind of method for manufacturing circuit board of detectable internal layer orifice ring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510345336.6A CN104918423B (en) | 2015-06-19 | 2015-06-19 | A kind of method for manufacturing circuit board of detectable internal layer orifice ring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104918423A true CN104918423A (en) | 2015-09-16 |
| CN104918423B CN104918423B (en) | 2018-06-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510345336.6A Expired - Fee Related CN104918423B (en) | 2015-06-19 | 2015-06-19 | A kind of method for manufacturing circuit board of detectable internal layer orifice ring |
Country Status (1)
| Country | Link |
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| CN (1) | CN104918423B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105682378A (en) * | 2016-04-11 | 2016-06-15 | 广州兴森快捷电路科技有限公司 | ICD (Internal Connection Defect) detection method for PCB |
| CN105934069A (en) * | 2016-05-31 | 2016-09-07 | 广东欧珀移动通信有限公司 | Circuit board jointed board |
| CN106102317A (en) * | 2016-06-28 | 2016-11-09 | 广东欧珀移动通信有限公司 | Pcb board and there is its mobile terminal |
| CN109287082A (en) * | 2018-11-28 | 2019-01-29 | 郑州云海信息技术有限公司 | A kind of test method and device of easy short circuit line plate |
| WO2021253473A1 (en) * | 2020-06-19 | 2021-12-23 | 昆山达卡特电子有限公司 | High-strength double-layer pcb |
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| CN2677944Y (en) * | 2003-12-03 | 2005-02-09 | 陈嘉隆 | Device for detecting circuit board |
| JP2006170623A (en) * | 2004-12-10 | 2006-06-29 | Nippon Mektron Ltd | Electric inspection device and electric inspection method of flexible printed board |
| CN101662895A (en) * | 2008-08-25 | 2010-03-03 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board, manufacturing method thereof and method for detecting alignment of circuit board |
| CN103363885A (en) * | 2012-03-31 | 2013-10-23 | 北大方正集团有限公司 | Method measuring interlayer offset of printed circuit board (PCB) and in-process PCB |
| US20140229783A1 (en) * | 2013-02-08 | 2014-08-14 | Nvidia Corporation | In-circuit test structure for printed circuit board |
-
2015
- 2015-06-19 CN CN201510345336.6A patent/CN104918423B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2677944Y (en) * | 2003-12-03 | 2005-02-09 | 陈嘉隆 | Device for detecting circuit board |
| JP2006170623A (en) * | 2004-12-10 | 2006-06-29 | Nippon Mektron Ltd | Electric inspection device and electric inspection method of flexible printed board |
| CN101662895A (en) * | 2008-08-25 | 2010-03-03 | 富葵精密组件(深圳)有限公司 | Multilayer circuit board, manufacturing method thereof and method for detecting alignment of circuit board |
| CN103363885A (en) * | 2012-03-31 | 2013-10-23 | 北大方正集团有限公司 | Method measuring interlayer offset of printed circuit board (PCB) and in-process PCB |
| US20140229783A1 (en) * | 2013-02-08 | 2014-08-14 | Nvidia Corporation | In-circuit test structure for printed circuit board |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105682378A (en) * | 2016-04-11 | 2016-06-15 | 广州兴森快捷电路科技有限公司 | ICD (Internal Connection Defect) detection method for PCB |
| CN105682378B (en) * | 2016-04-11 | 2018-08-31 | 广州兴森快捷电路科技有限公司 | A kind of detection method of PCB internal layers interconnection defect |
| CN105934069A (en) * | 2016-05-31 | 2016-09-07 | 广东欧珀移动通信有限公司 | Circuit board jointed board |
| CN105934069B (en) * | 2016-05-31 | 2019-04-05 | Oppo广东移动通信有限公司 | A kind of multiple-printed-panel for circuit board |
| CN106102317A (en) * | 2016-06-28 | 2016-11-09 | 广东欧珀移动通信有限公司 | Pcb board and there is its mobile terminal |
| CN109287082A (en) * | 2018-11-28 | 2019-01-29 | 郑州云海信息技术有限公司 | A kind of test method and device of easy short circuit line plate |
| CN109287082B (en) * | 2018-11-28 | 2022-02-18 | 郑州云海信息技术有限公司 | Testing method and device for circuit board easy to short circuit |
| WO2021253473A1 (en) * | 2020-06-19 | 2021-12-23 | 昆山达卡特电子有限公司 | High-strength double-layer pcb |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104918423B (en) | 2018-06-15 |
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Granted publication date: 20180615 Termination date: 20200619 |