CN104882431A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN104882431A CN104882431A CN201410357407.XA CN201410357407A CN104882431A CN 104882431 A CN104882431 A CN 104882431A CN 201410357407 A CN201410357407 A CN 201410357407A CN 104882431 A CN104882431 A CN 104882431A
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- China
- Prior art keywords
- semiconductor substrate
- pad group
- outer pad
- semiconductor device
- coupled
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 250
- 239000000758 substrate Substances 0.000 claims abstract description 198
- 230000008878 coupling Effects 0.000 claims abstract description 22
- 238000010168 coupling process Methods 0.000 claims abstract description 22
- 238000005859 coupling reaction Methods 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 42
- 230000006870 function Effects 0.000 claims description 37
- 238000010276 construction Methods 0.000 claims description 36
- 230000004888 barrier function Effects 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 238000003860 storage Methods 0.000 description 38
- 241000478345 Afer Species 0.000 description 32
- 238000010586 diagram Methods 0.000 description 15
- 238000012536 packaging technology Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000004927 fusion Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 240000001439 Opuntia Species 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- -1 wherein Substances 0.000 description 1
Classifications
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Abstract
一种半导体器件包括:操作电路,其形成在半导体衬底的顶表面上;存储器阵列,其形成在操作电路之上;内焊盘组,其形成在操作电路和存储器阵列之间的中间层上,且与操作电路耦接;第一外焊盘组,其形成在半导体衬底的底表面上;以及接线结构,其穿过半导体衬底,且将内焊盘组与第一外焊盘组耦接。
Description
相关申请的交叉引用
本申请要求2014年2月27日提交的申请号为10-2014-0023437的韩国专利申请的优先权,其全部公开通过引用合并于此。
技术领域
各种实施例总体而言涉及一种半导体器件,并且更具体地涉及一种包括焊盘的半导体器件。
背景技术
用于增加数据储存容量的一种方法是在预定面积内提供更多数量的存储器单元。另外,为了减小半导体芯片的尺寸,可以将多个半导体衬底层叠。每个半导体衬底可以包括焊盘。可以通过导线接合来将电路板和半导体衬底的焊盘耦接。为了暴露出半导体衬底的焊盘,半导体衬底可以层叠且彼此偏移一宽度,所述宽度容许暴露出半导体衬底的焊盘。结果,随着层叠的半导体衬底的数量增加,半导体芯片的尺寸可能增加。
发明内容
各种实施例涉及一种半导体器件,所述半导体器件具有形成在半导体衬底之上的、数量增加的存储器单元,且随着层叠的半导体衬底数量的增加,半导体芯片的尺寸增长减小。
根据本发明的一个实施例的半导体器件可以包括:操作电路,其形成在半导体衬底的顶表面上;存储器阵列,其形成在操作电路之上;内焊盘组,其形成在操作电路和存储器阵列之间的中间层上且与操作电路耦接;第一外焊盘组,其形成在半导体衬底的底表面上;以及接线结构,其穿过半导体衬底且将内焊盘组与第一外焊盘组耦接。
根据本发明的另一个实施例的半导体器件可以包括:电路板;半导体衬底,在每个半导体衬底中,内焊盘组和存储器阵列顺序地层叠在半导体衬底的顶表面上,并且外焊盘组形成在半导体衬底的底表面上;接线结构,其分别形成在半导体衬底中,其中,每个接线结构穿过每个半导体衬底以将内焊盘组与外焊盘组耦接;以及连接构件,每个连接构件将电路板与每个半导体衬底的外焊盘组耦接,其中,半导体衬底翻转且层叠在电路板上。
根据本发明的另一个实施例的半导体器件可以包括:电路板;半导体衬底,在每个半导体衬底中,内焊盘组和存储器阵列顺序地层叠在半导体衬底的顶表面上,并且第一外焊盘组和第二外焊盘组在半导体衬底的底表面上彼此电耦接,其中,半导体衬底层叠在电路板上;接线结构,其穿过半导体衬底,使得每个半导体衬底的内焊盘组与半导体衬底的第一外焊盘组耦接,其中,每个接线结构形成在每个半导体衬底中;以及连接构件,每个连接构件将电路板与奇数层中的每个半导体衬底的第一外焊盘组耦接,其中奇数层中的半导体衬底翻转且层叠。
附图说明
图1是说明根据本发明的一个实施例的半导体衬底的平面图;
图2是说明图1中所示的存储器阵列中包括的存储串的三维图;
图3是说明图1中所示的存储器阵列中包括的存储串的电路图;
图4A和图4B是说明图1中所示的存储器阵列的三维电路图;
图5A和图5B是根据本发明的一个实施例的半导体器件的截面图;
图6至图14是说明根据本发明的一个实施例的半导体器件的封装工艺的图;
图15至图22是说明根据本发明的另一个实施例的半导体器件的封装工艺的图;
图23和图24是说明根据本发明的另一个实施例的半导体器件的封装工艺的图;
图25和图26是说明根据本发明的另一个实施例的半导体器件的封装工艺的图;
图27是说明根据本发明的一个实施例的存储系统的示意性框图;
图28是说明根据前面描述的各种实施例的、根据编程操作的融合式存储器件或融合式存储系统的示意性框图;以及
图29是根据本发明的一个实施例的包括快闪存储器件的计算系统的示意性框图。
具体实施方式
在下文中,将参考附图来详细描述各种实施例。提供附图以使本领域技术人员理解本公开的实施例。然而,本发明可以用不同形式实施,且不应当被解释为局限于本文提出的实施例。更确切的,提供这些实施例使得本公开透彻且完整,且将向本领域技术人员充分地表达本发明的范围。
此外,“连接/耦接”表示一个部件与另一个部件直接耦接或经由另外的部件间接耦接。在本说明书中,只要未在句子中特意提及,单数形式可以包括复数形式,反之亦然。此外,本说明书中使用的“包括/包含”或“包括有/包含有”表示存在或增加一个或更多个部件、步骤、操作和元件。
应当容易理解的是,本公开中的“在…上”和“在…之上”的含义应当以最广义的方式来解释,使得“在…上”不仅表示“直接在某物上”,而且也表示在具有中间特征或中间层的情况下“在某物上”,以及“在…之上”不仅表示直接在顶部,而且也表示在具有中间特征或中间层的情况下在某物的顶部。
图1是说明根据本发明的一个实施例的半导体衬底的平面图。
参见图1,半导体衬底100可以包括操作电路120A至120D。存储器阵列110A和110B可以形成在操作电路120A至120D之上。另外,内焊盘INNER_PAD组可以形成在操作电路120A至120D与存储器阵列110A和110B之间的中间层上。半导体衬底100的形成有操作电路120A至120D、内焊盘INNER_PAD组以及存储器阵列110A和110B的表面,可以被定义为半导体衬底100的顶表面。
操作电路120A至120D可以形成在半导体衬底100的整个顶表面之上。存储器阵列110A和110B可以形成在操作电路120A至120D的大部分上部面积上。因此,存储器阵列110A和110B的面积几乎可以等于半导体衬底100的面积。结果,存储器单元的数量可以在存储器阵列110A和110B的面积内最大化。
操作电路120A和120B可以包括控制电路、电压供应电路和输入/输出电路。操作电路120C可以包括读取/写入电路。读取/写入电路可以在存储器阵列110A和110B之间的区域120E中与存储器阵列110A和110B的位线(未示出)耦接。包括读取/写入电路的操作电路120C可以形成在半导体衬底100的中心。操作电路120D可以包括字线驱动器。
电压供应电路可以产生用于读取操作、编程循环或擦除循环的操作电压,诸如编程电压、读取电压、擦除电压、通过电压、选择电压、公共源极电压和验证电压。字线驱动器可以将操作电压传输至本地线,例如存储块(未示出)中的选中存储块的字线、选择线和公共源极线(未示出)。读取/写入电路可以经由位线(未示出)与存储块电耦接。另外,读取/写入电路可以在编程操作期间响应于储存在存储器单元中的数据而选择性地对选中位线预充电或放电,以及在读取操作期间感测选中位线的电压变化或电流变化,且锁存储存在存储器单元中的数据。读取/写入电路可以包括页缓冲器。输入/输出电路可以将从外部源输入的命令信号和地址信号传输至控制电路。另外,输入/输出电路可以在编程操作期间将外部输入的数据传输至读取/写入电路,或在读取操作期间将从存储器单元读取的数据向外输出。控制电路可以控制电压供应电路、字线驱动器、读取/写入电路和输入/输出电路。
存储器阵列可以具有三维结构。更具体地,图2是说明图1中所示的存储器阵列110A和110B中包括的存储串的三维图。图3是说明图1中所示的存储器阵列110A和110B中包括的存储串的电路图。
参见图2和图3,公共源极线SL可以形成在半导体衬底100之上,在所述半导体衬底100中形成有P阱PW。垂直沟道层SP可以形成在公共源极线SL上。垂直沟道层SP的顶部可以与位线BL耦接。垂直沟道层SP可以包括多晶硅。多个导电层SGS、WL0至WLn以及SGD可以在不同高度包围垂直沟道层SP。包括电荷储存层的多层(未示出)可以形成在垂直沟道层SP的表面上。所述多层也可以形成在垂直沟道层SP与导电层SGS、WL0至WLn和SGD之间。
最下层导电层可以是源极选择线SGS或第一选择线,而最上层导电层可以是漏极选择线SGD或第二选择线。源极选择线SGS和漏极选择线SGD之间的导电层可以是字线WL0至WLn。换言之,导电层SGS、WL0至WLn和SGD可以在半导体衬底之上形成为多个层,且穿过导电层SGS、WL0至WLn和SGD的垂直沟道层SP可以沿着垂直方向耦接在形成于半导体衬底之上的位线BL和公共源极线SL之间。
漏极选择晶体管SDT或第二选择晶体管可以形成在最上层导电层SGD包围垂直沟道层SP之处。源极选择晶体管SST或第一选择晶体管可以形成在最下层导电层SGS包围垂直沟道层SP之处。存储器单元C0至Cn可以形成在中间导电层WL0至WLn包围垂直沟道层SP之处。
因此,如上述配置的存储串可以包括在公共源极线SL和位线BL之间沿着与衬底垂直的方向耦接的源极选择晶体管SST、存储器单元C0至Cn、以及漏极选择晶体管SDT。源极选择晶体管SST可以响应于施加至第一选择线SGS的第一选择信号而将存储器单元C0至Cn与公共源极线SL电耦接。漏极选择晶体管SDT可以响应于施加至第二选择线SGD的第二选择信号而将存储器单元C0至Cn与位线BL电耦接。
图4A和图4B是说明图1中示出的存储器阵列110A和110B的三维电路图。
参见图4A,存储块层110BL0可以包括沿着与衬底水平的方向布置的多个存储块MB。每个存储块可以包括耦接在位线BL0至BLk与公共源极线SL之间的存储串。在图4A中,出于说明性目的,示出了五个存储块MB和三个位线。在存储块层110BL0中,存储块MB可以共用位线BL0至BLk,而存储块MB的公共源极线SL可以彼此分开。位线BL0至BLk可以沿着与水平布置存储块MB的方向平行的方向延伸。
在每个存储块MB中,多个存储串可以与位线BL0至BLk中的每个耦接。每个存储串可以包括与公共源极线SL耦接的第一选择晶体管SST或源极选择晶体管、与位线BL0耦接的第二选择晶体管SDT或漏极选择晶体管、以及在第一选择晶体管SST和第二选择晶体管SDT之间串联地垂直耦接的存储器单元C0至Cn。
存储块MB中的相应的存储串包括的存储器单元C0至Cn可以分别共用对应的字线WLA0至WLAn。即,字线WLA0至WLAn——每个沿着水平方向与对应的存储器单元C0至Cn耦接——可以彼此耦接。换言之,在存储块MB中,形成在同一层中且沿着水平方向彼此相邻的字线可以彼此耦接。
与存储块MB中的不同位线BL0至BLk耦接的存储串的漏极选择晶体管SDT可以共用漏极选择线中的一个(例如,SGD0_0)。换言之,与不同位线BL0至BLk耦接的漏极选择晶体管SDT可以通过漏极选择线中的一个(例如,SGD0_0)彼此耦接。然而,与存储块MB中的同一位线(例如,BL0)耦接的存储串的漏极选择晶体管SDT可以与不同的漏极选择线SGD0_0至SGD0_i耦接。换言之,漏极选择线SGD0_0至SGD0_i——每个与耦接至同一位线(例如,BL0)的存储串的漏极选择晶体管SDT耦接——可以彼此分隔。因此,与同一位线(例如,BL0)耦接的漏极选择晶体管SDT可以通过不同的操作电压来独立地操作。漏极选择线SGD0_0至SGD0_i可以沿着与位线BL0至BLk相交叉的方向延伸。
与漏极选择线SGD0_0至SGD0_i类似,与存储块MB中的不同位线BL0至BLk耦接的存储串的源极选择晶体管SST可以共用源极选择线中的一个(例如,SGS0_0)。换言之,与不同位线BL0至BLk耦接的源极选择晶体管SST可以通过源极选择线中的一个(例如,SGS0_0)彼此耦接。然而,与存储块MB中的同一位线(例如,BL0)耦接的存储串的源极选择晶体管SST可以与不同的源极选择线SGS0_0至SGS0_j耦接。换言之,源极选择线SGS0_0至SGS0_j——每个与耦接至同一位线(例如,BL0)的存储串的源极选择晶体管SST耦接——可以彼此分隔。因此,与同一位线(例如,BL0)耦接的源极选择晶体管SST可以通过不同的操作电压来独立地操作。源极选择线SGS0_0至SGS0_j可以沿着与位线BL0至BLk相交叉的方向延伸。
然而,所有的源极选择线SGS0_0至SGS0_j可以根据设计变化而在存储块MB中彼此耦接。另外,在存储块MB的读取操作、编程操作和擦除操作期间施加至存储块MB的操作电压可以根据源极选择线SGS0_0至SGS0_j如何连接而不同。
在存储块层110BL0中,存储块MB的源极选择线SGS0_0至SGS0_j、字线WLA0至WLAn、漏极选择线SGD0_0至SGD0_i以及公共源极线SL可以与另一存储块MB’的源极选择线(未示出)、字线(未示出)、漏极选择线(未示出)以及公共源极线(未示出)分开。换言之,在存储块层110BL0中,各个存储块MB的源极选择线SGS0_0至SGS0_j、字线WLA0至WLAn、漏极选择线SGD0_0至SGD0_i以及公共源极线SL可以彼此分开。
参见图4B,参照图4A描述的两个或更多个存储块层可以层叠。在优选的实施例中,可以层叠四个存储块层110BL0至110BL3。奇数存储块层110BL0或110BL2中包括的存储块或存储串与偶数存储块层110BL1或110BL3中包括的存储块或存储串可以共用位线BLA0至BLAk或BLB0至BLBk或公共源极线SLA、SLB或SLC。换言之,最下层存储块层110BL0和位于其上的存储块层110BL1可以共用下位线BLA0至BLAk。最上层存储块层110BL3和位于其下的存储块层110BL2可以共用上位线BLB0至BLBk。
更具体地,例如,奇数存储块层110BL2可以与位于其上的偶数存储块层110BL3共用位线BLB0至BLBk,而与位于其下的偶数存储块层110BL1共用公共源极线SLB。另外,偶数存储块层110BL1可以与位于其上的奇数存储块层110BL2共用公共源极线SLB,而与位于其下的奇数存储块层110BL0共用位线BLA0至BLAk。因而,位线BLA0至BLAk和位线BLB0至BLBk可以形成在不同的层中,公共源极线SLA、SLB和SLC可以形成在不同的层中。
如上所述,为了使存储块层110BL0至110BL3共用位线BLA0至BLAk和BLB0至BLBk以及公共源极线SLB,可以层叠存储块层110BL0至110BL3,使得奇数存储块层110BL0和110BL2中包括的存储块与偶数存储块层110BL1和110BL3中包括的存储块可以水平对称。
存储块层110BL0至110BL3的字线WLA0至WLAn、WLB0至WLBn、WLC0至WLCn以及WLD0至WLDn可以彼此耦接。换言之,存储块层110BL0至110BL3的字线WLA0至WLAn、WLB0至WLBn、WLC0至WLCn以及WLD0至WLDn可以彼此垂直耦接。垂直层叠的存储块的字线可以彼此垂直耦接,而水平布置的存储块的字线可以彼此分开。存储块层110BL0至110BL3的源极选择线SGS0_0至SGS0_j、SGS1_0至SGS1_j、SGS2_0至SGS2_j以及SGS3_0至SGS3_j可以选择性地彼此耦接。另外,存储块层110BL0至110BL3的漏极选择线SGD0_0至SGD0_i、SGD1_0至SGD1_i、SGD2_0至SGD2_i以及SGD3_0至SGD3_i可以选择性地彼此耦接。存储块层的耦接或连接关系可以根据电压供应电路和读取/写入电路的耦接或连接关系而变化。施加至存储块层110BL0至110BL3的字线WLA0至WLAn、WLB0至WLBn、WLC0至WLCn以及WLD0至WLDn,源极选择线SGS0_0至SGS0_j、SGS1_0至SGS1_j、SGS2_0至SGS2_j和SGS3_0至SGS3_j以及漏极选择线SGD0_0至SGD0_i、SGD1_0至SGD1_i、SGD2_0至SGD2_i以及SGD3_0至SGD3_i的电压可以根据耦接或连接关系而变化。
存储块层110BL0至110BL3可以共用公共源极线SLA至SLC。换言之,存储块层110BL0至110BL3的公共源极线SLA至SLC可以彼此垂直耦接。与字线WLA0至WLAn类似,不同的存储块的公共源极线可以沿着垂直方向耦接,而不沿水平方向耦接。
图5A和图5B是说明根据本发明的一个实施例的半导体器件的截面图。图5A是说明图1中示出的半导体衬底沿着A-A’方向截取的截面图。图5B是图1中示出的半导体衬底沿着B-B’方向截取的截面图。
参见图1、图5A和图5B,形成控制电路的半导体器件(诸如晶体管)、电压供应电路、字线驱动器和输入/输出电路可以形成在半导体衬底100的第一操作电路区120A和第二操作电路区120B、读取/写入电路区120C以及字线驱动器区120D中。换言之,栅极(G)、源极(S)、漏极(D)和结(J)可以形成在半导体衬底100中,且用于建立他们之间的电连接的接触插塞CT和金属线ML可以形成在多个层中。
当形成金属线ML的最上层的一个时,也可以形成内焊盘INNER_PAD组。内焊盘INNER_PAD组可以与其他操作电路以及构成字线驱动器的半导体器件电连接。
存储器阵列110A和110B可以形成在半导体衬底100之上,在所述半导体衬底100之上形成有操作电路。如图4A和图4B中所示,存储器阵列110A和110B可以包括多个存储块,并且所述存储块可以层叠在多个层中。每个存储块可以包括具有如以上参照图2和图3描述的三维结构的存储串。
由第一存储块层110BL0和第二存储块层110BL1共用的下位线BLA以及由第三存储块层110BL2和第四存储块层110BL3共用的上位线BLB可以通过位于存储器阵列110A和110B之间的区域120E中的接触插塞CT和金属线ML而与读取/写入电路区120C中的半导体器件电连接。接触插塞CT可以形成在与存储串ST相同的层中,金属线ML可以形成在与公共源极线SL相同的层中。接触插塞CT和金属线ML可以将上位线BLB和下位线BLA平行地与读取/写入电路耦接,或将上位线BLB和下位线BLA分别与不同的读取/写入电路耦接。
另外,存储块层110BL0至110BL3的字线WL可以通过字线驱动器区中的接触插塞CT和金属线ML与形成字线驱动器的半导体器件耦接。
内焊盘INNER_PAD可以被布置在半导体衬底100的一个边缘之上,且位于存储器阵列110B之下。换言之,内焊盘INNER_PAD可以位于操作电路120A至120D与存储器阵列110A和110B之间的中间层中。
在下文中,描述上述根据本发明的一个实施例的半导体衬底的封装工艺。图6至图14是说明根据本发明的一个实施例的半导体器件的封装工艺的图。
参见图6,可以在以上参照图5A和图5B描述的半导体衬底100之上形成钝化层PL。图5A和图5B中示出的半导体衬底100可以是晶片WAFER中的单个裸片10。晶片WAFER中可以形成多个裸片10。
参见图7,可以将载体衬底CARRIER_SUB附接至晶片WAFER的顶表面,即,附接至形成在每个裸片10中的钝化层PL。载体衬底CARRIER_SUB还可以用作保护晶片WAFER的顶表面的保护板,在所述顶表面上形成有存储器阵列。晶片WAFER可以翻转,以及可以附接至载体衬底CARRIER_SUB。在载体衬底CARRIER_SUB附接至晶片WAFER之后,可以将晶片WAFER翻转。
参见图8和图9,当翻转晶片WAFER时,半导体衬底100可以位于载体衬底CARRIER_SUB之上。为了减小半导体衬底100的厚度,可以刻蚀位于载体衬底CARRIER_SUB之上的半导体衬底100的底表面。换言之,可以刻蚀晶片WAFER的整个底表面。可以通过化学机械抛光工艺来刻蚀晶片WAFER或半导体衬底100的底表面。可以在后续工艺期间执行用于在晶片WAFER或半导体衬底100中形成接触孔130的刻蚀工艺。当晶片WAFER或半导体衬底100的厚度减小时,可以顺利地执行形成接触孔130的刻蚀工艺。
在刻蚀半导体衬底100的底表面之后,可以在半导体衬底100的整个底表面上形成绝缘层D_LAYER。绝缘层D_LAYER可以形成在晶片WAFER的整个底表面之上,且可以包括氧化物层。
接下来,可以刻蚀绝缘层D_LAYER和晶片WAFER以暴露出形成在相应的裸片10中的内焊盘INNER_PAD。结果,接触孔130可以形成为穿过晶片WAFER。可以在翻转晶片WAFER时执行在晶片WAFER中形成接触孔130的工艺。晶片WAFER可以被载体衬底CARRIER_SUB支撑。
在接触孔130的侧壁上形成电介质薄膜(未示出)以防止要形成在接触孔130中的导电材料和半导体衬底100之间的电接触或物理接触。通常通过反应离子刻蚀(RIE)工艺和电介质材料的沉积工艺制造电介质薄膜。
参见图10至图12,可以在接触孔130中形成阻挡金属层140B,以及可以用导电层填充接触孔130。阻挡金属层140B可以包括钛层、氮化钛层、或包括钛层和氮化钛层的多层结构。形成接触插塞140C的导电层可以包括铜或钨。可以在接触孔130中形成包括导电层的接触插塞140C,使得接触插塞140C可以接触内焊盘INNER_PAD。可以通过接触插塞140C和阻挡金属层140B来形成接线结构140。接下来,可以在包括接线结构140的绝缘层D_LAYER上形成包括外焊盘OUTER_PAD的外焊盘组。
在接触插塞140C或外焊盘OUTER_PAD的形成期间,可以在另一个区域中另外地形成:用于形成与操作电路120A耦接的接触插塞的导电层140L和140M、与所述接触插塞耦接的另外的焊盘、以及用于将所述另外的焊盘与外焊盘OUTER_PAD耦接的接线。导电层140L和140M可以起到将各种电源供应至操作电路的金属线的作用。
结果,经由接线结构140与内焊盘INNER_PAD耦接的外焊盘OUTER_PAD可以形成在晶片WAFER或半导体衬底100的底表面上。
参见图13,每个裸片10可以与晶片WAFER分开,且每个裸片10可以附接至电路板CB_SUB。第一裸片10可以翻转且附接至电路板CB_SUB,使得可以在裸片10的顶表面暴露出外焊盘OUTER_PAD。因此,裸片10的载体衬底CARRIER_SUB可以接触电路板CB_SUB。
裸片10的外焊盘OUTER_PAD可以通过诸如线WB的连接构件与电路板CB_SUB的金属线CB_ML耦接。
内焊盘INNER_PAD可以形成在半导体衬底和存储器阵列之间,并且内焊盘INNER_PAD可以经由接线结构140、外焊盘OUTER_PAD和线WB与电路板CB_SUB耦接。因此,内焊盘INNER_PAD可以在不影响形成存储器阵列的面积的情况下与电路板CB_SUB耦接。因此,在半导体衬底的预定空间内可以增加形成存储器阵列的面积。结果,形成在半导体衬底中的存储器单元的数量可以增加,以及数据储存容量可以增加。
参见图14,当多个半导体衬底或裸片10层叠在电路板CB_SUB之上时,可以翻转裸片10。换言之,可以将裸片10层叠在电路板CB_SUB之上,使得形成在半导体衬底100的底表面上的绝缘层D_LAYER可以位于形成在半导体衬底100的顶表面上的保护板或载体衬底CARRIER_SUB之上。结果,在半导体衬底100底下的绝缘层D_LAYER与在半导体衬底100顶上的保护板或载体衬底CARRIER_SUB可以彼此面对。另外,半导体衬底100或裸片10可以彼此偏离以暴露出外焊盘OUTER_PAD。
层叠的半导体衬底100或裸片10的外焊盘OUTER_PAD可以通过诸如线WB的耦接构件与电路板CB_SUB的金属线CB_ML耦接。
在下文中,以下描述根据另一个实施例的半导体衬底的封装工艺。图15至图22是说明根据本发明的另一个实施例的半导体器件的封装工艺的图。
参见图15,可以提供以上参照图5A和图5B描述的半导体衬底100。换言之,可以在焊盘区中在存储器阵列110B之下形成内焊盘INNER_PAD1。另外,还可以在第一操作电路区中在存储器阵列110A之下形成内焊盘INNER_PAD2和INNER_PAD3。
可以在形成有内焊盘INNER_PAD1至INNER_PAD3的半导体衬底100上形成钝化层PL。半导体衬底100可以是晶片WAFER中的单个裸片10。晶片WAFER中可以形成多个裸片10。
参见图16,可以将载体衬底CARRIER_SUB附接至晶片WAFER的顶表面,即,附接至形成在每个裸片10中的钝化层PL。载体衬底CARRIER_SUB还可以用作用于保护晶片WAFER的形成有存储器阵列的顶表面的保护板。晶片WAFER可以翻转且可以附接至载体衬底CARRIER_SUB。在载体衬底CARRIER_SUB附接至晶片WAFER之后,可以翻转晶片WAFER。
参见图17和图18,可以执行以上参照图8和图9描述的工艺。换言之,为了减小晶片WAFER或半导体衬底100的厚度,可以刻蚀晶片WAFER或半导体衬底100的整个底表面。在刻蚀工艺之后,可以在晶片WAFER的整个底表面或半导体衬底100之上形成绝缘层D_LAYER。
接下来,可以刻蚀绝缘层D_LAYER和晶片WAFER以暴露出形成在每个裸片10上的内焊盘INNER_PAD1至INNER_PAD3。结果,可以在晶片WAFER的每个裸片10中形成穿过半导体衬底100而形成的接触孔130A至130C。
参见图19至图21,可以在接触孔130A至130C中形成阻挡金属层140B,以及可以在接触孔130A至130C中形成接触插塞140C1。接触插塞140C1可以接触内焊盘INNER_PAD1至INNER_PAD3。
可以在形成有接触插塞140C1的晶片WAFER上形成多层金属线140L1和140C2。结果,接线结构140可以包括接触插塞140C1以及多层金属线140L1和140C2。
接下来,可以在包括接线结构140的绝缘层D_LAYER上形成包括外焊盘OUTER_PAD的外焊盘组。在形成外焊盘OUTER_PAD期间,可以在另一个区域中另外地形成用于形成线或焊盘的导电层140L2和140P。导电层140L2和140P还可以被包括在多层线140中。因此,外焊盘OUTER_PAD可以与多层金属线140L1、140C2、140L2以及140P之中的最上层金属线140L2耦接。导电层140L2和140P可以起到将各种电源供应至操作电路的金属线的作用。
在接线结构中,接触插塞140C1可以包括铜或钨。多层金属线140L1、140L2和140P可以包括铝。与多层金属线140L1、140L2和140P垂直耦接的插塞140C2可以包括铝或铜。
可以在900℃或更高的温度执行退火以增加三维结构的存储串中包括的垂直沟道的晶粒尺寸,从而增加单元电流。然而,在完成包括高温退火的制造半导体器件的工艺之后,可以经由穿通硅通孔(TSV)工艺使用铜或铝来形成接线结构140,使得可以防止接线结构140被损坏。
还可以在晶片WAFER的形成有外焊盘OUTER_PAD的底表面上形成包括接触孔的绝缘层D_LAYER,经由所述接触孔暴露出外焊盘OUTER_PAD。
参见图22,每个裸片10可以在晶片WAFER中彼此分开,且图19中所示的裸片10可以附接至电路板CB_SUB。每个裸片10可以翻转,且附接至电路板CB_SUB,使得可以在其顶部暴露出外焊盘OUTER_PAD。结果,半导体衬底100底下的绝缘层D_LAYER与半导体衬底100的保护板或载体衬底CARRIER_SUB可以彼此面对。另外,半导体衬底100或裸片10可以彼此偏移以暴露出外焊盘OUTER_PAD。裸片10的外焊盘OUTER_PAD可以通过诸如线WB的连接构件与电路板CB_SUB的金属线CB_ML耦接。
在下文中,以下描述根据另一个实施例的半导体衬底的封装工艺。图23和图24是说明根据本发明的另一个实施例的半导体器件的封装工艺的图。
参见图23,在形成如以上参照图10或图19描述的接线结构140之后形成外焊盘时,还可以形成其他外焊盘。其详细描述如下。
如在图10或图19中所示,在将接线结构140形成在半导体衬底100之后,可以在半导体衬底100上形成经由接线结构140与内焊盘耦接的第一外焊盘OUTER_PAD1。还可以形成与第一外焊盘OUTER_PAD1相同的第二外焊盘OUTER_PAD2。另外,还可以形成将第一外焊盘OUTER_PAD1与第二外焊盘OUTER_PAD2电耦接的金属线140L3。第二外焊盘OUTER_PAD2可以形成为与另一个半导体衬底100耦接,而不与电路板CB_SUB耦接。
参见图24,可以在电路板CB_SUB之上层叠包括参照图23描述的第一外焊盘OUTER_PAD1和第二外焊盘OUTER_PAD2的裸片10_O和10_E。参照图23描述的半导体衬底100可以是裸片10_O和10_E。可以仅将奇数层中的裸片10_O翻转,使得半导体衬底100的形成有外焊盘OUTER_PAD1和OUTER_PAD2的底表面可以位于其顶部。
奇数层中的裸片10_O和偶数层中的裸片10_E可以层叠且彼此偏移,使得奇数层中的裸片10_O的第二外焊盘组OUTER_PAD2和位于奇数层中的裸片10_O上的偶数层中的裸片10_E的第一外焊盘组OUTER_PAD1可以彼此面对。结果,奇数层中的裸片10_O的第二外焊盘组OUTER_PAD2和位于奇数层中的裸片10_O上的偶数层中的裸片10_E的第一外焊盘组OUTER_PAD1可以通过连接构件SB而彼此耦接。
奇数层中的裸片10_O的第一外焊盘组OUTER_PAD1可以与电路板CB_SUB的金属线CB_ML通过诸如线WB的连接构件耦接。偶数层中的裸片10_E的第一外焊盘组OUTER_PAD1可以经由奇数层中的裸片10_O的第二外焊盘组OUTER_PAD2、图23中所示的金属线140L3以及第一外焊盘组OUTER_PAD1与线WB电耦接。
如上所述,可以仅将奇数层中的裸片10_O翻转,奇数层和偶数层中的裸片10_O和10_E可以利用第一外焊盘OUTER_PAD1和第二外焊盘OUTER_PAD2与电路板CB_SUB的金属线CB_ML电连接,使得即使层叠裸片的数量增加,也可以防止芯片尺寸的增加。
在下文中,描述根据本发明的一个实施例的半导体衬底的封装工艺。图25和图26是说明根据本发明的一个实施例的半导体器件的封装工艺的图。
参见图25,在形成接线结构140之后形成外焊盘OUTER_PAD1时,如在图10或图19中所示,还可以形成其他外焊盘OUTER_PAD2和OUTER_PAD3。其详细描述如下。
如以上参见图10或图19所述,在将接线结构140形成在半导体衬底100之上之后,可以在半导体衬底100之上形成经由接线结构140与内焊盘INNER_PAD耦接的第一外焊盘OUTER_PAD1。还可以形成与第一外焊盘OUTER_PAD1相同的第二外焊盘OUTER_PAD2和第三外焊盘OUTER_PAD3。另外,还可以形成用于将外焊盘OUTER_PAD1至OUTER_PAD3电耦接的金属线140L3。可以形成第二外焊盘OUTER_PAD2和第三外焊盘OUTER_PAD3以建立与其他半导体衬底100而非电路板CB_SUB的电连接。
参见图26,可以在电路板CB_SUB之上层叠参照图25描述的包括第一外焊盘OUTER_PAD1至第三外焊盘OUTER_PAD3的裸片10_O、10_O’、10_E和10_E’。参照图25描述的半导体衬底100可以是裸片10_O、10_O’、10_E和10_E’。可以在奇数层或偶数层中形成两个或更多个裸片10_O、10_O’、10_E和10_E’。另外,可以将奇数层中的裸片10_O和10_O’翻转,使得半导体衬底100的形成有外焊盘OUTER_PAD1和OUTER_PAD2的底表面可以位于奇数层中的裸片10_O和10_O’的顶部。
奇数层中的裸片10_O和偶数层中的裸片10_E可以层叠且彼此偏移,使得奇数层中的裸片10_O的第二外焊盘组OUTER_PAD2和位于奇数层中的裸片10_O上的偶数层中的裸片10_E的第一外焊盘组OUTER_PAD1可以彼此面对。另外,奇数层中的裸片10_O’和偶数层中的裸片10_E可以彼此偏移,使得奇数层中的裸片10_O’的第一外焊盘组OUTER_PAD1和位于奇数层中的裸片10_O’上的偶数层中的裸片10_E的第三外焊盘组OUTER_PAD3可以彼此面对。另外,奇数层中的裸片10_O’和偶数层中的裸片10_E’可以彼此偏移,使得奇数层中的裸片10_O’的第二外焊盘组OUTER_PAD2和位于奇数层中的裸片10_O’上的偶数层中的裸片10_E’的第一外焊盘组OUTER_PAD1可以彼此面对。
结果,奇数层中的裸片10_O的第二外焊盘组OUTER_PAD2和偶数层中的裸片10_E的第一外焊盘组OUTER_PAD1可以通过连接构件SB彼此耦接。另外,奇数层中的裸片10_O’的第一外焊盘组OUTER_PAD1和偶数层中的裸片10_E的第三外焊盘组OUTER_PAD3可以通过连接构件SB彼此耦接。另外,奇数层中的裸片10_O’的第二外焊盘组OUTER_PAD2和偶数层中的裸片10_E’的第一外焊盘组OUTER_PAD1可以通过连接构件SB彼此耦接。如上所述,裸片、例如裸片10_O’可以经由第一外焊盘组OUTER_PAD1至第三外焊盘组OUTER_PAD3中的两个而与位于其上或其下的两个裸片10_E和10_E’电连接。
奇数层中的裸片10_O的第一外焊盘组OUTER_PAD1可以通过诸如线WB的连接构件与电路板CB_SUB的金属线CB_ML耦接。偶数层中的裸片10_E的第一外焊盘组OUTER_PAD1可以分别经由第二外焊盘组OUTER_PAD2、图23中示出的金属线140L3以及奇数层中的裸片10_O的第一外焊盘组OUTER_PAD1与线WB电连接。
奇数层中的裸片10_O’的第一外焊盘组OUTER_PAD1可以经由偶数层中的裸片10_E的外焊盘组OUTER_PAD1至OUTER_PAD3、奇数层中的裸片10_O的第一外焊盘组OUTER_PAD1和第二外焊盘组OUTER_PAD2以及线WB与电路板CB_SUB的金属线CB_ML耦接。偶数层中的裸片10_E’的第一外焊盘组OUTER_PAD1可以经由奇数层中的裸片10_O’的第一外焊盘组OUTER_PAD1和第二外焊盘组OUTER_PAD2、偶数层中的裸片10_E的外焊盘组OUTER_PAD1至OUTER_PAD3、奇数层中的裸片10_O的第一外焊盘组OUTER_PAD1和第二外焊盘组OUTER_PAD2以及线WB与电路板CB_SUB的金属线CB_ML耦接。
换言之,线WB可以将奇数层中的裸片10_O的第一外焊盘OUTER_PAD1与电路板CB_SUB的金属线CB_ML耦接,并且其他裸片10_O'、10_E和10_E’的第一外焊盘OUTER_PAD1可以经由其他裸片的外焊盘与线WB耦接。
如上所述,由于每层中布置有多个裸片,仅将奇数层中的裸片10_O翻转,并且奇数层和偶数层中的裸片10_O、10_E、10_O’和10_E’利用第一外焊盘OUTER_PAD1至第三外焊盘OUTER_PAD3与电路板CB_SUB的金属线CB_ML电耦接,即使层叠裸片的数量增加,也可以进一步防止芯片尺寸的增加。
图27是说明根据本发明的一个实施例的存储系统的示意框图。
如在图27中所示,根据本发明的一个实施例的存储系统2700可以包括非易失性存储器件2720和存储器控制器2710。
非易失性存储器件2720可以包括上述半导体存储器。存储器控制器2710可以在诸如编程循环、读取操作或擦除循环的一般操作模式中控制非易失性存储器件2720。
存储器控制器2710可以是组合有非易失性存储器件2720和存储器控制器2710的固态盘(SSD)或存储卡。SRAM 2711可以起到处理单元2712的操作存储器的作用。主机接口2713可以包括与存储系统2700耦接的主机的数据交换协议。错误校正块2714可以检测且校正从非易失性存储器件2720读取的数据中包括的错误。存储器接口2714可以与非易失性存储器件2720接口。处理单元2712可以执行用于存储器控制器2710的数据交换的一般控制操作。
尽管在图27中未示出,但是存储系统2700还可以包括储存用于与主机接口的码数据的ROM(未示出)。另外,非易失性存储器件2720可以是由多个快闪存储芯片组成的多芯片封装体。具有上述配置的存储系统2700可以被提供作为具有高可靠性和低错误率的储存媒介。当在存储系统、诸如已进行积极研究的半导体盘器件(固态盘(SSD))中提供根据本发明的一个实施例的快闪存储器件时,存储器控制器2710可以经由诸如USB、MMC、PCI-E、SATA、PATA、SCSI、ESDI和IDE的各种接口协议之一与外部设备(例如,主机)通信。
图28是说明根据之前描述的实施例的执行编程操作的融合式存储器件或融合式存储系统的示意性框图。例如,本发明的技术特征可以应用至OneNAND(一体式NAND)快闪存储器件2800作为融合式存储器件。
OneNAND快闪存储器件2800可以包括主机接口(I/F)2810、缓冲器RAM 2820、控制器2830、寄存器2840和NAND快闪单元阵列2850。主机接口2810可以使用不同的协议与设备交换各种类型的信息。缓冲器RAM 2820可以加载有用于驱动存储器件的码或暂时储存数据。控制器2830可以响应于外部给予的控制信号和命令而在每个状态中控制读取和编程操作。寄存器2840可以储存包括指令、地址和定义存储器件中的系统操作环境的配置的数据。NAND快闪单元阵列2850可以包括操作电路,所述操作电路包括非易失性存储器单元和页缓冲器。在图4A和图4B中示出的存储器阵列可以被应用作为NAND快闪单元阵列2850的存储器阵列。
图29是说明包括快闪存储器件2912的计算系统的示意图。
根据本发明的一个实施例的计算系统2900可以包括微处理器2920、RAM 2930、用户接口2940、诸如基带芯片组的调制解调器2950、以及与系统总线2960电耦接的存储系统2910。另外,当计算系统2900是移动设备时,还可以包括电池(未示出)以将操作电压施加至计算系统2900。尽管在图29中未示出,但是计算系统2900还可以包括应用芯片组、照相机图像处理器(CIS)以及移动DRAM。存储系统2910可以形成使用非易失性存储器件的固态驱动/盘(SSD)以储存数据。可替选地,存储系统2910可以提供作为融合式存储快闪存储器(例如,OneNAND快闪存储器)。
根据本发明,形成在半导体衬底上的存储器单元的数量可以增加,以及半导体芯片根据层叠半导体衬底的数量的尺寸增长可以减小。
对于本领域技术人员将清楚的是,本发明的以上示例性实施例可以通过程序或记录程序的记录媒介来实施,所述程序或记录媒介被配置成执行与实施例以及本文中公开的器件和方法的构成相对应的功能。
尽管已经参照某些示例性实施例描述了本发明,但本领域技术人员将理解的是,在不脱离所附权利要求书中限定的本发明的精神或范围及其等同形式的情况下,可以对本发明进行各种修改和变化。
通过以上实施例可以看出,本申请提供了以下的技术方案。
技术方案1.一种半导体器件,包括:
操作电路,其形成在半导体衬底的顶表面上;
存储器阵列,其形成在所述操作电路之上;
内焊盘组,其形成在所述操作电路和所述存储器阵列之间,且与所述操作电路耦接;
第一外焊盘组,其形成在所述半导体衬底的底表面上;以及
接线结构,其穿过所述半导体衬底,且将所述内焊盘组与所述第一外焊盘组耦接。
技术方案2.如技术方案1所述的半导体器件,还包括保护板,其形成在所述存储器阵列之上,且附接至所述半导体衬底。
技术方案3.如技术方案1所述的半导体器件,还包括绝缘层,所述绝缘层形成在所述半导体衬底的底表面上,
其中,所述第一外焊盘组形成在所述绝缘层的表面上。
技术方案4.如技术方案1所述的半导体器件,其中,所述内焊盘组位于所述存储器阵列之下。
技术方案5.如技术方案1所述的半导体器件,其中,所述接线结构包括:
插塞,其穿过所述半导体衬底以将所述内焊盘组与所述第一外焊盘组耦接;以及
形成与所述操作电路耦接的接触插塞的导电层、与所述接触插塞耦接的另外的焊盘、以及将所述另外的焊盘与所述第一外焊盘组耦接的接线。
技术方案6.如技术方案1所述的半导体器件,其中,所述接线结构包括:
第一插塞,其与所述内焊盘组耦接,且穿过所述半导体衬底;以及
多层金属线,其形成在所述半导体衬底的底表面上,且与所述第一插塞电连接,
其中,所述第一外焊盘组与所述多层金属线之中的最上层金属线耦接。
技术方案7.如技术方案6所述的半导体器件,其中,所述第一插塞包括铜或钨,
所述多层金属线包括铝,以及
所述多层金属线通过包括铝或铜的第二插塞而垂直耦接。
技术方案8.如技术方案6所述的半导体器件,还包括第二外焊盘组,所述第二外焊盘组形成在所述半导体衬底的底表面上以建立与另一个半导体衬底的电连接,
其中,所述第二外焊盘组与所述第一外焊盘组电耦接。
技术方案9.如技术方案8所述的半导体器件,还包括第三外焊盘组,所述第三外焊盘组形成在所述半导体衬底的底表面上以建立与另一个半导体衬底的电连接,
其中,所述第三外焊盘组与所述第一外焊盘组或所述第二外焊盘组电耦接。
技术方案10.一种半导体器件,包括:
电路板;
半导体衬底,在每个半导体衬底中,内焊盘组和存储器阵列顺序地层叠在所述半导体衬底的顶表面上,并且外焊盘组形成在所述半导体衬底的底表面上;
接线结构,其分别形成在所述半导体衬底中,其中,每个接线结构穿过每个半导体衬底以将所述内焊盘组与所述外焊盘组耦接;以及
连接构件,每个连接构件将所述电路板与每个半导体衬底的外焊盘组耦接,
其中,所述半导体衬底翻转且层叠在所述电路板上。
技术方案11.如技术方案10所述的半导体器件,还包括:
保护板,其附接至所述半导体衬底的顶表面;以及
绝缘层,其形成在所述半导体衬底的底表面上,
其中,所述外焊盘组形成在所述绝缘层的表面上。
技术方案12.如技术方案11所述的半导体器件,其中,分别位于所述半导体衬底的顶部和底部的所述绝缘层和所述保护板彼此面对。
技术方案13.如技术方案10所述的半导体器件,其中,所述半导体衬底层叠且彼此偏移,使得暴露出每个半导体衬底的外焊盘组。
技术方案14.如技术方案10所述的半导体器件,其中,每个接线结构包括:
插塞,其穿过所述半导体衬底且与所述内焊盘组耦接;以及
形成与所述操作电路耦接的接触插塞的导电层、与所述接触插塞耦接的另外的焊盘、以及将所述另外的焊盘与所述外焊盘组耦接的接线。
技术方案15.一种半导体器件,包括:
电路板;
半导体衬底,在每个半导体衬底中,内焊盘组和存储器阵列顺序地层叠在所述半导体衬底的顶表面上,并且第一外焊盘组和第二外焊盘组在所述半导体衬底的底表面上彼此电耦接,其中,所述半导体衬底层叠在所述电路板上;
接线结构,其穿过所述半导体衬底,使得每个半导体衬底的内焊盘组与所述半导体衬底的第一外焊盘组耦接,其中,每个接线结构形成在每个半导体衬底中;以及
连接构件,每个连接构件将所述电路板与奇数层中的每个半导体衬底的第一外焊盘组耦接,
其中,所述奇数层中的半导体衬底翻转且层叠。
技术方案16.如技术方案15所述的半导体器件,其中,所述奇数层中的半导体衬底和偶数层中的半导体衬底层叠且彼此偏移,使得所述奇数层中的半导体衬底的第二外焊盘组和位于所述奇数层中的半导体衬底上的所述偶数层中的半导体衬底的第一外焊盘组彼此面对。
技术方案17.如技术方案15所述的半导体器件,其中,所述奇数层中的半导体衬底的第二外焊盘组和位于所述奇数层中的半导体衬底上的所述偶数层中的半导体衬底的第一外焊盘组彼此耦接。
技术方案18.如技术方案15所述的半导体器件,其中,在所述奇数层和所述偶数层中的每个中布置两个或更多个半导体衬底。
技术方案19.如技术方案18所述的半导体器件,还包括第三外焊盘组,所述第三外焊盘组形成在所述半导体衬底的底表面上,并且与所述第一外焊盘组或所述第二外焊盘组电连接。
技术方案20.如技术方案19所述的半导体器件,其中,所述半导体衬底经由所述第一外焊盘组至所述第三外焊盘组中的两个与位于所述半导体衬底上或所述半导体衬底下的两个半导体衬底电耦接。
Claims (10)
1.一种半导体器件,包括:
操作电路,其形成在半导体衬底的顶表面上;
存储器阵列,其形成在所述操作电路之上;
内焊盘组,其形成在所述操作电路和所述存储器阵列之间,且与所述操作电路耦接;
第一外焊盘组,其形成在所述半导体衬底的底表面上;以及
接线结构,其穿过所述半导体衬底,且将所述内焊盘组与所述第一外焊盘组耦接。
2.如权利要求1所述的半导体器件,还包括保护板,其形成在所述存储器阵列之上,且附接至所述半导体衬底。
3.如权利要求1所述的半导体器件,还包括绝缘层,所述绝缘层形成在所述半导体衬底的底表面上,
其中,所述第一外焊盘组形成在所述绝缘层的表面上。
4.如权利要求1所述的半导体器件,其中,所述内焊盘组位于所述存储器阵列之下。
5.如权利要求1所述的半导体器件,其中,所述接线结构包括:
插塞,其穿过所述半导体衬底以将所述内焊盘组与所述第一外焊盘组耦接;以及
形成与所述操作电路耦接的接触插塞的导电层、与所述接触插塞耦接的另外的焊盘、以及将所述另外的焊盘与所述第一外焊盘组耦接的接线。
6.如权利要求1所述的半导体器件,其中,所述接线结构包括:
第一插塞,其与所述内焊盘组耦接,且穿过所述半导体衬底;以及
多层金属线,其形成在所述半导体衬底的底表面上,且与所述第一插塞电连接,
其中,所述第一外焊盘组与所述多层金属线之中的最上层金属线耦接。
7.如权利要求6所述的半导体器件,其中,所述第一插塞包括铜或钨,
所述多层金属线包括铝,以及
所述多层金属线通过包括铝或铜的第二插塞而垂直耦接。
8.如权利要求6所述的半导体器件,还包括第二外焊盘组,所述第二外焊盘组形成在所述半导体衬底的底表面上以建立与另一个半导体衬底的电连接,
其中,所述第二外焊盘组与所述第一外焊盘组电耦接。
9.一种半导体器件,包括:
电路板;
半导体衬底,在每个半导体衬底中,内焊盘组和存储器阵列顺序地层叠在所述半导体衬底的顶表面上,并且外焊盘组形成在所述半导体衬底的底表面上;
接线结构,其分别形成在所述半导体衬底中,其中,每个接线结构穿过每个半导体衬底以将所述内焊盘组与所述外焊盘组耦接;以及
连接构件,每个连接构件将所述电路板与每个半导体衬底的外焊盘组耦接,
其中,所述半导体衬底翻转且层叠在所述电路板上。
10.一种半导体器件,包括:
电路板;
半导体衬底,在每个半导体衬底中,内焊盘组和存储器阵列顺序地层叠在所述半导体衬底的顶表面上,并且第一外焊盘组和第二外焊盘组在所述半导体衬底的底表面上彼此电耦接,其中,所述半导体衬底层叠在所述电路板上;
接线结构,其穿过所述半导体衬底,使得每个半导体衬底的内焊盘组与所述半导体衬底的第一外焊盘组耦接,其中,每个接线结构形成在每个半导体衬底中;以及
连接构件,每个连接构件将所述电路板与奇数层中的每个半导体衬底的第一外焊盘组耦接,
其中,所述奇数层中的半导体衬底翻转且层叠。
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KR102589301B1 (ko) | 2016-04-29 | 2023-10-13 | 삼성전자주식회사 | 비휘발성 메모리 장치 |
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CN113964102A (zh) | 2019-11-29 | 2022-01-21 | 长江存储科技有限责任公司 | 芯片封装结构及其制造方法 |
CN114121082A (zh) * | 2020-08-26 | 2022-03-01 | 长鑫存储技术(上海)有限公司 | 传输电路、接口电路以及存储器 |
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CN104882431B (zh) | 2019-08-27 |
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