CN104871249A - 数据存储系统的自适应错误纠正码 - Google Patents

数据存储系统的自适应错误纠正码 Download PDF

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CN104871249A
CN104871249A CN201380067610.7A CN201380067610A CN104871249A CN 104871249 A CN104871249 A CN 104871249A CN 201380067610 A CN201380067610 A CN 201380067610A CN 104871249 A CN104871249 A CN 104871249A
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G·陆
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    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields

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Abstract

本发明公开了一种被配置为自适应地编码数据的数据存储系统，在一个实施例中，数据存储系统控制器确定非易失性存储器阵列的共同的存储器页大小，例如，E页大小。基于所述共同的存储器页大小，所述控制器从多个预定义的低密度奇偶校验(LDPC)码字长中选择LDPC码字长。所述控制器基于所选择的LDPC码字长来确定用于对写入到所述存储器阵列的数据或从所述存储器阵列读取的数据进行编码的LDPC编码参数。通过使用所述多个预定义的LDPC码字长，所述数据存储系统能够支持多个非易失性存储器页格式，包括这样的存储器页格式：其中所述共同的存储器页大小不等于所述多个预定义的LDPC码字长中的任何LDPC码字长。从而能够获得数据编码的灵活性和高效性。

Description

数据存储系统的自适应错误纠正码
技术领域
本公开涉及计算机系统的诸如固态硬盘等的数据存储系统。更具体地，本公开涉及数据存储系统的自适应错误纠正码。
背景技术
非易失性存储器阵列常常具有有限的耐久性。存储器阵列的耐久性通常视使用模式和磨损而定。另外，耐久性取决于非易失性存储器阵列的特定类型。例如，与具有单层单元(SLC)NAND介质的存储器阵列相比，具有多层单元(MLC)NAND介质的存储器阵列通常具有较低的耐久性。为了保护存储到存储器阵列的用户数据免于可能由减少的耐久性而导致的讹误，能够确定奇偶校验数据并且将奇偶校验数据与用户数据一起存储以便于错误检测和/或错误纠正。
附图说明
现在参考下面的附图对实施本发明的各种特征的系统和方法进行描述，其中：
图1示出了根据本发明的一个实施例的自适应地编码数据的存储系统。
图2是示出了根据本发明的一个实施例的确定用于编码数据的编码参数的过程的流程图。
图3是示出了根据本发明的一个实施例的低密度奇偶校验(LDPC)编码参数与LDPC码字长之间关系的表。
图4A-4C是示出了根据本发明的一个实施例的已填充用户数据和奇偶校验数据的图。
图5是示出了根据本发明的一个实施例的自适应码缩短的过程的流程图。
图6是示出了根据本发明的一个实施例的调整码率的过程的流程图。
具体实施方式
尽管描述了某些实施例，但是这些实施例仅以示例的方式给出，而不是要限制保护范围。实际上，本文所描述的新颖方法和系统可以以多种其他形式来实施。而且，可以进行本文所描述的方法和系统的形式上的各种省略、替换和改变，而不会脱离保护范围。
在一些实施例中，本公开中所使用的“编码”数据指的是编码数据的过程和/或解码数据的过程。
概述
诸如固态硬盘等的存储系统通常包括与非易失性存储器阵列耦合的一个或多个控制器。通常，这些控制器由一方设计/制造而非易失性存储器阵列由另一方设计/制造。另外，来自不同制造商的存储器阵列往往具有不同的内部格式，包括不同的存储器页格式，其中每个存储器页格式对应于多个存储器页大小中的一个。而且，由于成本和多种其他竞争原因，存储系统制造商通常使用来自不同的制造商的存储器阵列。例如，存储系统制造商可能在当前生产周期中使用一种品牌的存储器阵列，而在下一个生产周期中使用另一种品牌的存储器阵列。此外，对于标价在不同的水平的不同的存储系统型号可以使用不同的存储器阵列。
因此，常见的设计方法是：令存储系统包括一个或多个控制器，所述一个或多个控制器具有多个专用的硬件、固件和/或软件以用于对从来自不同制造商的存储器阵列读取的数据或写入到来自不同制造商的存储器阵列的数据进行编码/解码，而实际使用的这些硬件、固件和/或软件的子集取决于在装配时或在最终设计阶段与(多个)控制器配对的实际存储器阵列。结果是，存储系统可能包括多个控制器或额外的、不使用的硬件、固件和/或软件以支持未包括在最终装配的存储系统中的一个或多个存储器阵列的多个存储器页格式。
替代地，为减少包括在存储系统中的硬件、固件和/或软件的数量，能够将存储系统和控制器构建为仅支持一个特定的、已知的、具有已知的存储器页大小的存储器页格式，而不支持其他存储器页格式。然而，这样的方法限制了存储系统和控制器对其他类型的存储器阵列的可用性，并且可能需要构建多个不同的存储系统和控制器以支持多个存储器阵列类型。另外，在一些实例中，在设计/构建存储系统和控制器时，可能不知道存储器阵列的存储器页格式。因此，期望有针对多个已知或未知的存储器存储格式自适应地编码数据的改善的系统和方法。
在本发明的一些实施例中，存储系统包括控制器和非易失性存储器阵列，非易失性存储器阵列具有多个存储器页，多个存储器页具有共同的存储器页大小。控制器确定非易失性存储器阵列的共同的存储器页大小，并且基于该共同的存储器页大小从多个预定义的码字长中选择码字长，例如低密度奇偶校验(LDPC)码字长。通过选择性地使用适当的码字长(从多个预定义的码字长中选择)和对应的编码参数，控制器使用至少一些共同的硬件、固件和/或软件来支持多个已知的或未知的存储器页格式。因而，控制器能够选择性地调节其操作，所以控制器能够与不同制造商所制造的不同格式的存储器阵列配对。
在一些实施例中，随着部分地由于存储器阵列的使用而引起存储器页、块或非易失性存储器阵列的管芯老化和/或逐渐耗尽，存储设备的控制器调整用于编码用户数据的编码参数。调整编码参数的机制使控制器能够支持随着时间推移每单元数据的附加奇偶校验，从而随着存储器阵列的质量(例如，数据保持能力)降低而改善错误纠正或错误检测能力。此外，调整编码参数的机制便于平衡由每单元数据的附加奇偶校验所引起的解码时间与由附加奇偶校验数据所引起的错误纠正或错误检测益处。另外，控制器能够存储针对存储器页、块或存储器阵列的管芯所调整的编码参数，以准许不同的码率或奇偶校验率适于不同的存储器页、块或管芯。
系统概述
图1示出了根据本发明的一个实施例的自适应地编码数据的存储系统120。如所示出的，存储系统120(例如，混合硬盘、固态硬盘等)包括控制器130和非易失性存储器阵列140，非易失性存储器阵列140包括一个或多个存储块，标识为块“A”142一直到块“N”。每个块包括多个闪存页(F页)。例如，图1中的块A 142包括多个F页，标识为F页A 153、F页B一直到F页N。在一些实施例中，每个“F页”是在非易失性存储器阵列140中能够在单个操作中或作为单元来编程的存储单元的最小组。此外，每个F页包括多个错误纠正码页(E页)。在所示出的实施例中，每个F页包括被示出为四个方框的四个E页，包括E页144。其他实施例可以采用以不同方式定义的F页或E页，或者每个F页可以包括多于或少于四个E页。
控制器130可以从主机系统110中的存储接口模块112(例如，设备驱动)接收数据和/或存储访问命令。由存储接口112所传送的存储访问命令能够包括由主机系统110所发布的写入命令和读取命令。命令能够指定存储系统120中的逻辑块地址，并且控制器130能够在非易失性存储器阵列140中执行所接收的命令。在混合硬盘中，除了非易失性存储器阵列140外，数据还可以存储在磁介质存储部件(图1中未示出)中。
存储系统120能够存储从主机系统110接收的数据，以使得存储系统120能够充当主机系统110的存储装置。为了便于该功能，控制器130能够实施逻辑接口。逻辑接口能够以其中能够存储数据的一组逻辑地址(例如，连续地址)的形式向主机系统110呈现存储系统存储器。在内部，控制器130能够将逻辑地址映射到非易失性存储器阵列140和/或其他(多个)存储器模块中的多种物理存储器地址。
控制器130包括编码器模块132。在一个实施例中，编码器模块132确定编码参数以用于对从非易失性存储器阵列140中的存储器页(例如，E页)读取的数据(例如，用户数据)或写入到存储器页的数据进行解码/编码。编码参数能够用于：对从非易失性存储器阵列140读取的用户数据进行解码，对存储到非易失性存储器阵列140的用户数据进行编码，以及诸如错误检测或错误纠正等的其他用途。编码参数能够包括LDPC编码参数，例如，G或H编码矩阵的列权值、G或H编码矩阵的行权值、P矩阵大小(例如，其中P矩阵是G或H编码矩阵的子矩阵)等。此外，编码器模块132能够确定针对未填充或已填充的用户数据的奇偶校验数据，也能够对具有对应的奇偶校验数据和填充数据的用户数据进行解码。另外，编码器模块132能够通过调整编码参数来对用于编码数据的码率或奇偶校验率进行调节。控制器130和/或编码器模块132还能够包括内部存储器(未示出)，其可以属于一个或多个适当的存储器类型。
非易失性存储器阵列140能够使用NAND闪速存储器设备来实施。能够替代地使用其他类型的固态存储器设备，例如，闪速集成电路的阵列、硫系RAM(C-RAM)、相变存储器(PC-RAM或PRAM)、可编程金属化单元RAM(PMC-RAM或PMCm)、双向统一存储器(OUM)、阻变RAM(RRAM)、NOR存储器、EEPROM、铁电存储器(FeRAM)、磁阻RAM(MRAM)、其他分立的NVM(非易失性存储器)芯片或其任意组合。在一个实施例中，尽管可以使用单层单元(SLC)存储器设备或SLC设备和多层单元(MLC)设备的组合，但非易失性存储器阵列140优选地包括具有能够存储多于单个位信息的多层单元的MLC设备。在一个实施例中，存储系统120能够包括诸如一个或多个磁存储器模块等其他存储器模块。存储系统120还能够包括诸如磁存储等其他类型的存储介质。
自适应数据编码
图2是示出了根据本发明的一个实施例的确定用于编码数据的编码参数的流程图。过程200能够由控制器130和/或编码器模块132来执行。有利地，过程200能够使控制器130和/或编码器模块132能够使用多个码字长来支持多个非易失性存储器页格式。
在方框205，过程200确定诸如非易失性存储器阵列140等非易失性存储器阵列的存储器页大小。例如，存储器页大小能够由存储器阵列厂商来提供或基于其他已知存储器大小来计算。例如，存储器页大小可以与非易失性存储器阵列的E页大小相对应，而过程200能够通过查询厂商提供的存储器阵列的F页大小并将F页的大小除以诸如4或8等对于非易失性存储器阵列适当的常数，来计算E页大小。在其他实施例中，存储器页大小能够与F页大小相对应。
在方框210，过程200从多种码字长中选择等于或超过存储器页大小的码字长。例如，存储器页大小能够是2164字节或八位位组，多个预定义的码字长能够包括2176字节和2304字节的长度。在一个实施例中，过程200从多个预定义的LDPC码字长中选择等于或大于存储器页大小的具有最小大小或数据字节数的LDPC码字长。例如，过程200能够选择2176字节的码字长，该码字长超过2164字节的存储器页大小并且具有多个预定义LDPC码字长中的最小大小。
在框215，过程200至少部分地基于所选择的码字长来确定编码参数。在对从非易失性存储器阵列读取的数据或写入到非易失性存储器阵列的数据进行编码时能够使用编码参数，并且编码参数使过程200能够管理数据的码率(例如，每数据单元的总数据的用户数据量，其中总数据包括用户数据和奇偶校验数据)。在一个实施例中，针对LDPC码字长的编码参数包括列权值、P矩阵大小和行权值，并且进一步包括码率、用户数据量和奇偶校验数据量中的至少一个。
在方框220，过程200存储编码参数。例如，过程200能够在非易失性存储器阵列140中和/或在存储系统120的一个或多个其他存储介质中存储编码参数。过程200能够在控制器130和/或编码器模块132的内部存储器中存储编码参数。所存储的编码参数能够便于使用不同的编码参数来编码非易失性存储器140中不同的页、块或其他划分和/或细分，以及便于随着非易失性存储器阵列的部分老化和/或逐渐耗尽来随着时间推移跟踪和调整编码参数。
图3是示出了根据本发明的一个实施例的LDPC编码参数和LDPC码字长之间关系的表300。表300能够标明由诸如控制器130和/或编码器模块132等控制器所支持的LDPC码子长和LDPC编码参数。表300能够存储在非易失性存储器阵列140、存储系统120中的一个或多个其他存储介质和/或控制器130和/或编码器模块132的内部存储器中。表300包括两个码长列，指示两种支持的LDPC码字长。一种LDPC码字长等于2176字节(2048+128·1字节)，而另一种LDPC码字长等于2304字节(2048+128·2字节)。已经发现，约2K字节的多种码率能够提供复杂性和性能之间的最佳折衷。
对于每个码长，包括列权值、P矩阵大小和行权值的LDPC编码参数可以是多样的，以使得能够对采用不同设计的码率(例如，不同的每数据单元的总数据的用户数据量，其中总数据包括用户数据和奇偶校验数据)的数据进行编码，如表300中所列出的那样。例如，如果LDPC码字长等于2176字节，则适用的LDPC编码参数可以是在圈C1、C2、C3或C4处的LDPC编码参数集合的其中之一。在一个实例中，能够选择圈C3处的LDPC编码参数，其对应列权值为4、P矩阵大小为512和行权值为34，并且还对应码率为0.882(对于2176字节的总码长，有1920字节的用户数据)。此外，在一个实施例中，可以被定义为2048+128xΔ的码长，能够被基于选择Δ为1或2等来进行调整。如所示出的那样，对Δ的值的选择也影响码率。例如，在圈C1，选择Δ为1使得码率为0.941，并且如果列权值、P矩阵大小和行权值保持不变，选择Δ为2使得码率为0.944。如将进一步解释的那样，能够使用多种预定义码率来适应不同页大小的存储器阵列。例如，如所示出的，两种码长2176字节和2304字节能够适应2176字节和2304字节的页大小。应当注意的是，在实践中预定义的码长的数量可以大大高于二，以适应多种页大小。
支持表300中的LDPC编码参数的控制器能够有利地为非易失性存储器阵列选择一个码长，并且调整LDPC编码参数来以不同码率对数据进行编码。例如，当E页大小为2176字节的存储器阵列相对较新(例如，轻度使用)和/或经历或展现了很少的编码错误时，可以选择在圈C1处的LDPC编码参数来编码数据。在圈C1处的LDPC编码参数对应列权值为4、P矩阵大小为256和行权值为68，以及还对应码率为0.941。在圈C1处，能够使用总共128字节的奇偶校验来编码2048字节的数据。随着存储器页、块或存储器阵列的管芯老化和/或逐渐耗尽，能够选择在圈C2、C3和C4处的LDPC编码参数作为代替来编码数据。因此，响应于非易失性存储器阵列质量的改变(例如，质量的损失)，控制器能够逐渐增加每单元数据的奇偶校验量，从0.941的码率分别到在圈C2、C3和C4处的0.926、0.882和0.853的码率。
自适应码缩短
整个自适应码缩短中，本发明的一些实施例能够适应具有与预定义码长不完全匹配的页大小的存储器阵列。图4A-4C是示出了根据本发明的一个实施例的在自适应码缩短中所使用的已填充用户数据和奇偶校验数据的图。特别地，图4A-4C示出了可以怎样使用缩短来调整码字长以匹配非易失性存储器阵列的存储器页大小。有利地，缩短使控制器130和/或编码器模块132能够支持其中存储器页大小不等于多个预定义的码字长中的任何码字长的存储器页格式。例如，如果控制器130和/或编码器模块132支持等于2176和2304字节的预定义的LDPC码字长，则能够使用缩短以使得控制器130和/或编码器模块132还支持2164字节的存储器页大小。此外，缩短能够准许控制器130和/或编码器模块132自适应地编码数据以使其匹配非易失性存储器阵列格式，而不牺牲大的位错误率性能。
在一个实施例中，缩短包括三个操作。第一，将填充数据加到将要被编码的用户数据上。在一个实施例中的填充数据的大小是预定义码长与存储器页大小之差。第二，基于填充数据和用户数据产生奇偶校验数据。第三，将合计达存储器页大小的用户数据和奇偶校验数据存储在存储器页中。填充数据不被存储，但是在解码时(例如，稍后当用户数据和奇偶校验数据被从存储器页读出时)将被附加到用户数据上。
图4A示出了数据单元400a中的填充数据410和用户数据420。用户数据420对应于数据单元400a的用户数据量，而填充数据410对应于便于码缩短的填充数据。填充数据410能够包括全零、全一等的数据组或任何已知的或预定义的数据模式。继续先前段中的示例，如果非易失性存储器阵列的存储器页大小为2164字节，那么控制器130和/或编码器模块132能够从诸如表300中所示出的那些多种预定义码长中选择大小等于或大于2164字节的最短的LDPC码字长。在该示例中，选择2176字节的码长。控制器130和/或编码器模块132能够确定：填充数据410应该包括长度等于码字长(2176)与非易失性存储器阵列的存储器页大小(2164)之差的数据组，即2176–2164＝12字节的填充数据。取决于数据单元400a的LDPC编码参数，控制器130和/或编码器模块132还能够确定：为用户数据420保留的字节量和用于确定和/或生成奇偶校验数据的适当的G编码矩阵。
图4B示出了根据一个实施例的一个示例性编码过程。实际上，用户数据420被“填充”，以使得组合在一起的用户数据和填充数据满足所选择的预定义字长中为用户数据保留的字节量。然后为数据单元400b中组合在一起的填充数据410和用户数据420生成奇偶校验430。继续先前段的示例，能够使用适当的G编码矩阵来确定LDPC奇偶校验数据以用于奇偶校验430。注意，如上文所描述的，2176字节在填充数据410、用户数据420和奇偶校验数据430中的实际分配可以变化。下表示出了一些可能的配置(所有大小单位为字节)：
存储器页大小2164字节
存储器页大小2164字节
图4C示出了数据单元400c，其具有数据单元400b的用户数据420和奇偶校验430，移除了填充数据410。能够将用户数据420和奇偶校验430写入到非易失性存储器阵列140的存储器页，并随后从非易失性存储器阵列140的存储器页读取用户数据420和奇偶校验430。如上表所示，用户数据420和奇偶校验数据430的量可以等于非易失性存储器阵列的存储器页大小，并且填充数据不被写入到页中。当该页稍后被读出时，作为解码的一部分，填充数据被附加回从该页读取的用户数据。照这样，能够以在编码效率上很小的损失为代价使用多个预定义码字长中的一个来执行针对任意页大小的编码。
图5是示出了根据本发明的一个实施例的自适应码缩短的过程500的流程图。过程500可以由控制器130和/或编码器模块132来执行。有利地，过程500可以使控制器130和/或编码器模块132能够支持这样的存储器页大小：其不等于控制器130和/或编码器模块132所支持的多个预定义码字长中的任意码字长。过程500能够用于构建和管理图4A-4C中所描述的数据单元400a、400b和400c。
在方框505，过程500接收用户数据。用户数据能够连同将用户数据写入到非易失性存储器阵列(例如，非易失性存储器阵列140)的写入命令一起，从存储接口模块112接收。
在方框510，过程500用填充数据来对用户数据进行填充。填充数据能够包括全零、全一的数据组或者已知的或预定义的数据模式。另外，在方框510，过程500还能够将用户数据分成大小等于每数据单元的用户数据量的单元，这取决于对应的编码参数。例如，如果非易失性存储器阵列具有等于2164字节的存储器页大小并且LDPC编码参数对应图3中圈C3处的参数，那么能够将用户数据分成大小等于1908字节的单元。
在方框515，过程500使用编码参数确定用于已填充用户数据的奇偶校验数据。继续先前段的示例，如果LDPC编码参数对应圈C3处的参数，那么能够选择并使用适当的G编码矩阵来确定用于已填充用户数据的LDPC奇偶校验数据。
在方框520，过程500输出用户数据和奇偶校验数据。例如，过程500能够输出用户数据和奇偶校验数据以使其存储到非易失性存储器阵列140中的F页143中的E页144。能够注意到的是，参照方框510和方框515所描述的填充可以被表征为“虚拟填充”，这是因为填充数据自身可以不被写入到存储器页。
码率调整
图6是示出了根据本发明的一个实施例的调整码率的过程600的流程图。过程600能够由控制器130和/或编码器模块132来执行。有利地，过程600可以使控制器130和/或编码器模块132能够随着存储器页、块或非易失性存储器阵列的其他划分逐渐耗尽和/或经历质量降低，来调整存储器页、块或其他划分的码率(例如，每单元数据的奇偶校验的量)。
在方框605，过程600读取存储在存储器页中的用户数据和奇偶校验数据。例如，过程600能够响应于来自主机系统110的读取命令而执行对F页143的读取。
在方框610，当使用奇偶校验数据和编码参数来解码用户数据时，过程600检测到若干位错误。例如，当使用所存储的奇偶校验数据和对应于存储器页的LDPC编码参数来解码用户数据时，过程600能够确定若干检测到的位错误。
在方框615，过程600对位错误的数量是否超过位错误阈值进行确定。位错误阈值能够取决于用于将数据编码到存储器页的编码参数或者基于编码参数而变化。例如，针对图3中圈C1处的LDPC编码参数的位错误阈值可以低于针对圈C2处的LDPC编码参数的位错误阈值。如果过程600确定位错误的数量不超过位错误阈值，那么过程600终止。另一方面，如果过程600确定位错误的数量超过位错误阈值，那么过程600进行到方框620。
在方框620，过程600检查是否能够调整编码参数以减少码率。换言之，过程600能够确定是否可以使用更多奇偶校验数据来进行编码。在一个实施例中，过程600能够确定是否可以调整LDPC编码参数同时保持LDPC码字长不变。例如，如果当前使用图3中圈C3处的LDPC编码参数来编码E页144，那么能够将LDPC编码参数调整为圈C4处的参数。替代地，如果当前使用圈C4处的LDPC编码参数来编码E页144并且表300包含唯一可用的LDPC编码参数，那么参数不可以被进一步调整为更低码率。如果过程600确定不可以调整编码参数以减小码率，那么过程600终止。另一方面，如果过程600确定能够调整编码参数以减小码率，那么过程600进行到方框625。在一个实施例中，可以在块一级上管理码率的改变，其中块中的页被同时转换到新码率。在使用MLC存储器的一个实施例中，在确定了不能使用进一步减少的码率时，页(或页构成的块)可以被配置为在仅较低页模式下操作，而不是终止过程600。
在方框625，过程600调整编码参数并存储所调整的编码参数以减少下一次写入操作的码率。过程600能够将所调整的编码参数存储在非易失性存储器阵列140中、存储系统120的其他存储器模块中和/或控制器130和/或编码器模块132的内部存储器中。过程600能够存储关于用于编码数据的码率或LDPC编码参数的指示，以便于管理存储器页、块或非易失性存储器阵列的其他级别的划分上的LDPC编码参数。此外，所调整的编码参数能够用于对与随后从主机系统110接收到的写入命令相关联的用户数据进行编码。
其他变化
本领域技术人员将会意识到，在一些实施例中能够使用其他方法和途径。例如，本文所披露的编码技术能够应用到除LDPC码之外的码，诸如像Turbo码等其他迭代码。另外，尽管图3中表300所披露的编码参数和其他值示出了一组编码参数和码字长之间关系的示例，但其他的或附加的编码关系也能够被使用。表300能够包括值小于4和大于5(例如，3或6)的列权值、值小于256位或大于512位(例如，128或1024)的P矩阵大小、小于1或大于2(例如，-1、0、3或4)的Δ值、对应的粒度不同于128字节(例如，64字节)的Δ值以及具有小于或大于2048(例如，2176)的值的基码长。此外，在每个数据单元中奇偶校验数据量能够被设置为不同的值，或者取决于存储介质的质量而变化。另外，能够采用除位错误之外的或不同于位错误的质量测度来确定是否调整用于编码数据的编码参数。而且，可以取决于实施例而移除上文所描述的特定步骤以及可以加入其它步骤。因此，旨在仅参照所附权利要求来定义本公开的范围。
尽管已经描述了某些实施例，但这些实施例只是以示例的方式给出，而并不是要限制保护范围。实际上，可以以多种其他形式实施本文所描述的新颖方法和系统。另外，可以进行本文所描述的方法和系统的形式上的各种省略、替换和改变，而不脱离本保护的精神。所附权利要求及其等价物旨在涵盖这样的将落入本保护的范围和精神的形式或变型。例如，能够将本文所披露的系统和方法应用到硬盘驱动器、混合硬盘等。另外，可以额外地或可替代地使用其他形式的存储(例如，DRAM或SRAM、电池备用易失性DRAM或SRAM设备、EPROM、EEPROM存储器等等)。作为另一个示例，可以将在附图中示出的各种部件实施为处理器上的软件和/或固件、ASIC/FPGA或专用硬件。同样，上文所披露的特定实施例的特征和属性可以以不同的方式组合以形成另外的实施例，其全部落入本公开的范围内。尽管本公开提供了某些优选的实施例和应用，但对本领域技术人员显而易见的是，其他实施例，包括没有提供本文所阐述的全部特征和优点的实施例，也在本公开的范围内。因此，旨在仅参考所附权利要求来定义本公开的范围。

Claims (13)

1.一种固态存储系统，包括：
非易失性存储器阵列，所述非易失性存储器阵列包括多个存储器页，每个存储器页具有共同的存储器页大小；以及
控制器，所述控制器被配置为：
确定所述非易失性存储器阵列的所述共同的存储器页大小；
从多个预定义的低密度奇偶校验(LDPC)码字长中选择LDPC码字长，所述LDPC码字长的大小等于或大于所述非易失性存储器阵列的所述共同的存储器页大小；以及
至少部分地基于所述LDPC码字长来确定LDPC编码参数以用于对写入到所述非易失性存储器阵列的一个或多个存储器页的数据或从所述一个或多个存储器页中读取的数据进行编码，
其中，所述控制器被配置为使用所述多个预定义的LDPC码字长来支持多个非易失性存储器页格式，并且被配置为支持这样的存储器页格式：其中所述共同的存储器页大小不等于所述多个预定义的LDPC码字长中的任何LDPC码字长。
2.根据权利要求1所述的固态存储系统，其中，所述LDPC编码参数包括P矩阵大小、列权值和行权值，并且进一步包括码率、用户数据量和奇偶校验数据量的至少其中之一。
3.根据权利要求1所述的固态存储系统，其中，所述控制器被配置为选择等于或大于所述非易失性存储器阵列的所述共同的存储器页大小的具有最小大小的LDPC码字长。
4.根据权利要求1所述的固态存储系统，其中，所述存储器页包括错误纠正码页(E页)。
5.根据权利要求1所述的固态存储系统，其中所述控制器进一步被配置为：
采用所述LDPC编码参数来确定针对已填充用户数据的奇偶校验数据，所述已填充用户数据包括用户数据和填充数据；以及
将所述用户数据和所述奇偶校验数据存储在所述非易失性存储器阵列的存储器页中。
6.根据权利要求5所述的固态存储系统，其中，所述已填充用户数据的所述填充数据的量至少部分地取决于所述LDPC码字长与所述非易失性存储器阵列的所述共同的存储器页大小之差。
7.一种在包括控制器的数据存储系统中编码数据的方法，所述方法包括：
确定非易失性存储器阵列的共同的存储器页大小，所述非易失性存储器阵列包括多个存储器页，每个存储器页具有所述共同的存储器页大小；
从多个预定义的低密度奇偶校验(LDPC)码字长中选择LDPC码字长，所述LDPC码字长的大小等于或大于所述非易失性存储器阵列的所述共同的存储器页大小；以及
至少部分地基于所述LDPC码字长来确定LDPC编码参数以用于对写入到所述非易失性存储器阵列的一个或多个存储器页的数据或从所述一个或多个存储器页中读取的数据进行编码。
8.根据权利要求7所述的方法，其中，所述LDPC编码参数包括P矩阵大小、列权值和行权值，并且进一步包括码率、用户数据量和奇偶校验数据量的至少其中之一。
9.根据权利要求7所述的方法，其中，所述的选择所述LDPC码字长包括选择等于或大于所述非易失性存储器阵列的所述共同的存储器页大小的具有最小大小的所述LDPC码字长。
10.根据权利要求7所述的方法，其中，所述存储器页包括错误纠正码页(E页)。
11.根据权利要求7所述的方法，进一步包括：
采用所述LDPC编码参数来确定针对已填充用户数据的奇偶校验数据，所述已填充用户数据包括用户数据和填充数据；以及
将所述用户数据和所述奇偶校验数据存储在所述非易失性存储器阵列的存储器页中。
12.根据权利要求11所述的方法，其中，所述已填充用户数据的所述填充数据的量至少部分地取决于所述LDPC码字长与所述非易失性存储器阵列的所述共同的存储器页大小之差。
13.一种固态存储系统，包括：
非易失性存储器阵列，所述非易失性存储器阵列包括多个存储器页，每个存储器页具有共同的存储器页大小；以及
控制器，所述控制器被配置为：
确定所述非易失性存储器阵列的所述共同的存储器页大小；
从多个预定义的码字长中选择码字长，所述码字长的大小等于或大于所述非易失性存储器阵列的所述共同的存储器页大小；以及
至少部分地基于所述码字长来确定编码参数以用于对写入到所述非易失性存储器阵列的一个或多个存储器页的数据或从所述一个或多个存储器页中读取的数据进行编码，
其中，所述控制器被配置为使用所述多个预定义的码字长来支持多个非易失性存储器页格式。
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