CN104835849B - 槽栅结构的n型ldmos器件及工艺方法 - Google Patents

槽栅结构的n型ldmos器件及工艺方法 Download PDF

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CN104835849B
CN104835849B CN201510107046.8A CN201510107046A CN104835849B CN 104835849 B CN104835849 B CN 104835849B CN 201510107046 A CN201510107046 A CN 201510107046A CN 104835849 B CN104835849 B CN 104835849B
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CN104835849A (zh
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石晶
钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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Abstract

本发明公开了一种槽栅结构的N型LDMOS器件，在P型衬底上的N型外延层中具有P阱，P阱中具有所述LDMOS器件的源区以及重掺杂P型区，衬底表面具有场氧化层，沟槽型的多晶硅栅极位于N型外延层中，沟槽内壁具有栅氧化层；所述的N型外延层中还具有P型外延层，深接触孔穿通P型外延层底部位于N型外延层中。上述结构使器件表面电场降低，器件具有更高的击穿电压。本发明还公开了所述槽栅结构的N型LDMOS器件的工艺方法。

Description

槽栅结构的N型LDMOS器件及工艺方法
技术领域
本发明涉及半导体领域，特别是指一种槽栅结构的N型LDMOS器件，本发明还涉及所述槽栅结构的N型LDMOS器件的工艺方法。
背景技术
DMOS由于具有耐高压，大电流驱动能力和极低功耗等特点，目前在电源管理电路中被广泛采用。在BCD工艺中，DMOS虽然与CMOS集成在同一块芯片中，但由于高耐压和低导通电阻的要求，DMOS在本底区和漂移区的条件与CMOS现有的工艺条件共享的前提下，其导通电阻与击穿电压存在矛盾，往往无法满足开关管应用的要求。在LDMOS器件中，导通电阻是一个重要的指标。因此，为了制作高性能的LDMOS，需要采用各种方法优化器件的导通电阻及击穿电压。
目前常规的槽栅结构的N型LDMOS的结构如图1所示，图中包含P型衬底101，N型外延层102，P阱103，栅氧化层104，多晶硅栅极105，重掺杂N型区(源区)106，衬底表面具有场氧化层108。这种结构在表面的电场强度较高，导通性能不佳。
发明内容
本发明所要解决的技术问题是提供一种槽栅结构的N型LDMOS器件。
为解决上述问题，本发明提供一种槽栅结构的N型LDMOS器件，在P型衬底上的N型外延层中具有沟槽，沟槽内壁附着栅氧化层并填充多晶硅形成所述LDMOS器件的多晶硅栅极；所述LDMOS器件的源区位于P阱中，且P阱中还具有重掺杂P型区；衬底表面具有场氧化层；所述的N型外延层之上还具有P型外延层，所述P阱位于P型外延层中，深接触孔穿通P型外延层底部位于N型外延层中。
所述P型外延层深度为3～10μm。
为解决上述问题，本发明所述的槽栅结构的N型LDMOS器件的工艺方法，包含如下步骤：
第1步，在P型衬底上形成N型外延层和P型外延层；
第2步，在P型外延层中离子注入形成P阱；
第3步，刻蚀形成沟槽，并通过热氧化的方法在沟槽内形成栅氧化层，淀积多晶硅后刻蚀形成多晶硅栅极；
第4步，P阱中离子注入形成源区和重掺杂P型区；
第5步，硅衬底表面形成场氧化层，进行接触孔及深接触孔的制作。
所述第1步，所采用的衬底为电阻率范围为0.007～0.013Ω·cm的P型衬底。
所述第5步，深接触孔穿通P型外延层，其底部位于N型外延层中。
本发明所述的槽栅结构的N型LDMOS器件，其沟槽型的多晶硅栅极使得表面电场降低，增加器件的可靠性，同时在有限的尺寸下得到更高的击穿电压，P型外延层增强漂移区耗尽，同时采用深接触孔淀积使得电流路径减少，导通性能得到改善。
附图说明
图1是传统N型LDMOS器件的结构示意图。
图2～图6是本发明工艺步骤示意图。
图7是本发明工艺步骤流程图。
附图标记说明
101是P型衬底，102是N型外延层，103是P阱，104是栅氧化层，105是多晶硅栅极，106是重掺杂N型区(源区)，107是重掺杂P型区，108是场氧化层，109是深接触孔(电极)，110是P型外延层。
具体实施方式
本发明所述的槽栅结构的N型LDMOS器件，如图6所示，在P型衬底101上的N型外延层102中具有沟槽，沟槽内壁附着栅氧化层104并填充多晶硅形成所述LDMOS器件的多晶硅栅极105；所述LDMOS器件的源区106位于P阱103中，且P阱103中还具有重掺杂P型区107；衬底101表面具有场氧化层108；所述的N型外延层102之上还具有P型外延层110，所述P型外延层110深度为3～10μm。所述P阱103位于P型外延层110中，深接触孔109穿通P型外延层110底部位于N型外延层102中。
为解决上述问题，本发明所述的槽栅结构的N型LDMOS器件的工艺方法，包含如下步骤：
第1步，如图2所示，在电阻率范围为0.007～0.013Ω·cm的低阻P型衬底101上形成N型外延层102和厚度约为3～10μm的P型外延层110。
第2步，如图3所示，在P型外延层110中离子注入形成P阱103。
第3步，如图4所示，刻蚀形成沟槽，并通过热氧化的方法在沟槽内形成栅氧化层104，淀积多晶硅后刻蚀形成多晶硅栅极105。
第4步，P阱103中离子注入形成重掺杂N型区106和重掺杂P型区107，如图5所示，重掺杂N型区106作为所述LDMOS器件的源区。
第5步，硅衬底101表面形成场氧化层108，进行接触孔及深接触孔109的制作，深接触孔109穿通P型外延层110，其底部位于N型外延层102中。最终完成如图6所示。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

1.一种槽栅结构的N型LDMOS器件，在P型衬底上的N型外延层中具有沟槽，沟槽内壁附着栅氧化层并填充多晶硅形成所述LDMOS器件的多晶硅栅极；所述LDMOS器件的源区位于P阱中，且P阱中还具有重掺杂P型区；衬底表面具有场氧化层；其特征在于：所述的N型外延层之上还具有P型外延层，所述P阱位于P型外延层中，深接触孔穿通P型外延层底部位于N型外延层中。
2.如权利要求1所述的槽栅结构的N型LDMOS器件，其特征在于：所述P型外延层厚度为3～10μm。
3.制造如权利要求1所述的槽栅结构的N型LDMOS器件的工艺方法，其特征在于：包含如下步骤：
第1步，在P型衬底上形成N型外延层和P型外延层；
第2步，在P型外延层中离子注入形成P阱；
第3步，刻蚀形成沟槽，并通过热氧化的方法在沟槽内形成栅氧化层，淀积多晶硅后刻蚀形成多晶硅栅极；
第4步，P阱中离子注入形成源区和重掺杂P型区；
第5步，硅衬底表面形成场氧化层，进行接触孔及深接触孔的制作。
4.如权利要求3所述的槽栅结构的N型LDMOS器件的工艺方法，其特征在于：所述第1步，所述衬底为电阻率范围为0.007～0.013Ω·cm的P型衬底。
5.如权利要求3所述的槽栅结构的N型LDMOS器件的工艺方法，其特征在于：所述第5步，深接触孔穿通P型外延层，其底部位于N型外延层中。
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CN102738240A (zh) * 2012-06-04 2012-10-17 电子科技大学 一种双栅功率mosfet器件

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