CN104835735A - 一种沟槽igbt器件的制造方法 - Google Patents
一种沟槽igbt器件的制造方法 Download PDFInfo
- Publication number
- CN104835735A CN104835735A CN201510228626.2A CN201510228626A CN104835735A CN 104835735 A CN104835735 A CN 104835735A CN 201510228626 A CN201510228626 A CN 201510228626A CN 104835735 A CN104835735 A CN 104835735A
- Authority
- CN
- China
- Prior art keywords
- photoetching
- igbt device
- layer
- source region
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 4
- 238000011049 filling Methods 0.000 claims abstract description 4
- 239000011810 insulating material Substances 0.000 claims abstract description 4
- 238000005224 laser annealing Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000001413 cellular effect Effects 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 12
- 238000002513 implantation Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000280 densification Methods 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000004857 zone melting Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
一种沟槽IGBT器件的制作方法,它包括如下步骤:a)首先在N型外延硅衬底或者区熔片上进行P阱光刻,形成所需的P阱;b)光刻刻蚀沟槽,生长栅极氧化层,淀积多晶硅材料填充沟槽;然后光刻刻蚀多晶硅形成顶层MOS结构的栅极;c)光刻N型源区注入N型杂质,然后淀积氧化层或者氮化硅等绝缘材料并退火致密,光刻接触孔,刻蚀绝缘层裸露出之前形成的所有元胞的P阱区和N型源区硅表面;d)溅射顶层金属,光刻刻蚀顶层金属,淀积钝化层,光刻刻蚀钝化层,完成顶层MOS结构的制作;e)硅片背面减薄到特定的厚度,背面注入P型杂质通过低温退火或者激光退火形成IGBT集电区,最后通过溅射或者蒸发的方法淀积背面金属完成整个IGBT器件的制作过程。
Description
技术领域
本发明涉及一种沟槽IGBT器件的制造方法。
背景技术
作为新型电力半导体器件的主要代表,IGBT被广泛用于工业、信息、新能源、医学、交通、军事和航空领域。目前,市场上的IGBT器件的耐压高达6500V,单管芯电流高达200A,频率达到300KHz。在高频大功率领域,目前还没有任何一个其它器件可以代替它。随着半导体材料和加工工艺的不断进步,采用沟槽技术的IGBT器件已成为主流产品。沟槽IGBT相比平面IGBT存在短路大的问题,为了克服沟槽技术高沟道密度带来的短路能力弱的问题,各个芯片厂家采用几种减少沟道密度的沟槽IGBT器件结构。
发明内容
本发明的目的在于克服现有技术存在的不足,而提供一种制作工艺简单,方法可靠,采用减少单位面积的有效元胞数量,比如选择性的接触顶层MOS结构的源极或者栅极多晶硅横跨两个元胞结构,来降低沟道密度的沟槽IGBT器件的制造方法。
本发明的目的是通过如下技术方案来完成的,一种沟槽IGBT器件的制作方法,该制作方法包括如下步骤:
a)首先在N型外延硅衬底或者区熔片上进行P阱光刻,形成所需的P阱;然后通过局部氧化方法或者场氧化层刻蚀方法形成有源区;
b)光刻刻蚀沟槽,生长栅极氧化层,淀积多晶硅材料填充沟槽;然后光刻刻蚀多晶硅形成顶层MOS结构的栅极;
c)光刻N型源区注入N型杂质,然后淀积氧化层或者氮化硅等绝缘材料并退火致密,光刻接触孔,刻蚀绝缘层裸露出之前形成的所有元胞的P阱区和N型源区硅表面;注入P型杂质并激活,确保P阱区与顶层金属的欧姆接触;
d)溅射顶层金属,光刻刻蚀顶层金属,淀积钝化层,光刻刻蚀钝化层,完成顶层MOS结构的制作。
e)硅片背面减薄到特定的厚度,背面注入P型杂质通过低温退火或者激光退火形成IGBT集电区,最后通过溅射或者蒸发的方法淀积背面金属完成整个IGBT器件的制作过程。
所述的步骤b)中,选择性注入顶层MOS结构的N型源区来控制沟道密度。
所述的步骤c)中,通过接触孔接触顶层MOS结构所有元胞的P型阱区和N型源区,避免出现空穴电流集中现象。
所述的步骤e)中,IGBT器件背面金属是通过溅射或者蒸发的方式淀积的。
本发明针对沟槽结构的IGBT,采用在发射区选择性的注入N型杂质来降低顶层MOS器件沟道密度,通过接触每个元胞的P型阱区,使得空穴电流均匀分布在每个元胞的P阱上,提高器件抗闩锁能力;它具有制作工艺简单,方法可靠,采用减少单位面积的有效元胞数量,比如选择性的接触顶层MOS结构的源极或者栅极多晶硅横跨两个元胞结构,来降低沟道密度等特点。
附图说明
图1是现有技术中栅极多晶硅横跨两个元胞的沟槽IGBT结构图。
图2是现有技术中选择性接触顶层MOS结构的源极的沟槽IGBT结构图。
图3是本发明所述的选择性注入N型源区并接触所有元胞的沟槽IGBT结构图。
具体实施方式
下面将结合附图及实施例对本发明作详细的介绍:一种沟槽IGBT器件的制作方法,该制作方法包括如下步骤:
a)首先在N型外延硅衬底或者区熔片上进行P阱光刻,形成所需的P阱;然后通过局部氧化方法或者场氧化层刻蚀方法形成有源区;
b)光刻刻蚀沟槽,生长栅极氧化层,淀积多晶硅材料填充沟槽;然后光刻刻蚀多晶硅形成顶层MOS结构的栅极;
c)光刻N型源区注入N型杂质,然后淀积氧化层或者氮化硅等绝缘材料并退火致密,光刻接触孔,刻蚀绝缘层裸露出之前形成的所有元胞的P阱区和N型源区硅表面;注入P型杂质并激活,确保P阱区与顶层金属的欧姆接触;
d)溅射顶层金属,光刻刻蚀顶层金属,淀积钝化层,光刻刻蚀钝化层,完成顶层MOS结构的制作。
e)硅片背面减薄到特定的厚度,背面注入P型杂质通过低温退火或者激光退火形成IGBT集电区,最后通过溅射或者蒸发的方法淀积背面金属完成整个IGBT器件的制作过程。
本发明优选的实施例是:所述的步骤b)中,选择性注入顶层MOS结构的N型源区来控制沟道密度。
本发明优选的实施例是:所述的步骤c)中,通过接触孔接触顶层MOS结构所有元胞的P型阱区和N型源区,避免出现空穴电流集中现象。
本发明优选的实施例是:所述的步骤e)中,IGBT器件背面金属是通过溅射或者蒸发的方式淀积的。
Claims (4)
1.一种沟槽IGBT器件的制作方法,其特征在于该制作方法包括如下步骤:
a)首先在N型外延硅衬底或者区熔片上进行P阱光刻,形成所需的P阱;然后通过局部氧化方法或者场氧化层刻蚀方法形成有源区;
b)光刻刻蚀沟槽,生长栅极氧化层,淀积多晶硅材料填充沟槽;然后光刻刻蚀多晶硅形成顶层MOS结构的栅极;
c)光刻N型源区注入N型杂质,然后淀积氧化层或者氮化硅等绝缘材料并退火致密,光刻接触孔,刻蚀绝缘层裸露出之前形成的所有元胞的P阱区和N型源区硅表面;注入P型杂质并激活,确保P阱区与顶层金属的欧姆接触;
d)溅射顶层金属,光刻刻蚀顶层金属,淀积钝化层,光刻刻蚀钝化层,完成顶层MOS结构的制作;
e)硅片背面减薄到特定的厚度,背面注入P型杂质通过低温退火或者激光退火形成IGBT集电区,最后通过溅射或者蒸发的方法淀积背面金属完成整个IGBT器件的制作过程。
2.根据权利要求1所述的沟槽IGBT器件的制作方法,其特征在于步骤b)中,选择性注入顶层MOS结构的N型源区来控制沟道密度。
3.根据权利要求1所述的沟槽IGBT器件的制作方法,其特征在于步骤c)中,通过接触孔接触顶层MOS结构所有元胞的P型阱区和N型源区,避免出现空穴电流集中现象。
4.根据权利要求1所述的沟槽IGBT器件的制作方法,其特征在于步骤e)中,IGBT器件背面金属是通过溅射或者蒸发的方式淀积的。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510228626.2A CN104835735A (zh) | 2015-05-07 | 2015-05-07 | 一种沟槽igbt器件的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510228626.2A CN104835735A (zh) | 2015-05-07 | 2015-05-07 | 一种沟槽igbt器件的制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104835735A true CN104835735A (zh) | 2015-08-12 |
Family
ID=53813540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510228626.2A Pending CN104835735A (zh) | 2015-05-07 | 2015-05-07 | 一种沟槽igbt器件的制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104835735A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105938798A (zh) * | 2016-04-08 | 2016-09-14 | 上海道之科技有限公司 | 一种沟槽igbt器件结构的制作方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104008971A (zh) * | 2014-01-13 | 2014-08-27 | 佛山芯光半导体有限公司 | 一种用于提升器件抗短路能力的沟槽igbt器件工艺 |
-
2015
- 2015-05-07 CN CN201510228626.2A patent/CN104835735A/zh active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104008971A (zh) * | 2014-01-13 | 2014-08-27 | 佛山芯光半导体有限公司 | 一种用于提升器件抗短路能力的沟槽igbt器件工艺 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105938798A (zh) * | 2016-04-08 | 2016-09-14 | 上海道之科技有限公司 | 一种沟槽igbt器件结构的制作方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2017139499A (ja) | 炭化珪素半導体装置の製造方法 | |
US20130234201A1 (en) | Field stop structure, reverse conducting igbt semiconductor device and methods for manufacturing the same | |
CN105679667A (zh) | 一种沟槽igbt器件的终端结构制造方法 | |
US20230223443A1 (en) | Silicon carbide semiconductor device | |
JP2015115337A (ja) | 炭化珪素半導体装置とその製造方法 | |
CN103035521B (zh) | 实现少子存储层沟槽型igbt的工艺方法 | |
CN103477439A (zh) | 半导体装置及其制造方法 | |
JP2007129231A (ja) | 空乏ストップ層を有するトレンチ絶縁ゲートバイポーラトランジスタ(igbt) | |
CN102916042B (zh) | 逆导igbt器件结构及制造方法 | |
KR20160065326A (ko) | 전력용 반도체 소자 및 그 소자의 제조 방법 | |
CN114975602A (zh) | 一种高可靠性的igbt芯片及其制作方法 | |
CN105070663B (zh) | 一种碳化硅mosfet沟道自对准工艺实现方法 | |
WO2018000223A1 (zh) | 一种绝缘栅双极型晶体管结构及其制造方法 | |
CN104617045A (zh) | 沟槽栅功率器件的制造方法 | |
WO2024037276A1 (zh) | 一种深缓冲层高密度沟槽的igbt器件及其制备方法 | |
WO2024037274A1 (zh) | 一种具有反向导通特性的igbt器件及其制备方法 | |
CN105280493A (zh) | 一种沟槽igbt器件的制造方法 | |
CN108493110A (zh) | 一种利用全固态电池实现增强型iii-v hemt器件的方法 | |
RU2498448C1 (ru) | Способ изготовления свч ldmos транзисторов | |
CN102290434B (zh) | 带栅下缓冲层结构的金属半导体场效应晶体管及制作方法 | |
WO2023082657A1 (zh) | Sic mosfet器件的制备方法 | |
CN103117309A (zh) | 一种横向功率器件结构及其制备方法 | |
CN104835735A (zh) | 一种沟槽igbt器件的制造方法 | |
CN113964197B (zh) | 一种低泄漏电流的igbt器件及其制备方法 | |
CN105679668A (zh) | 一种沟槽igbt器件的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
EXSB | Decision made by sipo to initiate substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20171220 Address after: Jiaxing City, Zhejiang province 314006 Nanhu District Branch Road No. 988 Applicant after: STARPOWER SEMICONDUCTOR LTD. Address before: Jiaxing City, Zhejiang province 314006 Ring Road No. 18 Sidalu Applicant before: Jiaxing Starpower Microelectronics Co., Ltd. |
|
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150812 |