CN104795358B - 钴阻挡层的形成方法和金属互连工艺 - Google Patents
钴阻挡层的形成方法和金属互连工艺 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000010941 cobalt Substances 0.000 title claims abstract description 68
- 229910017052 cobalt Inorganic materials 0.000 title claims abstract description 68
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 title claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 64
- 239000002184 metal Substances 0.000 title claims abstract description 64
- 230000004888 barrier function Effects 0.000 title claims abstract description 48
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000008021 deposition Effects 0.000 claims abstract description 16
- 238000000280 densification Methods 0.000 claims abstract description 11
- 238000005137 deposition process Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 113
- 239000000463 material Substances 0.000 claims description 37
- 238000009792 diffusion process Methods 0.000 claims description 15
- 238000000231 atomic layer deposition Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 230000002829 reductive effect Effects 0.000 claims description 9
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 5
- 239000012495 reaction gas Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000002344 surface layer Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 2
- 239000001569 carbon dioxide Substances 0.000 claims description 2
- 238000001723 curing Methods 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 13
- 210000002381 plasma Anatomy 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000011049 filling Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 238000003848 UV Light-Curing Methods 0.000 description 2
- CYHANSWJPNHHIE-UHFFFAOYSA-N [Si].[Ni].[Co] Chemical compound [Si].[Ni].[Co] CYHANSWJPNHHIE-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229960004424 carbon dioxide Drugs 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- GAURFLBIDLSLQU-UHFFFAOYSA-N diethoxy(methyl)silicon Chemical compound CCO[Si](C)OCC GAURFLBIDLSLQU-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 150000001388 alpha-terpinene derivatives Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910002090 carbon oxide Inorganic materials 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000003851 corona treatment Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000004088 foaming agent Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 238000004347 surface barrier Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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- C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
- C23C16/14—Deposition of only one other metal element
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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Abstract
本发明提供了一种钴阻挡层的形成方法和金属互连工艺,在表面具有金属互连线和线间介质层的半导体器件衬底上进行,包括:采用原子层沉积工艺将介质沉积到线间介质层表面,使所述线间介质层表面致密化;去除所沉积的介质,暴露出线间介质层的致密化的表面和金属互连线;钴选择性地沉积到金属互连线表面,从而形成钴阻挡层。本发明提高了钴在金属互连线和线间介质层表面之间的沉积选择性,从而降低了金属互连线之间的漏电流,提高了产品良率和可靠性。
Description
技术领域
本发明涉及半导体技术领域,具体涉及一种钴阻挡层的形成方法和金属互连工艺。
背景技术
随着CMOS集成电路制造工艺的发展以及关键尺寸的缩小,很多新的材料和工艺被运用到器件制造工艺中,用以改善器件性能。集成电路后段工艺流程中用铜线取代铝线,极大地降低了互联电阻。同时,采用多孔low k材料可以实现2.5以下的介电常数。这些技术都能够有效降低集成电路的RC延迟。
由于铜极易扩散,在后段Cu层化学机械掩膜之后,会先沉积一层铜扩散阻挡层,然后再进行后续low k材料的沉积,以避免铜向low k材料中扩散。在28nm以上技术节点,这一层铜扩散阻挡层通常采用氮掺杂碳化硅(NDC,k约为5.3)薄膜。而到了28nm以下技术节点,就会引入以CVD方式生长的钴膜扩散阻挡层。之所以需要钴扩散阻挡层是因为钴不仅能够更好的阻挡铜的扩散,同时也能防止生产过程中空气中的水汽渗透进入铜层。钴膜的引入意味着可以减薄氮掺杂碳化硅(NDC)薄膜的厚度,这有利于降低整体有效k值。另外,钴与铜具有很好的黏附性,可以极大地改进产品的可靠性。
钴在介质层上的沉积量越大,意味着铜互连线间的漏电流越大,因此,急需探索一种钴沉积方法,使其在多孔介质层上的沉积量尽量小,即沉积选择比尽量大。
发明内容
为了克服以上问题,本发明旨在提高钴在金属互连线表面和线间介质层表面的沉积选择性,减少在介质层上的钴沉积量。
为了实现上述目的,本发明提供了一种钴阻挡层的形成方法,在表面具有金属互连线和线间介质层的半导体器件衬底上进行,其包括以下步骤:
步骤01:采用原子层沉积工艺将介质沉积到所述线间介质层表面,使所述线间介质层表面致密化;
步骤02:去除所沉积的介质,暴露出所述线间介质层的致密化的表面和所述金属互连线;
步骤03:钴选择性地沉积到所述金属互连线表面,从而形成钴阻挡层。
优选地,在所述步骤02之后,且在所述步骤03之前,包括:采用还原性等离子体处理所述金属互连线表面和所述线间介质层表面。
优选地,所述线间介质层为多孔low-k材料。
优选地,所述步骤01中,所述介质渗透到所述多孔low-k材料里,使所述多孔low-k材料表面致密化。
优选地,所述步骤01中,所述原子层沉积工艺为等离子体增强原子层沉积工艺。
优选地,在原子层沉积过程中,降低所述衬底的温度,降低所采用的射频能量,采用低氧化性反应气体。
优选地,在原子层沉积过程中,所采用的反应气体为二氧化碳。
优选地,所述介质为氧化硅。
优选地,所述步骤03中,采用化学气相沉积法来沉积所述钴阻挡层。
为了实现上述目的,本发明还提供了一种金属互连工艺,其包括:
首先形成前段金属互连线和线间介质层;
然后,采用权利要求1的钴阻挡层的形成方法,在所述前段金属互连线表面形成钴阻挡层;
接着,在所述钴阻挡层和所述线间介质层表面形成扩散阻挡层;
最后,在所述扩散阻挡层上形成后段金属互连线。
本发明的一种钴阻挡层的形成方法和金属互连工艺,利用钴对致密度大的介质表面的沉积选择性较高的特点,采用原子层沉积方法将介质沉积在线间介质层表面,从而使线间介质层表面致密化,提高了钴在金属互连线和线间介质层表面之间的沉积选择性,从而降低了金属互连线之间的漏电流,提高了产品良率和可靠性。
附图说明
图1为本发明的一个较佳实施例的钴阻挡层的形成方法的流程示意图
图2~4为本发明的一个较佳实施例的钴阻挡层的形成方法的各步骤示意图
具体实施方式
为使本发明的内容更加清楚易懂,以下结合说明书附图,对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例,本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
本发明的钴阻挡层的形成方法,通过采用原子层沉积方式在线间介质层表面沉积介质,使其表面致密化,致使后续钴选择性地沉积在金属互连线表面,而在线间介质层表面沉积得非常少。原理为:原子层沉积过程中,介质会渗入线间介质层表层,使其致密化;并且,在不同的衬底表面所沉积的钴的数量或厚度不同,在致密的衬底表面,钴沉积的较少,而在疏松的或多孔的衬底表面,钴沉积的较多,也即是钴对衬底表面致密化程度的选择性沉积。本发明的目的为减少在线间介质层表面的钴的沉积,使钴选择性地沉积在金属互连线表面,因此,本发明通过介质形成于线间介质层表面来提高线间介质层表面的致密度,从而提高了钴在金属互连线表面和线间介质层表面之间的沉积选择性。
以下结合附图1~4和具体实施例对本发明的钴阻挡层的形成方法作进一步详细说明。需说明的是,附图均采用非常简化的形式、使用非精准的比例,且仅用以方便、清晰地达到辅助说明本实施例的目的。
请参阅图1,本发明的一实施例中,钴阻挡层的形成属于后段金属互连工艺,钴阻挡层的形成方法,在表面具有金属互连线和线间介质层的半导体器件衬底上进行,其包括以下步骤:
步骤01:请参阅图2,采用原子层沉积工艺将介质03沉积到线间介质层01表面,使线间介质层01表面致密化;
具体的,本实施例中,在金属互连线的化学机械研磨工艺之后,采用原子层沉积方法来沉积介质。介质也同时沉积在金属互连线02表面。由于后段金属互连工艺的温度限制,采用等离子体增强原子层沉积工艺,沉积温度为50~400℃;该沉积过程可以但不限于包括:前驱物吸附在线间介质层表面、惰性气体吹扫所沉积的介质、等离子体清洗所沉积的介质的循环过程;为了降低等离子体对线间介质层的损伤,在原子层沉积过程中,可以降低衬底的温度,如,衬底温度为50℃,降低所采用的射频能量,以及采用低氧化性反应气体,如二氧化碳。所沉积的介质可以为氧化硅,氧化硅的厚度为10~50A。在此过程中,由于反应前驱物会进入线间介质层表面的空隙中,空隙里生长该种介质,导致线间介质层的表层被致密化。被致密化的部分k值会升高,但是由于致密化的表层很薄,所以基本不会造成整体k值的明显升高。当然,也可以采用原子层沉积工艺来沉积其它介质,只要这种介质不会导致线间介质层的k值显著升高,就可以应用于本发明中。
本实施例中,线间介质层01为多孔low-k材料;介质03渗透到多孔low-k材料里,使多孔low-k材料表面致密化。
步骤02:请参阅图3,去除所沉积的介质03,暴露出线间介质层01的致密化的表面和金属互连线02;
具体的,去除介质的方法可以但不限于采用等离子体干法刻蚀工艺;在去除所沉积的介质时,保留线间介质层致密化的表面。本实施例中,所沉积的介质为氧化硅,此时,可以采用硅钴镍工艺来刻蚀去除氧化硅薄膜,关于硅钴镍工艺的具体刻蚀步骤,可以采用现有的工艺,本发明对此不再赘述。当然,本发明的其它实施例中,也可以采用其它刻蚀方式。
本实施例中,在步骤02之后,且在步骤03之前,包括:采用还原性等离子体处理金属互连线表面和线间介质层表面。还原性等离子体可以为H等离子体,从而可以还原金属互连线表面的氧化态金属,并且,可以对线间介质层进行一定程度的修复,从而降低线间介质层的k值。例如,对于铜金属互连线,在前面的沉积过程或去除过程中,可能被氧化成氧化铜,采用H等离子体处理铜金属互连线表面可以将氧化铜还原为铜金属;而且,H等离子体处理多孔low-k材料表面,可以修复多孔low-k因上述的沉积过程或去除过程所造成的损伤,进一步降低k值。
步骤03:请参阅图4,钴选择性地沉积到金属互连线02表面,从而形成钴阻挡层04。
具体的,采用化学气相沉积法来沉积钴阻挡层,由于线间介质层表面得到致密化,钴的沉积将表现出良好的选择性,钴选择性地沉积到金属互连线表面,而在线间介质层表面沉积的很少,从而提高了钴的沉积选择性;钴阻挡层的厚度可以为20~100A。
本发明还提供了一种金属互连工艺,其包括:
首先,形成前段金属互连线和线间介质层;这里,可以采用常规工艺,本发明对此不再赘述。
然后,采用上述的钴阻挡层的形成方法,在前段金属互连线表面形成钴阻挡层;
接着,在钴阻挡层和线间介质层表面形成扩散阻挡层;扩散阻挡层的材料可以为氮掺杂碳化硅,其厚度可以为50~200A。这里,可以采用常规工艺,本发明对此不再赘述。
最后,在扩散阻挡层上形成后段金属互连线。
本发明的一实施例中,金属互连线的形成方法包括以下步骤:
步骤201:在半导体器件衬底上依次沉积第一阻挡层和low-k材料;
具体的,半导体器件衬底可以但不限于为完成前段互连工艺之后的衬底;半导体器件衬底包括前段互连工艺形成多孔low-k材料、第一沟槽和其内的填充金属,在第一沟槽内壁还具有扩散阻挡层例如Ta/TaN,填充金属形成于扩散阻挡层表面;本步骤201中的low-k材料在PECVD反应腔中形成,其反应物包括甲基二乙氧基硅烷(mDEOS)和α-萜品烯(ATRP),其中,ATRP为制孔剂,反应温度为200~400℃,所沉积的low-k材料的厚度为1000~5000A。需要说明的是,本发明中的半导体器件衬底可以为任意半导体衬底,只要是进行多孔low-k材料的互连工艺的半导体器件衬底均可以应用于本发明中。
步骤202:对所沉积的low-k材料进行第一紫外固化工艺;
具体的,经第一紫外固化工艺之后形成low-k材料;第一紫外固化工艺所采用的固化温度为300~400℃,固化时间根据low-k材料的厚度来设定,例如为100~1000S。本发明要通过第一紫外固化工艺实现low-k材料的较高的孔隙率和较低的k值,以及较高的机械强度,如果第一紫外固化工艺的时间过短,则不能达到此效果;因此,在本发明的一些实施例中,第一紫外固化工艺的固化时间大于第二紫外固化工艺的固化时间。在本实施例中,第一紫外固化工艺的固化时间为第一紫外固化工艺和第二紫外固化工艺的时间总和的80%~95%。这样,在本实施例中的第一紫外固化工艺中,low-k材料仍然会产生收缩,但是,第一紫外固化工艺中的收缩程度小于将low-k材料一次彻底固化的收缩程度。第一紫外固化工艺可以包括多个紫外固化过程,比如,采用不同的固化温度等。
步骤203:经光刻和刻蚀工艺,在low-k材料中形成第二沟槽,并将第二沟槽底部的第一阻挡层刻蚀掉,以暴露第一沟槽中的填充金属;
具体的,首先,经光刻和刻蚀形成第二沟槽;然后,在形成的第二沟槽的内壁和底部沉积扩散阻挡层例如Ta/TaN;接着,刻蚀掉第二沟槽底部的第一阻挡层03部分;具体的工艺可以采用常规工艺来完成,这里不再赘述。
步骤204:在第二沟槽中进行金属填充,然后对所填充的金属进行化学机械研磨至low-k材料表面;
具体的,可以采用铜电镀工艺在第二沟槽中沉积金属铜;本步骤中还采用化学机械研磨掉部分low-k材料;本实施例中,化学机械研磨之后,low-k材料的厚度为1200~1800A。这里,第一沟槽及其内的填充金属和第二沟槽及其内的填充金属构成互连通孔;
步骤205:对low-k材料进行第二紫外固化工艺,以形成多孔low-k材料;
具体的,第二紫外固化工艺中,采用的固化温度为300~400℃;第二紫外固化工艺将low-k材料中的制孔剂彻底排出,由于互连通孔的存在,对low-k材料起到支撑作用,使其不能发生收缩;而致孔剂析出和交联反应依然会进行,这意味着low-k材料将得到更高的孔隙率和更低的k值。本实施例中,第二紫外固化工艺所采用的时间为第一紫外固化工艺时间与第二紫外固化工艺时间总和的5~20%。第二紫外固化工艺可以包括多个紫外固化过程,例如,可以采用不同的固化温度等。
步骤06:在多孔low-k材料表面和所填充的金属表面沉积第二阻挡层。
具体的,第二阻挡层的材料可以但不限于为氮掺杂碳化硅。
综上所述,本发明的一种钴阻挡层的形成方法和金属互连工艺,利用钴对致密度大的介质表面的沉积选择性较高的特点,采用原子层沉积方法将介质沉积在线间介质层表面,从而使线间介质层表面致密化,提高了钴在金属互连线和线间介质层表面之间的沉积选择性,从而降低了金属互连线之间的漏电流,提高了产品良率和可靠性。
虽然本发明已以较佳实施例揭示如上,然所述实施例仅为了便于说明而举例而已,并非用以限定本发明,本领域的技术人员在不脱离本发明精神和范围的前提下可作若干的更动与润饰,本发明所主张的保护范围应以权利要求书所述为准。
Claims (10)
1.一种钴阻挡层的形成方法,在表面具有金属互连线和线间介质层的半导体器件衬底上进行,其特征在于,包括以下步骤:
步骤01:采用原子层沉积工艺将介质沉积到所述线间介质层和金属互连线表面,同时,所述介质进入所述线间介质层表面的空隙中,使所述线间介质层表面致密化;
步骤02:去除沉积到所述线间介质层和金属互连线表面的介质,暴露出所述线间介质层的致密化的表面和所述金属互连线;
步骤03:钴选择性地沉积到所述金属互连线表面,从而形成钴阻挡层。
2.根据权利要求1所述的钴阻挡层的形成方法,其特征在于,在所述步骤02之后,且在所述步骤03之前,包括:采用还原性等离子体处理所述金属互连线表面和所述线间介质层表面。
3.根据权利要求1所述的钴阻挡层的形成方法,其特征在于,所述线间介质层为多孔low-k材料。
4.根据权利要求3所述的钴阻挡层的形成方法,其特征在于,所述步骤01中,所述介质渗透到所述多孔low-k材料里,使所述多孔low-k材料表面致密化。
5.根据权利要求1所述的钴阻挡层的形成方法,其特征在于,所述步骤01中,所述原子层沉积工艺为等离子体增强原子层沉积工艺。
6.根据权利要求5所述的钴阻挡层的形成方法,其特征在于,在原子层沉积过程中,降低所述衬底的温度,降低所采用的射频能量,采用低氧化性反应气体。
7.根据权利要求5所述的钴阻挡层的形成方法,其特征在于,在原子层沉积过程中,所采用的反应气体为二氧化碳。
8.根据权利要求1所述的钴阻挡层的形成方法,其特征在于,所述介质为氧化硅。
9.根据权利要求1所述的钴阻挡层的形成方法,其特征在于,所述步骤03中,采用化学气相沉积法来沉积所述钴阻挡层。
10.一种金属互连工艺,其特征在于,包括:
首先形成前段金属互连线和线间介质层;
然后,采用权利要求1的钴阻挡层的形成方法,在所述前段金属互连线表面形成钴阻挡层;
接着,在所述钴阻挡层和所述线间介质层表面形成扩散阻挡层;
最后,在所述扩散阻挡层上形成后段金属互连线。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7605082B1 (en) * | 2005-10-13 | 2009-10-20 | Novellus Systems, Inc. | Capping before barrier-removal IC fabrication method |
CN102623395A (zh) * | 2012-03-22 | 2012-08-01 | 上海华力微电子有限公司 | 一种低介电常数薄膜表面处理方法 |
CN102881677A (zh) * | 2012-09-24 | 2013-01-16 | 复旦大学 | 一种用于铜互连的合金抗铜扩散阻挡层及其制造方法 |
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CN104347476A (zh) * | 2013-07-23 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
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US20050287826A1 (en) * | 2004-06-29 | 2005-12-29 | Abell Thomas J | Method of sealing low-k dielectrics and devices made thereby |
US7521358B2 (en) * | 2006-12-26 | 2009-04-21 | Lam Research Corporation | Process integration scheme to lower overall dielectric constant in BEoL interconnect structures |
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