CN104733299B - 交错地形成镍硅和镍锗结构 - Google Patents

交错地形成镍硅和镍锗结构 Download PDF

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CN104733299B
CN104733299B CN201410281111.4A CN201410281111A CN104733299B CN 104733299 B CN104733299 B CN 104733299B CN 201410281111 A CN201410281111 A CN 201410281111A CN 104733299 B CN104733299 B CN 104733299B
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drain contact
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CN104733299A (zh
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刘继文
王昭雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及交错地形成镍硅和镍锗结构。本发明提供了用于在单个半导体衬底上产生半导体器件的系统和方法。产生的单个半导体衬底包括硅材料部分和锗材料部分。由第一金属在硅材料部分上形成第一组源极/漏极接触件。在第一温度下使用硅材料部分对第一组源极/漏极接触件进行退火。在将半导体衬底加热到第一温度之后，由第二金属在锗材料部分上形成第二组源极/漏极接触件，以及在第二温度下使用锗材料部分对第二组源极/漏极接触件进行退火，其中，第二温度小于第一温度。

Description

交错地形成镍硅和镍锗结构
技术领域
本发明中描述的技术通常涉及半导体器件制造，更具体地，涉及多层结构。
背景技术
非平面晶体管结构提供了在较小占地面积(footprint)的情况下获得高器件性能的方式。这种结构的制造经常被用于产生这些结构的物质的材料性质所限制。以特定的顺序实施组件规划，可以增加通过避免一些组件规划冲突可以获得的可用半导体配置的选单。
发明内容
为了解决现有技术中所存在的缺陷，提供了一种在单个半导体衬底上产生半导体器件的方法，包括：产生包括硅材料部分和锗材料部分的单个半导体衬底；由第一金属在所述硅材料部分上形成第一组源极/漏极接触件；在第一温度下使用所述硅材料部分对所述第一组源极/漏极接触件进行退火；在将所述半导体衬底加热到所述第一温度之后，由第二金属在所述锗材料部分上形成第二组源极/漏极接触件；以及在第二温度下使用所述锗材料部分对所述第二组源极/漏极接触件进行退火，其中，所述第二温度小于所述第一温度。
根据本发明的一个实施例，所述第一金属和所述第二金属为相同类型。
根据本发明的一个实施例，所述第一金属和所述第二金属都包括镍。
根据本发明的一个实施例，所述第一温度在400℃至600℃的范围内。
根据本发明的一个实施例，所述第二温度在250℃至300℃的范围内。
根据本发明的一个实施例，在所述单个半导体衬底的高于形成所述第一组源极/漏极接触件的水平面处形成所述第二组源极/漏极接触件。
根据本发明的一个实施例，在所述单个半导体衬底的与形成所述第一组源极/漏极接触件相同的水平面处形成所述第二组源极/漏极接触件。
根据本发明的一个实施例，所述硅材料部分是硅衬底的一部分，所述锗材料部分形成在所述硅衬底的顶部上。
根据本发明的一个实施例，所述硅材料部分上的所述第一组源极/漏极接触件是NMOS晶体管的组件，其中，所述锗材料部分上的所述第二组源极/漏极接触件是PMOS晶体管的组件。
根据本发明的一个实施例，该方法还包括去除所述第一金属或所述第二金属的未反应的部分。
根据本发明的一个实施例，该方法还包括在所述硅材料部分和所述锗材料部分的每一个上形成介电层和栅电极，以在所述单个半导体衬底上形成两个晶体管。
根据本发明的另一方面，提供了一种在单个半导体衬底上形成的半导体器件，包括：单个半导体衬底，所述单个半导体衬底包括硅材料部分和锗材料部分；第一组源极/漏极接触件，由第一金属在所述硅材料部分上形成，其中，在第一温度下使用所述硅材料部分对所述第一组源极/漏极接触件进行退火；以及第二组源极/漏极接触件，由第二金属在所述锗材料部分上形成，其中，在将所述半导体衬底加热到所述第一温度之后，形成所述第二组源极/漏极接触件，其中，在小于所述第一温度的第二温度下使用所述锗材料部分对所述第二组源极/漏极接触件进行退火。
根据本发明的一个实施例，所述第一金属和所述第二金属为相同类型。
根据本发明的一个实施例，所述第一金属和所述第二金属都包括镍。
根据本发明的一个实施例，所述第一温度在400℃至600℃的范围内。
根据本发明的一个实施例，所述第二温度在250℃至300℃的范围内。
根据本发明的一个实施例，所述第二组源极/漏极接触件设置在所述单个半导体衬底的高于所述第一组源极/漏极接触件的水平面处。
根据本发明的一个实施例，所述第二组源极/漏极接触件设置在所述单个半导体衬底的与所述第一组源极/漏极接触件相同的水平面处。
根据本发明的一个实施例，所述硅材料部分是硅衬底的一部分，所述锗材料部分形成在所述硅衬底的顶部上。
根据本发明的一个实施例，所述硅材料部分上的所述第一组源极/漏极接触件是NMOS晶体管的组件，其中，所述锗材料部分上的所述第二组源极/漏极接触件是PMOS晶体管的组件。
附图说明
图1是示出单个半导体衬底上的光敏层的图案化的示意图。
图2示出了在材料去除过程和剥离光敏层之后的半导体器件。
图3示出了在掺入介电层之后的半导体器件。
图4示出了在掺入栅极介电材料之后的半导体器件。
图5示出了位于半导体器件的NMOS部分上的栅极的形成。
图6示出了位于NMOS晶体管的源极/漏极区上的镍硅化物的形成。
图7示出了位于NMOS晶体管层之上的层间电介质的形成。
图8示出了用于制造PMOS晶体管组件的开口的形成。
图9示出了额外的半导体材料的掺入。
图10示出了PMOS晶体管的栅极叠层的形成。
图11示出了位于PMOS晶体管的源极/漏极区上的镍锗化物的形成。
图12示出了覆盖层间电介质的掺入。
图13是示出在单个半导体衬底上产生半导体器件的方法的流程图。
具体实施方式
当设计半导体制造工艺时，一些材料性质限制了形成不同结构的能力。例如，一些半导体结构制造工艺需要将半导体结构暴露于特定的温度水平(例如，不同材料之间的退火工艺需要不同的形成温度)下。当一些结构需要高温时，其他结构由于暴露于那些高温下可以潜在地被损坏。组件制造的策略顺序避免了一些组件规划冲突且扩大了可用半导体配置的组。
下图描述了一个实例，其中，半导体器件100形成在单个半导体衬底102上，该半导体器件100包括具有镍硅化物源极/漏极接触件126的NMOS晶体管104和具有镍锗化物源极/漏极接触件150的PMOS晶体管106(在图1至图12中示出)。以下工艺使这些结构能够形成，尽管用于PMOS晶体管106的镍锗化物的形成温度(250℃至300℃)远远低于用于PMOS晶体管104的镍硅化物的形成温度(400℃至600℃)。
图1是示出单个半导体衬底上的光敏层的图案化的示意图。将硅衬底102划分为分别用于形成NMOS晶体管104和PMOS晶体管106的区104、106。缓冲层(例如，SiO2)108和硬掩模(例如，Si3N4)110形成在硅衬底102上，光敏层(例如，光刻胶)112布置在区104、106的部分上方以在材料去除过程期间(例如，湿蚀刻、干蚀刻)保护下方的层。
图2示出了在材料去除过程和剥离光敏层112之后的半导体器件100。材料去除过程消除了硅衬底102、缓冲层108和硬掩模110的未受到光敏层112(现在已经从半导体材料100剥离)保护的一些部分。材料去除过程在硅衬底102内产生一些凹进区114。
图3示出了在掺入介电层之后的半导体器件100。材料去除过程之后，用诸如SiO2的介电材料116填充硅衬底102的凹进区。去除硬掩模110和缓冲层108(例如，通过化学机械抛光/平坦化(CMP)工艺)，留下具有相关联的凹进区(包含介电材料116)的硅衬底102。
图4示出了在掺入栅极介电材料之后的半导体器件100。用介电材料116填充硅衬底102的凹进区114之后，在硅衬底102和介电材料116的顶部上形成栅极介电材料118。栅极介电材料118由SiO2或诸如HfO2的高k材料形成。
图5示出了位于半导体器件100的NMOS部分104上的栅极的形成。从半导体器件100的NMOS部分104去除部分栅极电介质118，在硅衬底102的左侧凸起部分留下较小的栅极电介质部分118。栅电极(例如，Al、TiAl、W、TiN、TaN)120沉积在剩余的NMOS侧栅极电介质118上以形成栅极叠层122。栅极叠层122由间隔层材料124(例如，SiO2、Si3N4)环绕。对栅极叠层122的最接近的左侧和右侧实施注入工艺形成的NMOS凸起硅衬底部分的区域被指定为NMOS晶体管104的源极/漏极区126。
图6示出了位于NMOS晶体管104的源极/漏极区上的镍硅化物的形成。在一个实施例中，以阶梯状在源极/漏极区126上形成镍硅化物接触件128。在该实例中，在硅衬底102的源极/漏极区126上形成镍金属层，以形成第一组源极/漏极接触件128。在第一温度(例如，400℃至600℃)下使用源极/漏极区126的硅材料对第一组源极/漏极接触件128进行退火，以形成镍硅化物。然后去除未反应的镍，留下镍硅化物源极/漏极接触件128。
图7至图12示出了在半导体器件100的不同于NMOS晶体管104的水平面处位于单个半导体衬底102的PMOS区106上的PMOS晶体管106的组件的形成。在本发明的其他实施例中，NMOS晶体管104和PMOS晶体管106形成在半导体器件100的相同或附近的层上。
图7示出了位于NMOS晶体管层之上的层间电介质的形成。在源极/漏极接触件128和栅电极120上制造多个接触件延伸部(例如，Al、Cu、W、TiN、TaN)130，以使从半导体器件100的较高层能够连接到那些接触件128和电极120。由诸如SiO2或PSG的材料在其他组件的顶部上形成层间电介质(ILD1)132。
图8示出了用于制造PMOS晶体管组件的开口的形成。在图8中，由诸如SiO2或PSG的材料形成第二层间电介质(ILD2)134。而且，在半导体器件100的PMOS区106中形成开口136(例如，通过湿法蚀刻或干法蚀刻)，诸如，深度至硅衬底102。
图9示出了额外的半导体材料的掺入。在图9中，用诸如含锗材料(例如，Ge、SiGe)的半导体材料138填充在图8中的ILD1132和ILD2134中形成的开口。在一个实施例中，用化学机械抛光/平坦化(CMP)工艺进一步处理半导体材料138的顶部。
图10示出了PMOS晶体管106的栅极叠层的形成。栅极电介质(例如，SiO2或其他高k材料)140形成在含锗材料138上，并且进一步在栅极电介质140上形成栅电极(例如，W、TiN、TaN)142以产生栅极叠层144。栅极叠层144由间隔层材料(例如，SiO2、Si3N4)146环绕，并且通过对间隔层环绕的栅极叠层144的左侧和右侧实施注入工艺形成的含锗材料的区域被指定为PMOS晶体管的源极/漏极区148。
图11示出了位于PMOS晶体管106的源极/漏极区上的镍锗化物的形成。在一个实施例中，以阶梯状在源极/漏极区148上形成镍锗化物接触件150。在那个实例中，在含锗材料138的源极/漏极区148上形成镍金属层，以形成第二组源极/漏极接触件150(NMOS源极/漏极接触件128为第一组)。在第二温度(例如，250℃至300℃)下使用源极/漏极区148的锗材料对第二组源极/漏极接触件150实施退火以形成镍锗化物。然后去除未反应的镍，留下镍锗化物源极/漏极接触件150。然后，在第三温度(例如，600℃至750℃)下对衬底102退火以形成低电阻镍硅化物和低电阻镍锗化物。
在形成镍锗化物的退火工艺中使用的第二温度(例如，250℃至300℃)小于用于形成128中的镍硅化物的第一温度(例如，400℃至600℃)。通过按所述顺序实施操作，镍锗化物接触件150不再经受在用于形成128中的镍硅化物的退火工艺中使用的第一温度，其中，镍锗化物接触件150在暴露于这样的温度时可以被损坏。
图12示出了覆盖层间电介质的掺入。用于相应的NMOS和PMOS晶体管的源极/漏极区和栅极的每一个的接触件(例如，Al、Cu、W、TiN、TaN)152延伸穿过第二层间电介质134，其中这是必要的且要延伸超出第二层间电介质。围绕接触件152形成额外的第三层间电介质(ILD3)154(由诸如SiO2或PSG的电介质形成)，以产生均一的、单个衬底的半导体器件。
图13是示出在单个半导体衬底上产生半导体器件的方法的流程图。在步骤1302中，产生了包括硅材料部分和锗材料部分的单个半导体衬底。在步骤1304中，由第一金属在硅材料部分上形成第一组源极/漏极接触件。在步骤1306中，在第一温度下使用硅材料部分对第一组源极/漏极接触件进行退火。在步骤1308中，在将半导体衬底加热到第一温度之后，由第二金属在锗材料部分上形成第二组源极/漏极接触件，以及在步骤1310中，在第二温度下使用锗材料部分对第二组源极/漏极接触件进行退火，其中，第二温度小于第一温度。
该书面说明书使用实例以公开本发明，包括最好的模式，并且也使本领域的技术人员能够制造和使用本发明。本发明的可取得专利权的范围可以包括本领域的技术人员可以想到的其他实例。例如，一些系统或方法包括额外的步骤以形成互连件以及用于钝化。
作为另一实例，在单个半导体衬底上产生半导体器件的方法中，产生了包括硅材料部分和锗材料部分的单个半导体衬底。由第一金属在硅材料部分上形成第一组源极/漏极接触件。在第一温度下使用硅材料部分对第一组源极/漏极接触件进行退火。在将半导体衬底加热到第一温度之后，由第二金属在锗材料部分上形成第二组源极/漏极接触件，以及在第二温度下使用锗材料部分对第二组源极/漏极接触件进行退火，其中，第二温度小于第一温度。
作为又一实例，在单个半导体衬底上形成的半导体器件包括具有硅材料部分和锗材料部分的单个半导体衬底。由第一金属在硅材料部分上形成第一组源极/漏极接触件，其中，在第一温度下使用硅材料部分对第一组源极/漏极接触件进行退火。由第二金属在锗材料部分上形成第二组源极/漏极接触件，其中，在将半导体衬底加热到第一温度之后，形成第二组源极/漏极接触件，其中，在小于第一温度的第二温度下使用锗材料部分对第二组源极/漏极接触件进行退火。
相关领域内的技术人员将认识到可以在没有一个或多个具体细节的情况下，或具有其他替换和/或额外的方法、材料或组件的情况下实施各个实施例。可能没有详细示出或描述众所周知的结构、材料或操作以避免模糊本发明的各个实施例的各方面。图中所示的各个实施例是说明性实例代表且没必要按比例进行绘制。在一个或多个实施例中，可以以任何合适的方式结合具体的部件、结构、材料或性质。在其他实施例中，可以包括各个额外的层和/或结构，和/或可以省略描述的部件。以最有助于理解本发明的方式，将各个操作描述为依次的多个不连续的操作。然而，描述的顺序不应该被解释为暗示这些操作必须是根据该顺序。特别地，这些操作不必以呈现的顺序实施。在此描述的操作可以以不同于所述实施例的顺序(顺序或并行)实施。可以实施和/或描述各个额外的操作。在额外的实施例中可以省略一些操作。
该书面说明书和以下权利要求可以包括仅用于描述性目的而不被解释为限制的术语(诸如，左、右、顶部、底部、在…上方、在…下方、上面的、下面的、第一、第二等)。例如，指定相对垂直位置的术语可以指位置，其中，衬底或集成电路的器件侧(或有源表面)是该衬底的“顶”面；该衬底实际上可以是任何方位，使得在标准的地球参考框架中衬底的“顶”侧可以低于“底”侧，且还可以属于术语“顶部”的意思。除非特别说明，在此(包括权利要求中)使用的术语“在…上”可以不指“第一层在第二层上”是直接位于第二层上且与第二层直接接触；在第一层和第二层(位于第一层上)之间可以有第三层或其他结构。在此描述的器件或物品的实施例可以以许多位置和方位制造、使用或运输。本领域的技术人员将认识到用于图中示出的各种组件的各种等同的组合和替代。

Claims (20)

1.一种在单个半导体衬底上生成半导体器件的方法，包括：
生成包括硅材料部分的单个半导体衬底；
由第一金属在所述硅材料部分上形成第一组源极/漏极接触件；
在第一温度下使用所述硅材料部分对所述第一组源极/漏极接触件进行退火；
在所述第一温度的退火完成后，在所述单个半导体衬底上邻近所述硅材料部分处沉积锗材料部分；
由第二金属在所述锗材料部分上形成第二组源极/漏极接触件；以及
在第二温度下使用所述锗材料部分对所述第二组源极/漏极接触件进行退火，其中，所述第二温度小于所述第一温度。
2.根据权利要求1所述的方法，其中，所述第一金属和所述第二金属为相同类型。
3.根据权利要求2所述的方法，其中，所述第一金属和所述第二金属都包括镍。
4.根据权利要求1所述的方法，其中，所述第一温度在400℃至600℃的范围内。
5.根据权利要求1所述的方法，其中，所述第二温度在250℃至300℃的范围内。
6.根据权利要求1所述的方法，其中，在所述单个半导体衬底的高于形成所述第一组源极/漏极接触件的水平面处形成所述第二组源极/漏极接触件。
7.根据权利要求1所述的方法，其中，在所述单个半导体衬底的与形成所述第一组源极/漏极接触件相同的水平面处形成所述第二组源极/漏极接触件。
8.根据权利要求1所述的方法，其中，所述硅材料部分是硅衬底的一部分，所述锗材料部分形成在所述硅衬底的顶部上。
9.根据权利要求1所述的方法，其中，所述硅材料部分上的所述第一组源极/漏极接触件是NMOS晶体管的组件，其中，所述锗材料部分上的所述第二组源极/漏极接触件是PMOS晶体管的组件。
10.根据权利要求1所述的方法，还包括去除所述第一金属或所述第二金属的未反应的部分。
11.根据权利要求1所述的方法，还包括在所述硅材料部分和所述锗材料部分的每一个上形成介电层和栅电极，以在所述单个半导体衬底上形成两个晶体管。
12.一种在单个半导体衬底上形成的半导体器件，包括：
单个半导体衬底，所述单个半导体衬底包括硅材料部分和锗材料部分；
第一组源极/漏极接触件，由第一金属在所述硅材料部分上形成，其中，在第一温度下使用所述硅材料部分对所述第一组源极/漏极接触件进行退火；以及
第二组源极/漏极接触件，由第二金属在所述锗材料部分上形成，其中，在所述第一温度的退火之后，形成所述第二组源极/漏极接触件，其中，在小于所述第一温度的第二温度下使用所述锗材料部分对所述第二组源极/漏极接触件进行退火。
13.根据权利要求12所述的器件，其中，所述第一金属和所述第二金属为相同类型。
14.根据权利要求13所述的器件，其中，所述第一金属和所述第二金属都包括镍。
15.根据权利要求12所述的器件，其中，所述第一温度在400℃至600℃的范围内。
16.根据权利要求12所述的器件，其中，所述第二温度在250℃至300℃的范围内。
17.根据权利要求12所述的器件，其中，所述第二组源极/漏极接触件设置在所述单个半导体衬底的高于所述第一组源极/漏极接触件的水平面处。
18.根据权利要求12所述的器件，其中，所述第二组源极/漏极接触件设置在所述单个半导体衬底的与所述第一组源极/漏极接触件相同的水平面处。
19.根据权利要求12所述的器件，其中，所述硅材料部分是硅衬底的一部分，所述锗材料部分形成在所述硅衬底的顶部上。
20.根据权利要求12所述的器件，其中，所述硅材料部分上的所述第一组源极/漏极接触件是NMOS晶体管的组件，其中，所述锗材料部分上的所述第二组源极/漏极接触件是PMOS晶体管的组件。
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