CN106505096B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN106505096B
CN106505096B CN201610595157.2A CN201610595157A CN106505096B CN 106505096 B CN106505096 B CN 106505096B CN 201610595157 A CN201610595157 A CN 201610595157A CN 106505096 B CN106505096 B CN 106505096B
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fin
semiconductor fin
semiconductor
substrate
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CN106505096A (zh
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李智圣
黄信杰
刘继文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括：衬底、至少一个有源半导体鳍、至少一个第一伪半导体鳍、以及至少一个第二伪半导体鳍。在衬底上设置有源半导体鳍。在衬底上设置第一伪半导体鳍。在衬底上且在有源半导体鳍和第一伪半导体鳍之间设置第二伪半导体鳍。第一伪半导体鳍的顶面和第二伪半导体鳍的顶面在不同的方向上弯曲。本发明的实施例还涉及半导体器件的制造方法。

Description

半导体器件及其制造方法
优先权声明和交叉引用
本申请要求2015年9月4日提交的美国临时申请第62/214,770号的优先权，其内容结合于此作为参考。
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及半导体器件及其制造方法。
背景技术
半导体集成电路(IC)产业经历了指数式增长。IC材料和设计的技术进步产生了多代IC，其中，每代都具有比前一代更小且更复杂的电路。在IC发展过程中，功能密度(即每芯片面积上互连器件的数量)通常增大了而几何尺寸(即，使用制造工艺可以做出的最小的元件(或线))减小了。这种按比例缩小工艺通常通过增加生产效率和降低相关成本来提供很多益处。
这种按比例缩小工艺还增加了处理和制造IC的复杂性并且，为了实现这些进步，需要IC处理和制造方面的相似进步。例如，已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管以代替平面晶体管。鳍式晶体管具有与顶面和相对的两个侧壁相关联的沟道(称为鳍沟道)。鳍沟道的总沟道宽度通过顶面和相对的两个侧壁限定。
发明内容
本发明的实施例提供了一种半导体器件，包括：衬底；至少一个有源半导体鳍，设置在所述衬底上；至少一个第一伪半导体鳍，设置在所述衬底上；以及至少一个第二伪半导体鳍，设置在所述衬底上以及所述有源半导体鳍和所述第一伪半导体鳍之间，其中，所述第一伪半导体鳍的顶面和所述第二伪半导体鳍的顶面在不同方向上弯曲。
本发明的另一实施例提供了一种半导体器件，包括：衬底；至少一个有源半导体鳍，设置在所述衬底上；多个第一伪半导体鳍，设置在所述衬底上，其中，所述第一伪半导体鳍的顶面形成凹面轮廓；以及至少一个第二伪半导体鳍，设置在所述衬底上以及在所述有源半导体鳍和所述第一伪半导体鳍之间，其中，所述第二伪半导体鳍的顶面是非凹面的。
本发明的又一实施例提供了一种用于制造半导体鳍的方法，包括：在衬底上形成至少一个有源半导体鳍、至少一个第一伪半导体鳍以及至少一个第二伪半导体鳍，其中，所述第二伪半导体鳍设置在所述有源半导体鳍和所述第一伪半导体鳍之间；去除所述第二伪半导体鳍的至少部分；以及在去除所述第二伪半导体鳍的所述部分之后去除所述第一伪半导体鳍的至少部分。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1A至图1H是根据本发明的一些实施例的用于制造半导体器件的方法在各个阶段的截面图。
图2是根据本发明一些实施例的半导体器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
可以从本申请的一个或多个实施例改善的器件的实例是半导体器件。例如，这样的器件是FinFET器件。例如，FinFET器件可以是包括至少一个P型金属氧化物半导体(PMOS)FinFET器件和至少一个N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。以下公开内容将继续以FinFET实例来说明本申请的各个实施例。然而，应该理解，本申请不应限制于特定类型的器件。
图1A至图1H是根据本发明的一些实施例的用于制造半导体器件的方法在各个阶段的截面图。参考图1A。提供衬底110。衬底110具有至少一个有源区域102和至少一个伪区域104。例如，在图1A中，衬底110具有两个有源区域102和一个伪区域104，以及伪区域104存在于两个有源区域102之间。在一些实施例中，衬底110包括硅。可选地，衬底110可以包括锗、硅锗、砷化镓或其他适当的半导体材料。同样可选地，衬底110可以包括外延层。例如，衬底110可以具有位于块状半导体上面的外延层。此外，衬底110可以被应变以用于性能增强。例如，外延层可以包括与块状半导体的那些材料不同的半导体材料，诸如位于块状硅上面的硅锗层或者位于块状硅锗上面的硅层。可以通过选择性外延生长(SEG)形成这样的应变的衬底。此外，衬底110可以包括绝缘体上半导体(SOI)结构。同样可选地，衬底110可以包括诸如通过注氧隔离(SIMOX)技术、晶圆接合、SEG或其他适当的方法形成的诸如埋氧(BOX)层的掩埋介电层。
在衬底110上形成衬垫层122和掩模层124。衬垫层122包括诸如氧化硅、氮化硅、氮氧化硅、或任何其他合适的介电材料的介电材料。掩模层124包括诸如氧化硅、氮化硅、氮氧化硅、或任何其他合适的介电材料的介电材料。在一些实施例中，掩模层124是硬掩模层。在一些实施例中，衬垫层122是在衬底110上沉积的氧化硅层，以及掩模层124是在衬垫层122上沉积的氮化硅层。可以通过热氧化、化学氧化、原子层沉积(ALD)或任何其他适合的方法形成衬垫层122和掩模层124。在一些实施例中，衬垫层122的厚度可以在约100埃至800埃之间，以及掩模层124的厚度可以在约200埃至2000埃之间。
实施在半导体衬底110上限定半导体鳍的光刻工艺。在一些实施例中，可以使用三层光刻胶130，包括作为顶部或最上部的光刻胶(PR)层132，中间层134、和底层136。在掩模层124上设置三层光刻胶130。三层光刻胶130提供PR层132、可以包括抗反射层或背面抗反射层以帮助PR处理的曝光和聚焦的中间层134、以及可以是例如氮化物的硬掩模材料的底层136。为了图案化三层光刻胶130，通过使用掩模，曝露于诸如光或准分子激光的辐射，通过例如烘烤或固化操作以硬化光刻胶，并且根据使用的是正性光刻胶还是负性光刻胶，使用显影剂去除光刻胶的暴露部分或未暴露部分以在PR层132中形成来自掩模的图案，来图案化PR层132。然后，使用图案化的PR层132以蚀刻下面的中间层134和底层136以为目标层(此处为掩模层124)形成蚀刻掩模。
参考图1B。实施沟槽蚀刻以形成图案化的掩模层124'。在沟槽蚀刻期间，将图案化的PR层132(见图1A)用作掩模。在沟槽蚀刻中，可以通过包括干蚀刻、湿蚀刻或干蚀刻和湿蚀刻的组合的各种方法蚀刻中间层134、底层136以及掩模层124(见图1A)。可以使用含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，C12、CHCl3、CC14、和/或BC13)、含溴气体(例如，HBr和/或CHBr3)、含氧气体、含碘气体、其他合适的气体和/或等离子体或它们的组合来执行干蚀刻工艺。蚀刻工艺可以包括多步蚀刻以获得蚀刻选择性、灵活性和期望的蚀刻轮廓。在图案化掩模层124之后，去除PR层132、中间层134以及底层136。
参考图1C。使用图案化的掩模层124'作为掩模，可以通过包括干蚀刻、湿蚀刻或干蚀刻和湿蚀刻的组合的各种方法蚀刻衬垫层120和衬底110以形成多个半导体鳍。可以使用含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，C12、CHCl3、CC14、和/或BC13)、含溴气体(例如，HBr和/或CHBr3)、含氧气体、含碘气体、其他合适的气体和/或等离子体或它们的组合来执行干蚀刻工艺。蚀刻工艺可以包括多步蚀刻以获得蚀刻选择性、灵活性和期望的蚀刻轮廓。
在图1C中，半导体鳍包括至少一个有源半导体鳍112、至少一个第一伪半导体鳍114、以及至少一个第二伪半导体鳍116。例如，在图1C中，具有六个有源半导体鳍112、四个第一伪半导体鳍114、和两个第二伪半导体鳍116，并且在这方面不限制要求保护的范围。六个有源半导体鳍112分成两组并且分别地设置在两个有源区域102中。在图1C中，在有源区域102的一个中具有三个有源半导体鳍112。在伪区域104中设置第一伪半导体鳍114和第二伪半导体鳍116。换言之，在两组有源半导体鳍112之间设置第一伪半导体鳍114和第二伪半导体鳍116。彼此邻近地设置第一伪半导体鳍114以形成一组，且在第一伪半导体鳍114的一组和有源半导体鳍112的一组之间设置第二伪半导体鳍116中的一个。因此，第一伪半导体鳍114可以称为内部伪半导体鳍，并且第二伪半导体鳍116可以称为外部伪半导体鳍。
第一伪半导体鳍114和第二伪半导体鳍116在半导体器件中没有功能，但是使器件工艺更统一、更可以复制且更可以制造。有源半导体鳍112在半导体器件中具有功能。使第一伪半导体鳍114和第二伪半导体鳍116位于有源半导体鳍112旁边，在非常相似的形成环境下，可以在所有相关的位置中形成有源半导体鳍112。在鳍的临界尺寸(CD)、轮廓和高度方面，相同的形成环境提升了所有相关的位置中的有源半导体鳍112的一致性。
在一些实施例中，有源半导体鳍112的高度H1、第一伪半导体鳍114的高度H2、和第二伪半导体鳍116的高度H3可以为约100nm至约150nm，且在这方面不限制要求保护的范围。
参考图1D。可以使用另一三层光刻胶140，包括作为顶部或最上部的光刻胶(PR)层142、中间层144、和底层146。三层光刻胶140覆盖有源半导体鳍112、第一伪半导体鳍114和第二伪半导体鳍116。三层光刻胶140提供PR层142、可以包括抗反射层或背面抗反射层以帮助PR处理的曝光和聚焦的中间层144、以及可以是例如氮化物的硬掩模材料的底层146。
然后，图案化三层光刻胶140的PR层142。图案化的PR层142暴露出设置在第二伪半导体鳍116上的中间层144的部分。同时，在有源伪半导体鳍112和第一伪半导体鳍114上设置的中间层144的另一部分仍然由PR层142覆盖。为了图案化三层光刻胶140，通过使用掩模，曝露于诸如光或准分子激光的辐射，通过例如烘烤或固化操作以硬化光刻胶，并且根据使用的是正性光刻胶还是负性光刻胶，使用显影剂去除光刻胶的暴露部分或未暴露部分以在PR层142中形成来自掩模的图案，来图案化PR层142。然后，使用图案化的PR层142以蚀刻下面的中间层144和底层146以为目标部件(此处为第二伪半导体鳍116)形成蚀刻掩模。
参考图1E。使用图案化的PR层142(见图1D)作为掩模，可以通过包括干蚀刻、湿蚀刻或干蚀刻和湿蚀刻的组合的各种方法蚀刻三层光刻胶140的中间层144和底层146(见图1D)。此外，去除(或蚀刻)第二伪半导体鳍116的至少部分。可以使用含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，C12、CHCl3、CC14、和/或BC13)、含溴气体(例如，HBr和/或CHBr3)、含氧气体、含碘气体、其他合适的气体和/或等离子体或它们的组合来执行干蚀刻工艺。蚀刻工艺可以包括多步蚀刻以获得蚀刻选择性、灵活性和期望的蚀刻轮廓。在部分地去除第二伪半导体鳍116之后，去除三层光刻胶140的PR层142、中间层144和底层146。
在图1E中，剩余的第二伪半导体鳍116的高度H3a和H3b可以为有源半导体鳍112的高度H1的约17％至约27％。换言之，剩余的第二伪半导体鳍116的高度H3a和H3b为约17nm至约40.5nm。第二伪半导体鳍116中的至少一个具有顶面117a(117b)。顶面117a(117b)可以是非凹面的，诸如凸面的或基本上平的。在一些实施例中，第二伪半导体鳍116的顶面117a(117b)是向外弯曲的。此外，在一些实施例中，两个剩余的第二伪半导体鳍116的高度H3a和H3b是基本上相同的。本文所使用的术语“基本上”可以应用于修改任何数量表示，允许该数量表示在不导致其相关基本功能变化的情况下变化。
参考图1F。仍然可以使用另一三层光刻胶150，包括作为顶部或最上部的光刻胶(PR)层152，中间层154、和底层156。三层光刻胶150覆盖有源半导体鳍112、第一伪半导体鳍114和剩余的第二伪半导体鳍116。三层光刻胶150提供PR层152、可以包括抗反射层或背面抗反射层以帮助PR处理的曝光和聚焦的中间层154、以及可以是例如氮化物的硬掩模材料的底层156。
然后，图案化三层光刻胶150的PR层152。图案化的PR层152暴露出设置在第一伪半导体鳍114上的中间层154的部分。同时，在有源伪半导体鳍112和剩余的第二伪半导体鳍116上设置的中间层154的另一部分仍然由PR层152覆盖。为了图案化三层光刻胶150，通过使用掩模，曝露于诸如光或准分子激光的辐射，通过例如烘烤或固化操作以硬化光刻胶，并且根据使用的是正性光刻胶还是负性光刻胶，使用显影剂去除光刻胶的暴露部分或未暴露部分以在PR层152中形成来自掩模的图案，来图案化PR层152。然后，使用图案化的PR层152以蚀刻下面的中间层154和底层156以为目标部件(此处为第一伪半导体鳍114)形成蚀刻掩模。
参考图1G。使用图案化的PR层152(见图1F)作为掩模，可以通过包括干蚀刻、湿蚀刻或干蚀刻和湿蚀刻的组合的各种方法蚀刻三层光刻胶150的中间层154和底层156(见图1F)。此外，去除(或蚀刻)第一伪半导体鳍114的至少部分。可以使用含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，C12、CHCl3、CC14、和/或BC13)、含溴气体(例如，HBr和/或CHBr3)、含氧气体、含碘气体、其他合适的气体和/或等离子体或它们的组合来执行干蚀刻工艺。蚀刻工艺可以包括多步蚀刻以获得蚀刻选择性、灵活性和期望的蚀刻轮廓。在部分地去除第一伪半导体鳍114之后，去除三层光刻胶150的PR层152、中间层154和底层156。
在图1G中，剩余的第一伪半导体鳍114的高度H2a、H2b、H2c和H2d可以为有源半导体鳍112的高度H1的约6％至约16％。换言之，剩余的第一伪半导体鳍114的高度H2a、H2b、H2c和H2d为约6nm至约24nm。此外，剩余的第二伪半导体鳍116的高度H3a和H3b大于剩余的第一伪半导体鳍114的高度H2a、H2b、H2c和H2d。在一些实施例中，剩余的第一伪半导体鳍114和第二伪半导体鳍116的高度差(即，(H3a或H3b)-(H2a、H2b、H2c或H2d))为约3nm至约30nm，或为有源半导体鳍112的高度H1的约3％至约17％。在一些实施例中，剩余的第一伪半导体鳍114的轮廓是对称的。或者，高度H2a和H2d是基本上相同的，高度H2b和H2c是基本上相同的，且高度H2a和H2d大于高度H2b和H2c，以及在这方面不限制要求保护的范围。本文所使用的术语“基本上”可以应用于修改任何数量表示，允许该数量表示在不导致其相关基本功能变化的情况下变化。
第一伪半导体鳍114分别具有顶面115a、115b、115c和115d。顶面115a、115b、115c和115d可以是凹面的。换言之，剩余的第一伪半导体鳍114的顶面115a、115b、115c和115d是向内弯曲的。剩余的第一伪半导体鳍114的顶面115a、115b、115c和115d的至少一个以及剩余的第二伪半导体鳍116的顶面117a和117b的至少一个是在不同的方向上弯曲。例如，剩余的第一伪半导体鳍114的顶面115a、115b、115c和115d是凹面的(或向内弯曲的)，且剩余的第二伪半导体鳍116的顶面117a和117b是非凹面的，诸如凸面的(或向外弯曲的)或基本上平的。此外，在一些实施例中，第一伪半导体鳍114的至少两个的顶面形成凹面轮廓C。例如，在图1G中，剩余的第一伪半导体鳍114的顶面115a、115b、115c和115d形成凹面轮廓。
根据上述实施例，使用至少两个去除工艺(即，图1E和图1G的工艺)去除(或蚀刻或切割)伪半导体鳍(即，第一和第二伪半岛体鳍)。此外，在去除内部伪半导体鳍(即，第一伪半导体鳍)之前去除外部伪半导体鳍(即，第二伪半导体鳍)。在伪半导体鳍的去除工艺期间，这样的工艺可以防止有源半导体鳍被损坏。更详细地，提前去除第二伪半导体鳍，从而在第一伪半导体鳍和有源半导体鳍之间形成间隔。在第一伪半导体鳍的去除工艺期间，该间隔可以减小蚀刻剂损坏有源半导体鳍的可能性。
参考图1H。在一些实施例中，形成至少一个隔离结构160以覆盖第一伪半导体鳍114和第二伪半导体鳍116，而同时未覆盖有源半导体鳍112。换言之，有源半导体鳍112从隔离结构160突出，且在隔离结构160下方嵌入第一伪半导体鳍114和第二伪半导体鳍116。有源半导体鳍112可以是至少一个鳍式场效应晶体管(finFET)的源极/漏极部件。
在一些实施例中，隔离结构160包括氧化硅、氮化硅、氮氧化硅、其他合适的材料或它们的组合。通过合适的工艺来形成隔离结构160。例如，通过使用化学汽相沉积(CVD)利用一种或多种介电材料填充半导体鳍(即，有源半导体鳍112、以及第一伪半导体鳍114和第二伪半导体鳍116)之间的沟槽形成隔离结构160。在一些实施例中，隔离结构160可以具有多层结构，诸如填充有氮化硅或氧化硅的热氧化物衬垫层。在形成隔离结构之后可以实施至少一个退火工艺。在一些实施例中，在隔离结构160的形成工艺期间，可以去除衬垫层122和掩模层124'(见图1G)。
在形成隔离结构160之后，半导体器件可进行进一步CMOS或MOS技术处理，以形成各种部件和区域。例如，除了其它方面，进一步的制造工艺可以包括在衬底110上形成栅极结构，包括在有源半导体鳍112的部分上，并且在栅极结构的相对两侧上形成源极和漏极(S/D)区域，包括有源半导体鳍112的另一部分。栅极结构的形成可以包括沉积、图案化和蚀刻工艺。可以通过沉积和蚀刻技术，在栅极结构的壁上形成栅极间隔件。可以通过凹进、外延生长和注入技术形成S/D区域。可以在上述工艺之前、期间和之后提供额外的工艺，并且对于方法的其他实施例，可以替代或消除描述的一些工艺。
随后的处理也可以在衬底110上形成各种接触件/通孔/线和多层互连部件(例如，金属层和层间电介质)，接触件/通孔/线和多层互连部件配置为连接半导体器件的各种部件或结构。例如，多层互连件包括诸如传统的通孔或接触件的垂直互连件，和诸如金属线的水平互连件。各个互连部件可以使用各种导电材料，包括铜，钨，和/或硅化物。在一些实施例中，使用镶嵌工艺和/或双镶嵌工艺以形成与铜相关的多层互连结构。
图2是根据本发明一些实施例的半导体器件的截面图。图1G和图2的半导体器件之间的区别在于衬底的组件。在图2中，衬底110包括第一部分106、第二部分107和第三部分108。在第一部分106上设置第二部分107，且在第二部分107上设置第三部分108，从而堆叠第一部分106、第二部分107和第三部分108以形成衬底110。第一部分106和第二部分107具有不同的材料成分，且第二部分107和第三部分108具有不同的材料成分。在一些实施例中，衬底110的第一部分106和第三部分108可以由基本上相同的材料制成。例如，衬底的第一部分106和第三部分108包括诸如块状硅的硅，并且衬底110的第二部分107包括硅、锗和诸如SiGeO的氧化物。因此，第一部分106、第二部分107和第三部分108形成Si/SiGeO/Si堆叠的层。尽管在图2中，在衬底110的第三部分108中形成邻近的半导体鳍(即，第一和第二伪半导体鳍以及有源半导体鳍)之间的至少一个沟槽T。换言之，沟槽T的底面高于衬底110的第二部分107和第三部分108的界面。然而，在一些其它实施例中，沟槽T可以暴露出衬底110的第二部分107，并且在这方面不限制要求保护的范围。图2的半导体器件的其他相关结构细节与图1G的半导体器件类似，因此下文中不再重复这方面的描述。
根据一些实施例，半导体器件包括衬底、至少一个有源半导体鳍、至少一个第一伪半导体鳍、以及至少一个第二伪半导体鳍。在衬底上设置有源半导体鳍。在衬底上设置第一伪半导体鳍。在衬底上且在有源半导体鳍和第一伪半导体鳍之间设置第二伪半导体鳍。第一伪半导体鳍的顶面和第二伪半导体鳍的顶面在不同的方向上弯曲。
在上述半导体器件中，其中，所述第二伪半导体鳍邻近所述有源半导体鳍和所述第一伪半导体鳍。
在上述半导体器件中，其中，所述第一伪半导体鳍的所述顶面向内弯曲，以及所述第二伪半导体鳍的所述顶面向外弯曲。
在上述半导体器件中，还包括：隔离结构，覆盖所述第一伪半导体鳍和所述第二伪半导体鳍，而未覆盖所述有源半导体鳍。
在上述半导体器件中，其中，所述衬底由块状硅制成。
在上述半导体器件中，其中，所述衬底包括：第一部分；在所述第一部分上设置的第二部分，其中，所述第一部分和所述第二部分具有不同的材料组分；以及在所述第二部分上设置的第三部分，其中，所述第二部分和所述第三部分具有不同的材料组分。
在上述半导体器件中，其中，所述衬底包括：第一部分；在所述第一部分上设置的第二部分，其中，所述第一部分和所述第二部分具有不同的材料组分；以及在所述第二部分上设置的第三部分，其中，所述第二部分和所述第三部分具有不同的材料组分，其中，所述衬底的所述第一部分和所述第三部分由相同的材料制成。
在上述半导体器件中，其中，所述衬底包括：第一部分；在所述第一部分上设置的第二部分，其中，所述第一部分和所述第二部分具有不同的材料组分；以及在所述第二部分上设置的第三部分，其中，所述第二部分和所述第三部分具有不同的材料组分，其中，所述衬底的所述第一部分和所述第三部分包括硅，以及所述衬底的所述第二部分包括硅、锗和氧化物。
在上述半导体器件中，其中，所述第二伪半导体鳍的至少两个设置在所述有源半导体鳍的至少两个之间，以及所述第一伪半导体鳍设置在所述第二伪半导体鳍之间。
在上述半导体器件中，其中，所述第二伪半导体鳍的至少两个设置在所述有源半导体鳍的至少两个之间，以及所述第一伪半导体鳍设置在所述第二伪半导体鳍之间，所述第二伪半导体鳍具有相同的高度。
根据一些实施例，半导体器件包括衬底、至少一个有源半导体鳍、多个第一伪半导体鳍、以及至少一个第二伪半导体鳍。在衬底上设置有源半导体鳍。在衬底上设置第一伪半导体鳍。第一伪半导体鳍的顶面形成凹面轮廓。在衬底上且在有源半导体鳍和第一伪半导体鳍之间设置第二伪半导体鳍。第二伪半导体鳍的顶面是非凹面的。
在上述半导体器件中，其中，所述有源半导体鳍具有第一高度，所述第一伪半导体鳍的至少一个具有短于所述有源半导体鳍的所述第一高度的第二高度。
在上述半导体器件中，其中，所述有源半导体鳍具有第一高度，所述第一伪半导体鳍的至少一个具有短于所述有源半导体鳍的所述第一高度的第二高度，所述第二伪半导体鳍具有大于所述第一伪半导体鳍的所述至少一个的所述第二高度且短于所述有源半导体鳍的所述第一高度的第三高度。
在上述半导体器件中，还包括：在所述第一伪半导体鳍和所述第二伪半导体鳍上设置的隔离结构，所述隔离结构未覆盖所述有源半导体鳍。
根据一些实施例，一种用于制造半导体鳍的方法包括：在衬底上形成至少一个有源半导体鳍、至少一个第一伪半导体鳍、以及至少一个第二伪半导体鳍。在有源半导体鳍和第一伪半导体鳍之间设置第二伪半导体鳍。去除第二伪半导体鳍的至少部分。在去除第二伪半导体鳍的部分之后去除第一伪半导体鳍的至少部分。
在上述方法中，其中，去除所述第二伪半导体鳍的所述部分包括：形成抗反射层以覆盖所述有源半导体鳍、所述第一伪半导体鳍和所述第二伪半导体鳍；在所述抗反射层上形成图案化的掩模，其中，所述图案化的掩模暴露出设置在所述第二伪半导体鳍上的所述抗反射层的部分；以及去除由所述图案化的掩模暴露出的所述抗反射层的所述部分和所述第二伪半导体鳍的所述部分。
在上述方法中，其中，去除所述第一伪半导体鳍的所述部分包括：在去除所述第二伪半导体鳍的所述部分之后，形成抗反射层以覆盖所述有源半导体鳍、所述第一伪半导体鳍和剩余的第二伪半导体鳍；在所述抗反射层上形成图案化的掩模，其中，所述图案化的掩模暴露出设置在所述第一伪半导体鳍上的所述抗反射层的部分；以及去除由所述图案化的掩模暴露出的所述抗反射层的所述部分和所述第一伪半导体鳍的所述部分。
在上述方法中，还包括：形成隔离结构以覆盖剩余的第一伪半导体鳍和剩余的第二伪半导体鳍，而未覆盖所述有源半导体鳍。
在上述方法中，其中，所述衬底由硅制成。
在上述方法中，其中，所述衬底包括Si/SiGeO/Si堆叠的层。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (19)

1.一种半导体器件，包括：
衬底；
至少一个有源半导体鳍，设置在所述衬底上；
至少一个第一伪半导体鳍，设置在所述衬底上；以及
至少一个第二伪半导体鳍，设置在所述衬底上以及所述有源半导体鳍和所述第一伪半导体鳍之间，其中，所述第一伪半导体鳍的顶面和所述第二伪半导体鳍的顶面在不同方向上弯曲，所述第一伪半导体鳍的所述顶面向内弯曲，以及所述第二伪半导体鳍的所述顶面向外弯曲。
2.根据权利要求1所述的半导体器件，其中，所述第二伪半导体鳍邻近所述有源半导体鳍和所述第一伪半导体鳍。
3.根据权利要求1所述的半导体器件，还包括：
隔离结构，覆盖所述第一伪半导体鳍和所述第二伪半导体鳍，而未覆盖所述有源半导体鳍。
4.根据权利要求1所述的半导体器件，其中，所述衬底由块状硅制成。
5.根据权利要求1所述的半导体器件，其中，所述衬底包括：
第一部分；
在所述第一部分上设置的第二部分，其中，所述第一部分和所述第二部分具有不同的材料组分；以及
在所述第二部分上设置的第三部分，其中，所述第二部分和所述第三部分具有不同的材料组分。
6.根据权利要求5所述的半导体器件，其中，所述衬底的所述第一部分和所述第三部分由相同的材料制成。
7.根据权利要求5所述的半导体器件，其中，所述衬底的所述第一部分和所述第三部分包括硅，以及所述衬底的所述第二部分包括硅、锗和氧化物。
8.根据权利要求1所述的半导体器件，其中，所述第二伪半导体鳍的至少两个设置在所述有源半导体鳍的至少两个之间，以及所述第一伪半导体鳍设置在所述第二伪半导体鳍之间。
9.根据权利要求8所述的半导体器件，其中，所述第二伪半导体鳍具有相同的高度。
10.一种半导体器件，包括：
衬底；
至少一个有源半导体鳍，设置在所述衬底上；
多个第一伪半导体鳍，设置在所述衬底上，其中，所述第一伪半导体鳍的顶面形成凹面轮廓；以及
至少一个第二伪半导体鳍，设置在所述衬底上以及在所述有源半导体鳍和所述第一伪半导体鳍之间，其中，所述第二伪半导体鳍的顶面是非凹面的；
其中，所述第一伪半导体鳍的顶面向内弯曲，以及所述第二伪半导体鳍的顶面向外弯曲。
11.根据权利要求10所述的半导体器件，其中，所述有源半导体鳍具有第一高度，所述第一伪半导体鳍的至少一个具有短于所述有源半导体鳍的所述第一高度的第二高度。
12.根据权利要求11所述的半导体器件，其中，所述第二伪半导体鳍具有大于所述第一伪半导体鳍的所述至少一个的所述第二高度且短于所述有源半导体鳍的所述第一高度的第三高度。
13.根据权利要求10所述的半导体器件，还包括：
在所述第一伪半导体鳍和所述第二伪半导体鳍上设置的隔离结构，所述隔离结构未覆盖所述有源半导体鳍。
14.一种用于制造半导体鳍的方法，包括：
在衬底上形成至少一个有源半导体鳍、至少一个第一伪半导体鳍以及至少一个第二伪半导体鳍，其中，所述第二伪半导体鳍设置在所述有源半导体鳍和所述第一伪半导体鳍之间；
去除所述第二伪半导体鳍的至少部分；以及
在去除所述第二伪半导体鳍的所述部分之后去除所述第一伪半导体鳍的至少部分；
其中，所述第一伪半导体鳍的顶面向内弯曲，以及所述第二伪半导体鳍的顶面向外弯曲。
15.根据权利要求14所述的方法，其中，去除所述第二伪半导体鳍的所述部分包括：
形成抗反射层以覆盖所述有源半导体鳍、所述第一伪半导体鳍和所述第二伪半导体鳍；
在所述抗反射层上形成图案化的掩模，其中，所述图案化的掩模暴露出设置在所述第二伪半导体鳍上的所述抗反射层的部分；以及
去除由所述图案化的掩模暴露出的所述抗反射层的所述部分和所述第二伪半导体鳍的所述部分。
16.根据权利要求14所述的方法，其中，去除所述第一伪半导体鳍的所述部分包括：
在去除所述第二伪半导体鳍的所述部分之后，形成抗反射层以覆盖所述有源半导体鳍、所述第一伪半导体鳍和剩余的第二伪半导体鳍；
在所述抗反射层上形成图案化的掩模，其中，所述图案化的掩模暴露出设置在所述第一伪半导体鳍上的所述抗反射层的部分；以及
去除由所述图案化的掩模暴露出的所述抗反射层的所述部分和所述第一伪半导体鳍的所述部分。
17.根据权利要求14所述的方法，还包括：
形成隔离结构以覆盖剩余的第一伪半导体鳍和剩余的第二伪半导体鳍，而未覆盖所述有源半导体鳍。
18.根据权利要求14所述的方法，其中，所述衬底由硅制成。
19.根据权利要求14所述的方法，其中，所述衬底包括Si/SiGeO/Si堆叠的层。
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