TW201711195A - 半導體裝置與其製造方法 - Google Patents

半導體裝置與其製造方法 Download PDF

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TW201711195A
TW201711195A TW105120574A TW105120574A TW201711195A TW 201711195 A TW201711195 A TW 201711195A TW 105120574 A TW105120574 A TW 105120574A TW 105120574 A TW105120574 A TW 105120574A TW 201711195 A TW201711195 A TW 201711195A
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semiconductor fin
dummy
dummy semiconductor
fin
fins
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TW105120574A
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TWI596766B (zh
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李智聖
黃信傑
劉繼文
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台灣積體電路製造股份有限公司
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    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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Abstract

半導體裝置包含基板、至少一主動半導體鰭、至少一第一偽半導體鰭與至少一第二偽半導體鰭。主動半導體鰭置於基板上。第一偽半導體鰭置於基板上。第二偽半導體鰭置於基板上以及主動半導體鰭與第一偽半導體鰭之間。第一偽半導體鰭之頂表面與第二偽半導體鰭之頂表面向不同的方向彎曲。

Description

半導體裝置與其製造方法
本揭露係關於一種半導體裝置。
半導體積體電路(integrated circuit；IC)工業已經歷指數級增長。IC材料與設計之技術進步已產生數代IC，其中每一代都具有比上一代更小與更複雜的電路。在積體電路進化過程中，功能密度(亦即單位晶片面積中之互連裝置數目)已普遍提高，同時幾何形狀尺寸(亦即可藉由使用製造工藝而產生之最小組件(或線路))已縮小。此種按比例縮小之製程一般藉由提高生產效率與降低關連成本來提供益處。
此種按比例縮小亦已提高處理與製造IC之複雜性，及為了實現此進步，IC處理與製造需要類似的發展。例如，引入諸如鰭式場效電晶體(fin-like field-effect transistor；FinFET)之三維電晶體以更替平面電晶體。鰭式電晶體具有一通道(被稱作鰭式通道)，此通道與頂表面及相對的側壁關連。鰭式通道具有一總通道寬度，此寬度由頂表面及相對的側壁界定。
本揭露之一態樣提供一種半導體裝置，包含基板、至少一主動半導體鰭、至少一第一偽半導體鰭與至少一第二偽半導體鰭。主動半導體鰭置於基板上。第一偽半導體鰭置於基板上。第二偽半導體鰭置於基板上以及主動半導體鰭與第一偽半導體鰭之間。第一偽半導體鰭之頂表面與第二偽半導體鰭之頂表面向不同的方向彎曲。
本揭露之另一態樣提供一種半導體裝置，包含基板、至少一主動半導體鰭、複數個第一偽半導體鰭與至少一第二偽半導體鰭。主動半導體鰭置於基板上。第一偽半導體鰭置於基板上。第一偽半導體鰭之頂表面形成凹面輪廓。第二偽半導體鰭置於基板上以及主動半導體鰭與第一偽半導體鰭之間。第二偽半導體鰭之頂表面為非凹面。
本揭露之再一態樣提供一種半導體裝置的製造方法，包含在基板上形成至少一主動半導體鰭、至少一第一偽半導體鰭與至少一第二偽半導體鰭。第二偽半導體鰭置於主動半導體鰭與第一偽半導體鰭之間。移除第二偽半導體鰭之至少一部分。在移除第二偽半導體鰭之該部分之後移除第一偽半導體鰭之至少一部分。
根據前述的實施方式，偽半導體鰭(亦即，第一及第二偽半導體鰭)藉由使用至少兩個移除製程而被移除(或蝕刻或截斷)。此外，在內部偽半導體鰭(亦即第一偽半導體鰭)被移除之前移除外側偽半導體鰭(亦即第二偽半導體鰭)。此製程可防止主動半導體鰭在偽半導體鰭之移除製 程期間被損壞。更詳細而言，預先移除第二偽半導體鰭，以使得第一偽半導體鰭與主動半導體鰭之間形成空間。在第一偽半導體鰭之移除製程期間，此空間可降低蝕刻劑損害主動半導體鰭之可能性。
102‧‧‧主動區域
104‧‧‧偽區域
106‧‧‧第一部分
107‧‧‧第二部分
108‧‧‧第三部分
110‧‧‧基板
112‧‧‧主動半導體鰭
114‧‧‧第一偽半導體鰭
115a、115b、115c、115d、117a、117b‧‧‧頂表面
116‧‧‧第二偽半導體鰭
122‧‧‧襯墊層
124‧‧‧遮罩層
124’‧‧‧圖案化遮罩層
130、140、150‧‧‧三層光阻劑
132、142、152‧‧‧光阻劑層
134、144、154‧‧‧中間層
136、146、156‧‧‧底層
160‧‧‧絕緣結構
C‧‧‧凹面輪廓
H1、H2、H2a、H2b、H2c、H2d、H3、H3a、H3b‧‧‧高度
T‧‧‧溝槽
本揭露之態樣最佳在閱讀附圖時根據下文之詳細說明來進行理解。應注意，依據工業中之標準實務，多個特徵並未按比例繪製。實際上，多個特徵之尺寸可任意增大或縮小，以便使論述明晰。
第1A圖至第1H圖是依據本揭露之一些實施方式之用於製造半導體裝置的方法中各階段的剖面圖。
第2圖是依據本揭露之一些實施方式之一半導體裝置之剖面圖。
以下揭示內容提供眾多不同的實施方式或範例以用於實施本案提供之標的物的不同特徵。下文中描述組件及排列之特定範例以簡化本揭露。此等組件及排列當然僅為範例，及不意欲進行限制。例如，在下文之描述中，第一特徵在第二特徵上方或之上的形成可包含其中第一特徵與第二特徵以直接接觸方式形成的實施方式，及亦可包含其中在第一特徵與第二特徵之間形成額外特徵以使得第一特徵與第二特徵無法直接接觸之實施方式。此外，本揭露在多個範 例中可重複元件符號及/或字母。此重複用於實現簡化與明晰之目的，及其自身並不規定所論述之多個實施方式及/或配置之間的關係。
此外，本案中可使用諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等等之空間相對術語在以便於描述，以描述一個元件或特徵與另一或更多個元件或特徵之關係，如圖式中所圖示。空間相對術語意欲包含在使用或操作中之裝置除圖式中繪示之定向以外的不同定向。或者，設備可經定向(旋轉90度或其他定向)，及本案中使用之空間相對描述詞同樣可相應地進行解釋。
可利用本案之一或更多個實施方式得到改良的裝置範例為半導體裝置。此種裝置例如為鰭式場效電晶體(fin field effect transistor,FinFET)裝置。FinFET裝置例如可為互補金氧半導體(complementary metal-oxide-semiconductor；CMOS)裝置，此裝置包含至少一P型金氧半導體(P-type metal-oxide semiconductor；PMOS)FinFET裝置與至少一N型金氧半導體(N-type metal-oxide-semiconductor；NMOS)FinFET裝置。以下揭示內容將繼續介紹FinFET範例，以說明本案之多個實施方式。然而，應理解，本案不應限定於特定類型之裝置。
第1A圖至第1H圖是依據本揭露之一些實施方式之用於製造半導體裝置的方法中各階段的剖面圖。請參照第1A圖。提供基板110。基板110具有至少一主動區域102 與至少一偽區域104。例如，在第1A圖中，基板110具有兩個主動區域102與一個偽區域104，且偽區域104位於兩個主動區域102之間。在一些實施方式中，基板110包含矽，例如塊體矽(bulk silicon)。或者，基板110可包含鍺、矽鍺、砷化鎵或其他適當的半導體材料。又或者，基板110可包含磊晶層。例如，基板110可具有覆蓋整塊半導體之磊晶層。此外，基板110可經應變處理以獲得效能增強。例如，磊晶層可包含一種半導體材料，此材料不同於整塊半導體之材料，如覆蓋塊體矽之矽鍺層或覆蓋塊體矽鍺之矽層。此種應變基板可由選擇性磊晶生長(selective epitaxial growth；SEG)形成。此外，基板110可包含絕緣體上半導體(semiconductor on insulator；SOI)結構。亦或者，基板110可包含埋置介電層，如埋置氧化物(buried oxide BOX)層，此層如由氧佈植隔離(separation by implantation of oxygen；SIMOX)技術、晶圓黏接、選擇性磊晶成長或其他適當方法形成。
襯墊層122與遮罩層124形成於基板110上。襯墊層122包含介電材料，如氧化矽、氮化矽、氮氧化矽，或任何其他適合之介電材料。遮罩層124包含介電材料，如氧化矽、氮化矽、氮氧化矽，或任何其他適合之介電材料。在一些實施方式中，遮罩層124是硬質遮罩層。在一些實施方式中，襯墊層122是沉積在基板110上之氧化矽層，而遮罩層124是沉積在襯墊層122上之氮化矽層。襯墊層122與遮罩層124可由熱氧化、化學氧化、原子層沉積(atomic layer deposition；ALD)或任何其他適當的方法而形成。在一些實施方式中，襯墊層122之厚度可在約100-800Å之間，而遮罩層124之厚度可在約200-2000Å之間。
執行在半導體基板110上界定半導體鰭之微影術製程。在一些實施方式中，可使用三層光阻劑130，此三層光阻劑包含用作頂部或最上層部分之光阻劑(photoresist；PR)層132、中間層134與底層136。三層光阻劑130置於遮罩層124上。三層光阻劑130提供光阻劑層132、可包含抗反射層或背側抗反射層以協助光阻劑處理之曝露與聚焦的中間層134，以及可為硬質遮罩材料之底層136；例如，氮化物。為了圖案化三層光阻劑130，光阻劑層132藉由以下步驟而經圖案化：使用遮罩，曝露於諸如燈或準分子雷射之輻射，經烘焙或固化操作以硬化抗蝕劑，以及依據所使用的是正性抗蝕劑還是負性抗蝕劑而使用顯影劑以移除抗蝕劑之曝露或未曝露部分，以利用光阻劑層132中之遮罩而形成圖案。然後，此圖案化光阻劑層132用於蝕刻位於下方的中間層134及底層136以形成蝕刻遮罩以用於目標層(在本實施方式中亦即遮罩層124)。
請參照第1B圖。執行溝槽蝕刻以形成圖案化遮罩層124’。在溝槽蝕刻期間，圖案化光阻劑層132(請參照第1A圖)用作遮罩。在溝槽蝕刻時，中間層134、底層136，與遮罩層124(請參照第1A圖)可藉由多種方法進行蝕刻，包含乾式蝕刻、濕式蝕刻，或乾式蝕刻與濕式蝕刻之組合。蝕刻製程可實施含氟氣體(例如四氟化碳(CF4)、六氟化硫 (SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)與/或六氟乙烷(C2F6))、含氯氣體(例如氯氣(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)與/或三氯化硼(BCl3))、含溴氣體(例如溴化氫(HBr)與/或三溴甲烷(CHBR3))、含氧氣體、含碘氣體、其他適合氣體與/或電漿，或上述各者之組合。蝕刻製程可包含多步驟蝕刻以獲得蝕刻選擇性、靈活性及所需蝕刻輪廓。在遮罩層124經圖案化之後，移除光阻劑層132、中間層134與底層136。
請參照第1C圖。藉由使用圖案化遮罩層124'作為遮罩，襯墊層122及基板110可藉由多種方法經蝕刻以形成複數個半導體鰭，方法包含乾式蝕刻、濕式蝕刻，或乾式蝕刻與濕式蝕刻之組合。幹蝕刻製程可實施含氟氣體(例如四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6))、含氯氣體含氯氣體(例如氯氣(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)與/或三氯化硼(BCl3))、含溴氣體(例如溴化氫(HBr)與/或三溴甲烷(CHBR3))、含氧氣體、含碘氣體、其他適合氣體與/或電漿，或上述各者之組合。蝕刻製程可包含多步驟蝕刻以獲得蝕刻選擇性、靈活性及所需蝕刻輪廓。
在第1C圖中，半導體鰭包含至少一主動半導體鰭112、至少一第一偽(dummy)半導體鰭114與至少一第二偽半導體鰭116。例如，在第1C圖中，有六支主動半導體鰭112、四支第一偽半導體鰭114與兩支第二偽半導體鰭116，然而本揭露所主張之範疇並非限定於此。六支主動半 導體鰭112被分成兩組並分別置於兩個主動區域102中。在第1C圖中，主動半導體鰭112中有三個位於主動區域102之一者中。第一偽半導體鰭114及第二偽半導體鰭116置於偽區域104中。亦即，第一偽半導體鰭114及第二偽半導體鰭116置於兩組主動半導體鰭112之間。第一偽半導體鰭114彼此毗鄰以形成一組，而一之第二偽半導體鰭116置於此組第一偽半導體鰭114與一組主動半導體鰭112之間。因此，第一偽半導體鰭114可被稱作內部偽半導體鰭，而第二偽半導體鰭116可被稱作外部偽半導體鰭。
第一偽半導體鰭114與第二偽半導體鰭116在半導體裝置中沒有功能，但可使得裝置製程更為均勻、可再現性更高，且可製造性更高。主動半導體鰭112在半導體裝置中具有功能。在第一偽半導體鰭114與第二偽半導體鰭116緊鄰主動半導體鰭112之情況下，主動半導體鰭112可形成於所有關連位置中極相似之環繞結構之下。在鰭之臨界尺寸(critical dimension；CD)、輪廓及高度方面，一致的環繞結構形成增強所有關連位置中之均勻的主動半導體鰭112。
在一些實施方式中，主動半導體鰭112之高度H1、第一偽半導體鰭114之高度H2與第二偽半導體鰭116之高度H3可為約100奈米至約150奈米，然而本揭露所主張之範疇並非限定於此。
請參照第1D圖。可使用另一三層光阻劑140，此三層光阻劑包含用作頂部或最上層部分之光阻劑 (photoresist；PR)層142、中間層144與底層146。三層光阻劑140覆蓋主動半導體鰭112、第一偽半導體鰭114與第二偽半導體鰭116。三層光阻劑140提供光阻劑層142、可包含抗反射層或背側抗反射層以協助光阻劑處理之曝露及聚焦的中間層144，與可為硬質遮罩材料之底層146；例如，氮化物。
然後，圖案化三層光阻劑140之光阻劑層142。圖案化光阻劑層142曝露中間層144之置於第二偽半導體鰭116上之部分。同時，中間層144中置於主動半導體鰭112與第一偽半導體鰭114上之另一部分仍由光阻劑層142覆蓋。為了圖案化三層光阻劑140，光阻劑層142藉由以下步驟而經圖案化：使用遮罩，曝露於諸如燈或準分子雷射之輻射，經烘焙或固化操作以硬化抗蝕劑，並依據所使用的是正性抗蝕劑還是負性抗蝕劑而使用顯影劑以移除抗蝕劑之曝露或未曝露部分，以利用光阻劑層142中之遮罩而形成圖案。然後，此圖案化光阻劑層142用於蝕刻位於下方的中間層144及底層146以形成目標特徵(此處亦即第二偽半導體鰭116)之蝕刻遮罩。
請參照第1E圖。藉由使用圖案化光阻劑層142(請參照第1D圖)以作為遮罩，三層光阻劑140之中間層144與底層146(請參照第1D圖)藉由多種方法蝕刻，包含乾式蝕刻、濕式蝕刻或乾式蝕刻與濕式蝕刻之組合。此外，移除(或蝕刻)第二偽半導體鰭116中之至少部分。幹蝕刻製程可實施含氟氣體(例如四氟化碳(CF4)、六氟化硫(SF6)、二 氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6))、含氯氣體含氯氣體(例如氯氣(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)與/或三氯化硼(BCl3))、含溴氣體(例如溴化氫(HBr)與/或三溴甲烷(CHBR3))、含氧氣體、含碘氣體、其他適合氣體與/或電漿，或上述各者之組合。蝕刻製程可包含多步驟蝕刻以獲得蝕刻選擇性、靈活性及所需蝕刻輪廓。在部分移除第二偽半導體鰭116之後，移除三層光阻劑140之光阻劑層142、中間層144與底層146。
在第1E圖中，剩餘之第二偽半導體鰭116之高度H3a及H3b可為主動半導體鰭112之高度H1的約17%至約27%。換言之，剩餘之第二偽半導體鰭116之高度H3a及H3b為約17奈米至約40.5奈米。至少一之第二偽半導體鰭116具有頂表面117a(117b)。頂表面117a(117b)可為非凹面，如凸面或實質平面。在一些實施方式中，第二偽半導體鰭116之頂表面117a(117b)是向外彎曲的。此外，在一些實施方式中，兩個剩餘第二偽半導體鰭116之高度H3a及H3b實質相同。本案中所使用術語「實質」可適用於修正任何定量表述，此表述可以允許之方式改變，而不使得其所相關之基本功能發生變更。
請參照第1F圖。可使用又一三層光阻劑150，此三層光阻劑包含用作頂部或最上層部分之光阻劑(photoresist；PR)層152、中間層154與底層156。三層光阻劑150覆蓋主動半導體鰭112、第一偽半導體鰭114，及剩餘的第二偽半導體鰭116。三層光阻劑150提供光阻劑層 152、可包含抗反射層或背側抗反射層以協助光阻劑處理之曝露及聚焦的中間層154，與可為硬質遮罩材料之底層156；例如，氮化物。
然後，圖案化三層光阻劑150之光阻劑層152。經圖案化光阻劑層152曝露中間層154之置於第一偽半導體鰭114上之部分。同時，中間層154中置於主動半導體鰭112與剩餘第二偽半導體鰭116上之部分仍由光阻劑層152覆蓋。為了圖案化三層光阻劑150，藉由以下步驟而圖案化光阻劑層152：使用遮罩，曝露於諸如燈或準分子雷射之輻射，經烘焙或固化操作以硬化抗蝕劑，及依據所使用的是正性抗蝕劑還是負性抗蝕劑而使用顯影劑以移除抗蝕劑之曝露或未曝露部分，以利用光阻劑層152中之遮罩而形成圖案。然後，此圖案化光阻劑層152用於蝕刻位於下方的中間層154及底層156以形成靶特徵(此處亦即第一偽半導體鰭114)之蝕刻遮罩。
請參照第1G圖。藉由使用圖案化光阻劑層152(請參照第1F圖)以作為遮罩，三層光阻劑150之中間層154與底層156(請參照第1F圖)藉由多種方法經蝕刻，包含乾式蝕刻、濕式蝕刻或乾式蝕刻與濕式蝕刻之組合。此外，移除(或蝕刻)第一偽半導體鰭114中之至少部分。幹蝕刻製程可實施含氟氣體(例如四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或六氟乙烷(C2F6))、含氯氣體含氯氣體(例如氯氣(Cl2)、三氯甲烷(CHCl3)、四氯化碳(CCl4)與/或三氯化硼(BCl3))、含溴氣 體(例如溴化氫(HBr)與/或三溴甲烷(CHBR3))、含氧氣體、含碘氣體、其他適合氣體與/或電漿，或上述各者之組合。蝕刻製程可包含多步驟蝕刻以獲得蝕刻選擇性、靈活性與所需蝕刻輪廓。在部分移除第一偽半導體鰭114之後，移除三層光阻劑150之光阻劑層152、中間層154與底層156。
在第1G圖中，剩餘第一偽半導體鰭114之高度H2a、H2b、H2c與H2d可為主動半導體鰭112之高度H1之約6%至約16%。亦即，剩餘第一偽半導體鰭114之高度H2a、H2b、H2c與H2d為約6奈米至24奈米。此外，剩餘第二偽半導體鰭116之高度H3a與H3b大於剩餘第一偽半導體鰭114之高度H2a、H2b、H2c與H2d。在一些實施方式中，剩餘第一偽半導體鰭114與第二偽半導體鰭116之間的高度差(亦即(H3a或H3b)-(H2a、H2b、H2c或H2d))為約3奈米至約30奈米，或主動半導體鰭112之高度H1之約3%至約17%。在一些實施方式中，剩餘第一偽半導體鰭114之輪廓是對稱的。或者，高度H2a與H2d實質上相同，高度H2b與H2c實質上相同，且高度H2a與H2d大於高度H2b與H2c，然而本揭露所主張之範疇並非限定於此。本揭露中所使用之術語「實質」可適用於修正任何定量表述，此表述可以允許之方式改變，而不使得其所相關之基本功能發生變更。
第一偽半導體鰭114分別具有頂表面115a、115b、115c與115d。頂表面115a、115b、115c與115d可為凹面。亦即，剩餘第一偽半導體鰭114之頂表面115a、 115b、115c與115d向內彎曲。剩餘第一偽半導體鰭114之頂表面115a、115b、115c與115d中之至少一者與剩餘第二偽半導體鰭116之頂表面117a與117b中之至少一者向不同的方向彎曲。例如，剩餘第一偽半導體鰭114之頂表面115a、115b、115c與115d是凹面的(或者向內彎曲的)，而剩餘第二偽半導體鰭116之頂表面117a與117b是非凹面的，如凸形(或者向外彎曲的)或實質為平面。此外，在一些實施方式中，至少兩個第一偽半導體鰭114之頂表面形成凹面輪廓。例如，在第1G圖中，剩餘第一偽半導體鰭114之頂表面115a、115b、115c與115d形成凹面輪廓C。
根據前述的實施方式，偽半導體鰭(亦即，第一及第二偽半導體鰭)藉由使用至少兩個移除製程(亦即第1E圖及第1G圖之製程)而被移除(或蝕刻或截斷)。此外，在內部偽半導體鰭(亦即第一偽半導體鰭)被移除之前移除外側偽半導體鰭(亦即第二偽半導體鰭)。此製程可防止主動半導體鰭在偽半導體鰭之移除製程期間被損壞。更詳細而言，預先移除第二偽半導體鰭，以使得第一偽半導體鰭與主動半導體鰭之間形成空間。在第一偽半導體鰭之移除製程期間，此空間可降低蝕刻劑損害主動半導體鰭之可能性。
請參照第1H圖。在一些實施方式中，形成至少一絕緣結構160以覆蓋第一偽半導體鰭114及第二偽半導體鰭116，且未覆蓋主動半導體鰭112。亦即，主動半導體鰭112從絕緣結構160中突出，且第一偽半導體鰭114及第二偽半導體鰭116埋於絕緣結構160下方。主動半導體鰭112 可為至少一鰭場效電晶體(fin field effect transistor；finFET)之源極/汲極。
在一些實施方式中，絕緣結構160包含氧化矽、氮化矽、氮氧化矽、其他適合材料，或上述各者之組合。絕緣結構160藉由適合製程形成。例如，絕緣結構160是藉由利用一或更多個介電材料，藉由使用化學氣相沉積(chemical vapor deposition；CVD)充填半導體鰭(亦即主動半導體鰭112、第一偽半導體鰭114與第二偽半導體鰭116)之間的溝槽而形成的。在一些實施方式中，絕緣結構160可具有多層結構，如充滿氮化矽或氧化矽之熱氧化襯裡層。可在絕緣結構160形成之後執行至少一次退火製程。在一些實施方式中，襯墊層122及遮罩層124'(參照第1G圖)可在絕緣結構160之形成製程期間被移除。
在絕緣結構160形成之後，半導體裝置可經受進一步CMOS或MOS技術處理以形成多種特徵及區域。例如，更多製程可包含但不限於在基板110上(包含在主動半導體鰭112之一部分上)形成閘極結構，並在閘極結構之相對側(包含主動半導體鰭112之另一部分)形成源極及汲極(source and drain；S/D)區域。閘極結構之形成可包含沉積、圖案化及蝕刻製程。閘極間隔物可藉由沉積及蝕刻技術而形成於閘極結構壁上。S/D區域可藉由凹槽、磊晶生長及佈植技術而形成。在上文提及之製程之前、期間與之後可提供額外製程，且在此方法之其他實施方式中，所述製程中之一些製程可被替換或消除。
後續處理亦可在基板110上形成多種觸點/通孔/線路與多層互連特徵(例如金屬層與層間介電質)，上述各者經配置以連接半導體裝置之多種特徵或結構。例如，多層互連裝置包含垂直互連裝置，如習用通孔或觸點，以及包含水平互連裝置，如金屬線路。多種互連特徵可實施多種導電材料，這些材料包含銅、鎢與/或矽化物。在一些實施方式中，鑲嵌(damascene)與/或雙鑲嵌製程用以形成與銅相關之多層互連結構。
第2圖是依據本揭露之一些實施方式之一半導體裝置之剖面圖。第1G圖之半導體裝置與第2圖之半導體裝置之間的差異是基板的組成。在第2圖中，基板110包含第一部分106、第二部分107與第三部分108。第二部分107置於第一部分106上，且第三部分108置於第二部分107上，使得第一部分106、第二部分107與第三部分108堆疊以形成基板110。第一部分106與第二部分107具有不同的材料組成物，且第二部分107與第三部分108具有不同的材料組成物。在一些實施方式中，基板110之第一部分106及第三部分108之材質實質相同。例如，基板110之第一部分106及第三部分108包含矽，如塊體矽(bulk silicon)，而基板110之第二部分107包含矽、鍺與氧化物，如矽鍺氧化物(SiGeO)。因此，第一部分106、第二部分107與第三部分108形成矽/矽鍺氧化物/矽(Si/SiGeO/Si)堆疊層。雖然在第2圖中，相鄰半導體鰭(亦即第一偽半導體鰭、第二偽半導體鰭與主動半導體鰭)之間的至少一溝槽T形成於基板 110之第三部分108中，亦即，溝槽T之底表面高於基板110之第二部分107與第三部分108之介面。然而，在一些其他實施方式中，溝槽T可曝露基板110之第二部分107，然而本揭露所主張之範疇並非限定於此。因第2圖中的半導體裝置之其他相關結構細節類似於第1G圖中之半導體裝置，因此便不再贅述。
根據一些實施方式，一種半導體裝置包含基板、至少一主動半導體鰭、至少一第一偽半導體鰭與至少一第二偽半導體鰭。主動半導體鰭置於基板上。第一偽半導體鰭置於基板上。第二偽半導體鰭置於基板上以及主動半導體鰭與第一偽半導體鰭之間。第一偽半導體鰭之頂表面與第二偽半導體鰭之頂表面向不同的方向彎曲。
根據一些實施方式，一種半導體裝置包含基板、至少一主動半導體鰭、複數個第一偽半導體鰭與至少一第二偽半導體鰭。主動半導體鰭置於基板上。第一偽半導體鰭置於基板上。第一偽半導體鰭之頂表面形成凹面輪廓。第二偽半導體鰭置於基板上以及主動半導體鰭與第一偽半導體鰭之間。第二偽半導體鰭之頂表面為非凹面。
根據一些實施方式，一種半導體裝置的製造方法包含在基板上形成至少一主動半導體鰭、至少一第一偽半導體鰭與至少一第二偽半導體鰭。第二偽半導體鰭置於主動半導體鰭與第一偽半導體鰭之間。移除第二偽半導體鰭之至少一部分。在移除第二偽半導體鰭之該部分之後移除第一偽半導體鰭之至少一部分。
前述內容概括數個實施方式之特徵，以便彼等熟習此項技術者可更佳地理解本揭露之態樣。彼等熟習此項技術者應瞭解，本揭露可易於用作設計或修正其他製程及結構之基礎，以實現與本案介紹之實施方式相同的目的及/或達到與其相同的優勢。彼等熟習此項技術者亦應瞭解，此種同等構造不脫離本揭露之精神及範疇，及可在不脫離本揭露精神及範疇之情況下在本案中進行多種變更、取代及更動。
110‧‧‧基板
112‧‧‧主動半導體鰭
114‧‧‧第一偽半導體鰭
115a、115b、115c、115d、117a、117b‧‧‧頂表面
116‧‧‧第二偽半導體鰭
122‧‧‧襯墊層
124’‧‧‧圖案化遮罩層
C‧‧‧凹面輪廓
H1、H2a、H2b、H2c、H2d、H3a、H3b‧‧‧高度

Claims (10)

  1. 一種半導體裝置，包含：一基板；至少一主動半導體鰭，置於該基板上；至少一第一偽半導體鰭，置於該基板上；以及至少一第二偽半導體鰭，置於該基板上以及該主動半導體鰭與該第一偽半導體鰭之間，其中該第一偽半導體鰭之一頂表面與該第二偽半導體鰭之一頂表面向不同的方向彎曲。
  2. 如請求項1所述之半導體裝置，其中該第二偽半導體鰭毗鄰該主動半導體鰭與該第一偽半導體鰭。
  3. 如請求項1所述之半導體裝置，其中該第一偽半導體鰭之該頂表面向內彎曲，且該第二偽半導體鰭之該頂表面向外彎曲。
  4. 如請求項1所述之半導體裝置，更包含：一絕緣結構，覆蓋該第一偽半導體鰭及該第二偽半導體鰭，且未覆蓋該主動半導體鰭。
  5. 一種半導體裝置，包含：一基板；至少一主動半導體鰭，置於該基板上； 複數個第一偽半導體鰭，置於該基板上，其中該些第一偽半導體鰭之頂表面形成一凹面輪廓；以及至少一第二偽半導體鰭，置於該基板上以及該主動半導體鰭與該些第一偽半導體鰭之間，其中該第二偽半導體鰭之頂表面為非凹面。
  6. 如請求項5所述之半導體裝置，其中該主動半導體鰭具有一第一高度，至少一之該些第一偽半導體鰭具有一第二高度，該第二高度比該主動半導體鰭之該第一高度短，該第二偽半導體鰭具有一第三高度，該第三高度大於該至少一之該些第一偽半導體鰭之該第二高度，並小於該主動半導體鰭之該第一高度。
  7. 如請求項5所述之半導體裝置，更包含：一絕緣結構，置於該第一偽半導體鰭與該第二偽半導體鰭上，且未覆蓋該主動半導體鰭。
  8. 一種半導體裝置的製造方法，包含：在一基板上形成至少一主動半導體鰭、至少一第一偽半導體鰭與至少一第二偽半導體鰭，其中該第二偽半導體鰭置於該主動半導體鰭與該第一偽半導體鰭之間；移除該第二偽半導體鰭之至少一部分；以及在移除該第二偽半導體鰭之該部分之後移除該第一偽半導體鰭之至少一部分。
  9. 如請求項8所述之製造方法，其中該移除該第二偽半導體鰭之該部分包含：形成一抗反射層以覆蓋該主動半導體鰭、該第一偽半導體鰭與該第二偽半導體鰭；在該抗反射層上形成一圖案化遮罩，其中該圖案化遮罩曝露該抗反射層中置於該第二偽半導體鰭上之一部分；以及移除由該圖案化遮罩曝露之該抗反射層之該部分與該第二偽半導體鰭之該部分。
  10. 如請求項8所述之製造方法，更包含：形成一絕緣結構，以覆蓋該剩餘第一偽半導體鰭及該剩餘第二偽半導體鰭，且未覆蓋該主動半導體鰭。
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