CN104703401B - A kind of electro-plating method of circuit board - Google Patents
A kind of electro-plating method of circuit board Download PDFInfo
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- CN104703401B CN104703401B CN201310672062.2A CN201310672062A CN104703401B CN 104703401 B CN104703401 B CN 104703401B CN 201310672062 A CN201310672062 A CN 201310672062A CN 104703401 B CN104703401 B CN 104703401B
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Abstract
The invention discloses a kind of electro-plating method of circuit board, to solve drawbacks described above existing for craft of gilding and thin copper method partially plating gold technique before existing figure, for processing the circuit board required with high-density line and high-precision size.Method includes：The surface metal-layer of circuit board is processed as line layer；The electroless coating region etching of the line layer is subtracted into thickness；Subtract thick electroless coating region setting dielectric having etched；The plating area of the line layer is electroplated.
Description
Technical field
The present invention relates to circuit board technology fields, and in particular to a kind of electro-plating method of circuit board.
Background technology
In circuit board machining process, have a kind of to circuit board surface layer pad（PAD）Or circuit carries out the technique of gold-plated processing,
To play the role of wear-resistant and beat gold thread.Craft of gilding or thin copper method partially plating gold before the craft of gilding generally use figure
Technique is realized.
Craft of gilding is to use big copper face as glodclad wire before making surface lines figure, covered with dry film before figure
Other regions are covered, it is gold-plated to needing plating area to carry out.But craft of gilding has the disadvantage that before figure, cannot meet more
Carry out higher plating lsp request.
A, gold-plated plating and etching are not clean.In the electroless coating region of dry film covering, not due to the binding force of dry film and copper face
Enough big, when gold-plated, dry film is easy to fall off around plating area or liquid medicine easily infiltrates under dry film, is caused and phase around plating area
There is plating gold in the big copper face of connection, and in subsequent etch, these copper faces for oozing plating area are difficult to etch clean.
B, plating area collapses.Because being connected with big copper face around plating area, when subsequent etch finished surface line map
When shape, the layers of copper below plating area is easy to be snapped eating away, plating area occurs and collapses.
C, plating short circuit.Circuit board surface circuit is susceptible to plating short circuit when closeer.
Therefore, craft of gilding does not process high-density line before figure, cannot produce high-precision size circuit plate.
Thin copper method partially plating gold technique is that surface lines figure is first produced on the surface metal-layer of circuit board, then to whole
A surface metal-layer carries out heavy copper, then, using heavy layers of copper as glodclad wire, other regions is covered with dry film, to needing electricity
It is gold-plated to plate region progress；It is gold-plated to finish, remove heavy layers of copper.But thin copper method partially plating gold technique has the disadvantage that：
A, produced it is rough and uneven in surface on the surface metal-layer of surface lines figure, cover dry film when be easy to cause dry film pleat
Wrinkle is even damaged so that the region that should not be plated is gold-plated；
B, the process for copper that sinks can adhere to one layer of Metal Palladium on the base material that trace clearance exposes, and this layer of Metal Palladium is difficult to be had
Effect removal is subsequently likely to result in surface line figure short circuit.
Invention content
The embodiment of the present invention provides a kind of electro-plating method of circuit board, to solve craft of gilding and thin copper before existing figure
Drawbacks described above existing for method partially plating gold technique, for processing the circuit required with high-density line and high-precision size
Plate.
The electro-plating method of circuit board provided by the invention, including：The surface metal-layer of circuit board is processed as line layer；It will
The electroless coating region etching of the line layer subtracts thickness；Subtract thick electroless coating region setting dielectric having etched；To institute
The plating area for stating line layer is electroplated.
Therefore the embodiment of the present invention etches the electroless coating region of line layer using after processing surface line layer
Subtract thickness and dielectric be set and protected, then, to the technical solution that the plating area of line layer is electroplated, achieve with
Lower technique effect：
Relative to electroplating technology before existing figure, after plating step is placed on line pattern step, and it is electroplated
It is not big copper face around region but dielectric, the only circuit top surface that plating area is exposed, it can thus be avoided gold-plated
It permeates and etches not clean and plating area and collapse the problems such as short-circuit with plating.
Relative to thin copper method partially plating gold technique, since electroless coating region is provided with dielectric, be no longer convex-concave not
Flat circuit, therefore, the plating resist film of covering will not fold or breakage, and heavy layers of copper and line layer are kept apart by dielectric, no
Line pattern can be caused short-circuit because of heavy layers of copper residual.
As it can be seen that technical solution of the present invention solve it is above-mentioned existing for electroplating technology and thin copper method partially plating gold technique before figure
Defect, can process has more highdensity line pattern, can produce the circuit board with high-precision size.
Description of the drawings
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to institute in embodiment and description of the prior art
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the schematic diagram of the electro-plating method of circuit board provided by one embodiment of the present invention；
Fig. 2 is the schematic diagram of the electro-plating method for the circuit board that another embodiment of the present invention provides；
Fig. 3 a-3i be present invention method each step in circuit board schematic diagram.
Specific implementation mode
The embodiment of the present invention provides a kind of electro-plating method of circuit board, to solve craft of gilding and thin copper before existing figure
Drawbacks described above existing for method partially plating gold technique, for processing the circuit required with high-density line and high-precision size
Plate.
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model that the present invention protects
It encloses.
Below by specific embodiment, it is described in detail respectively.
Referring to FIG. 1, the embodiment of the present invention provides a kind of electro-plating method of circuit board, it may include：
110, the surface metal-layer of circuit board is processed as line layer.
In the present embodiment, described circuit board can be single-side coated copper plate or double face copper, can also be based on single side
Or multi-layer board made of double face copper lamination, for the concrete structure and preparation method thereof of the circuit board, the embodiment of the present invention
Not limit.In general, the circuit board includes at least one layer of insulating layer and at least one layer of metal layer.Present invention method is used
In being electroplated on the surface metal-layer in the circuit board.
In the present embodiment, the surface metal-layer of circuit board one or both sides is processed as line layer first.Wherein, by surface
Conventional processing technology may be used in the technique that metal layer is processed as line layer, and the embodiment of the present invention not limits this.Surface
On the line layer that metal layer is process, the region being electroplated, referred to as plating area can specifically include some pads
Or circuit etc.；Other regions that need not be electroplated, then referred to as electroless coating region.
120, the etching of the electroless coating region of the line layer is subtracted into thickness.
In this step, the electroless coating region etching on circuit board surface line layer is subtracted into thickness so that plating area is higher than non-
Plating area.It is reduced to nearly or only slight beyond original thickness in general, the copper thickness in electroless coating region can be etched
Half.Wherein, etching subtracts thick step and may include：
Etchant resist is covered in the plating area of line layer；The electroless coating region of the uncovered etchant resist of line layer is carried out
Etching subtracts thickness；Remove etchant resist.
Wherein, described etchant resist can be specifically dry film against corrosion or wet film against corrosion.The described electroplating region in line layer
Domain covering etchant resist may include：After the full surface covering etchant resist of line layer, operated electroless coating region by exposed and developed
Etchant resist removal, only retain plating area etchant resist.The electroless coating area of the described uncovered etchant resist to line layer
Domain, which is etched, to be subtracted thickness and may include：The circuit board for having covered etchant resist is placed in electroplating bath, is taken after the plating setting time that is powered
Go out, detects whether to have reached requirement.Described removal etchant resist may include：Etchant resist is removed by the methods of alkali etching.
In a kind of embodiment, the thickness of the surface metal-layer of circuit board can be 3-5 ounces（It is micro- that OZ, 1OZ are approximately equal to 35
Rice）, such as 4OZ, it may include correspondingly, the electroless coating region etching of the line layer is subtracted thickness：By the non-electrical of the line layer
The etching of plating region subtracts thickness to 1-2 ounces.
130, the electroless coating region setting dielectric for subtracting thickness is being etched.
In this step, the electroless coating region setting dielectric for subtracting thickness is being etched in circuit board surface line layer, but
Expose plating area, and the line layer flush of set dielectric and plating area.In the embodiment of the present invention, if
The step of setting dielectric may include：
Dielectric is laminated on line layer；The surface layer for removing dielectric, makes the electroplating region of dielectric and line layer
Field surface is concordant, to expose plating area.
Wherein it is possible to slot in advance in the position corresponding to plating area of dielectric, in order to be laminated.Described is exhausted
Edge medium can be specifically prepreg, that is, the PP pieces often said, PP pieces are one of the main materials in multi-layer board production, mainly
It is made of resin and reinforcing material, reinforcing material is divided into as several types such as glass-fiber-fabric, paper substrate, composite materials.Described removal
The surface layer of dielectric can be removed by controlled depth milling technique, by the depth for controlling controlled depth milling so that the height of dielectric
The part for going out plating area is removed.
In some embodiments of the invention, in order to ensure lamination, in specific lamination process, it can be set above line layer
Dielectric is set, one layer of false core plate is then set above dielectric, is then laminated.Described false core plate is also one layer of insulation
Material, but its hardness is more than prepreg.The vacation core plate is only used for auxiliary lamination, can't really be pressed on circuit board,
Even if alternatively, pressing on circuit board, removed also by techniques such as controlled depth millings.
140, the plating area of the line layer is electroplated.
After above-mentioned setting dielectric step, circuit board surface includes two regions, and one is plating area, the area
In domain, the line layer for needing to be electroplated is exposed；The other is electroless coating region, which is covered by insulating resin, the region
Interior line pattern is entirely located in below insulating resin, without being exposed.
In this step, the plating area of the line layer to being exposed is electroplated, and described plating can be electricity
Gold-plated, nickel is golden or NiPdAu etc..The plating step may include：
Heavy layers of copper is generated in circuit board surface；In the electroless coating region overlay plating resist film of circuit board surface；It is anti-to not covering
The plating area of plated film is electroplated；Remove the heavy layers of copper of plating resist film and electroless coating region.
Wherein, using heavy process for copper the heavy layers of copper covering board surface that circuit board surface generates electroless coating region and
Plating area, the heavy layers of copper of generation will be used to be used as electroplate lead wire in following electroplating process.Usually heavy layers of copper is very thin by one
Layer after generating heavy layers of copper, can also increase plating step to improve reliability, to regenerate electricity in heavy layers of copper
Coating（It can be described as heavy copper electroplated layer）.The heavy layers of copper and the overall thickness of electroplated layer can be between 5-10 micron, to be played good with guarantee
Good conductive effect.
The electroless coating region overlay plating resist film of described circuit board surface may include：Plating resist film is covered on the full surface of circuit board
Afterwards, the plating resist film that plating area is removed by exposed and developed operation, only retains the plating resist film in electroless coating region, that is to say, that
Only retain the plating resist film on set dielectric.
Described is electroplated concretely the plating area for not covering plating resist film：With heavy layers of copper or heavy copper electroplated layer
For electroplate lead wire, to plating area electroplating gold, nickel gold or NiPdAu etc..
Plating finishes, and the heavy layers of copper of plating resist film and electroless coating region can be removed by alkaline etching process.
More than, an embodiment of the present invention provides a kind of electro-plating method of circuit board, this method uses and processes surface line
After layer, the electroless coating region etching of line layer is subtracted thickness and dielectric is arranged and is protected, then, to the electroplating region of line layer
The technical solution that domain is electroplated achieves following technique effect：
Relative to electroplating technology before existing figure, after plating step is placed on line pattern step, and it is electroplated
It is not big copper face around region but dielectric, the only circuit top surface that plating area is exposed, it can thus be avoided gold-plated
It permeates and etches not clean and plating area and collapse the problems such as short-circuit with plating.
Relative to thin copper method partially plating gold technique, since electroless coating region is provided with dielectric, be no longer convex-concave not
Flat circuit, therefore, the plating resist film of covering will not fold or breakage, and heavy layers of copper and line layer are kept apart by dielectric, no
Line pattern can be caused short-circuit because of heavy layers of copper residual.
As it can be seen that technical solution of the present invention solve it is above-mentioned existing for electroplating technology and thin copper method partially plating gold technique before figure
Defect, can process has more highdensity line pattern, can produce the circuit board with high-precision size.
The technical solution that embodiment provides to facilitate the understanding of the present invention, below by the reality under a concrete scene
It applies and is introduced for mode.
Referring to FIG. 2, the electro-plating method of another circuit board of the embodiment of the present invention, it may include：
201, as best shown in figures 3 a and 3b, line layer 310 is produced on the surface metal-layer of circuit board 300.The line layer
310 include needing gold-plated plating area 301 and not needing gold-plated electroless coating region 302.The thickness of the line layer is assumed to
4OZ.Before making line layer 310, if the thickness of surface metal-layer less than 4OZ, can be by electroplating surface mode by surface
Metal layer plating is thickeied to 4OZ.
202, as shown in Figure 3c, the plating area of line layer 310 dry film 401 against corrosion is covered, but expose electroless coating
Region.
203, as shown in Figure 3d, remove dry film against corrosion after the etching of electroless coating region being subtracted thickness to 1-2OZ using etch process
401。
204, as shown in Figure 3 e, dielectric 320 is pressed on line layer 310, which corresponds to plating
The position in region has fluting.
205, as illustrated in figure 3f, using whole plate controlled depth milling technique, the surface layer resin of dielectric 320 is reamed, until exposing
The plating area of line layer 310, electroless coating region are not exposed by 320 covering protection of dielectric then.
206, as shown in figure 3g, a packet is formed in the heavy copper of circuit board surface whole plate and plating using heavy copper-electroplating technology
The metal layer 330 of heavy layers of copper and electroplated layer is included, the copper thickness of the metal layer can be 5-10um.
207, as illustrated in figure 3h, electroless coating region is covered using plating resist dry film 402, exposes plating area, then, with metal
Layer 330 is electroplate lead wire, carries out normal electroplating gold, nickel gold or NiPdAu to plating area, forms electroplated layer 340.
208, as shown in figure 3i, removal plating resist dry film 402 after the completion of plating is completed, alkaline etching process of going further removes non-electrical
Metal layer that area thickness is 5-10um is plated to get to required circuit board.
Therefore in some feasible embodiments of the present invention, after processing surface line layer, by line layer
The etching of electroless coating region, which subtracts thickness and dielectric is arranged, to be protected, and then, the plating area of line layer is electroplated, due to
It is not big copper face around plating area but dielectric, it can thus be avoided gold-plated permeate and etch not clean and plating
Region collapses the problems such as short-circuit with plating；No longer it is scraggly circuit since electroless coating region is provided with dielectric,
Therefore, the plating resist film of covering will not fold or breakage, and heavy layers of copper and line layer are kept apart by dielectric, will not be because sinking layers of copper
Residual causes line pattern short-circuit.As it can be seen that technical solution of the present invention solves electroplating technology and thin copper method partially plating gold before figure
Drawbacks described above existing for technique, can process has more highdensity line pattern, can produce with high-precision size
Circuit board.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, is not described in some embodiment
Part, may refer to the associated description of other embodiments.
It should be noted that for each method embodiment above-mentioned, for simple description, therefore it is all expressed as a series of
Combination of actions, but those skilled in the art should understand that, the present invention is not limited by described sequence of movement because according to
According to the present invention, certain steps may be used other sequences or be carried out at the same time.Next, those skilled in the art should also know that,
Embodiment described in this description belongs to preferred embodiment, and not necessarily the present invention must for involved action and module
Must.
The electro-plating method for being provided for the embodiments of the invention circuit board above is described in detail, but above example
Explanation be merely used to help understand the present invention method and its core concept, should not be construed as limiting the invention.This skill
The technical staff in art field, according to the thought of the present invention, in the technical scope disclosed by the present invention, the variation that can readily occur in or
It replaces, should be covered by the protection scope of the present invention.
Claims (10)
1. a kind of electro-plating method of circuit board, which is characterized in that including：
The surface metal-layer of circuit board is processed as line layer；
The electroless coating region etching of the line layer is subtracted into thickness；
Subtract thick electroless coating region setting dielectric having etched, the dielectric is prepreg；
The plating area of the line layer is electroplated.
2. according to the method described in claim 1, it is characterized in that, described subtract thickness by the electroless coating region etching of the line layer
Including：
Etchant resist is covered in the plating area of the line layer；
The electroless coating region of the uncovered etchant resist of the line layer is etched and subtracts thickness；
Remove the etchant resist.
3. method according to claim 1 or 2, which is characterized in that the thickness of the surface metal-layer is 3-5 ounces, phase
It answers, the electroless coating region etching by the line layer subtracts thickness and includes：
The electroless coating region etching of the line layer is subtracted into thickness to 1-2 ounces.
4. according to the method described in claim 1, it is characterized in that, described etching the electroless coating region setting for subtracting thickness
Dielectric includes：
It is laminated dielectric on the line layer；
The surface layer for removing the dielectric makes the plating area flush of the dielectric and the line layer, with sudden and violent
Expose the plating area.
5. according to the method described in claim 4, it is characterized in that, described be laminated before dielectric also on the line layer
Including：
It slots in the position corresponding to the plating area of the dielectric.
6. according to the method described in claim 4, it is characterized in that, the dielectric includes prepreg.
7. according to the method described in claim 4, it is characterized in that, removing the table of the dielectric using controlled depth milling technique
Layer.
8. according to the method described in claim 1, it is characterized in that, the plating area to the line layer carries out plating packet
It includes：
Heavy layers of copper is generated in the circuit board surface；
In the electroless coating region overlay plating resist film of the circuit board surface；
Plating area to not covering plating resist film is electroplated；
Remove the heavy layers of copper of the plating resist film and the electroless coating region.
9. according to the method described in claim 8, it is characterized in that, described be electroplated the plating area for not covering plating resist film
Including：
Plating area to not covering plating resist film carries out electroplating gold, nickel gold or NiPdAu.
10. according to the method described in claim 8, it is characterized in that, removing the electroless coating region using alkaline etching process
Heavy layers of copper.
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| CN201310672062.2A CN104703401B (en) | 2013-12-10 | 2013-12-10 | A kind of electro-plating method of circuit board |
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| CN201310672062.2A CN104703401B (en) | 2013-12-10 | 2013-12-10 | A kind of electro-plating method of circuit board |
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| CN104703401B true CN104703401B (en) | 2018-08-03 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106191935A (en) * | 2016-08-11 | 2016-12-07 | 强半导体（苏州）有限公司 | Electrogilding technique for chip testing connecting plate |
| CN107920427B (en) * | 2016-10-09 | 2020-07-14 | 北大方正集团有限公司 | Preparation method of metal connection structure of circuit board and printed circuit board |
| CN109994660B (en) * | 2019-03-15 | 2023-12-05 | 福建南平南孚电池有限公司 | Rechargeable battery with improved circuit unit |
| CN110602889A (en) * | 2019-10-21 | 2019-12-20 | 深圳市中基自动化有限公司 | Contact circuit board process for lithium battery formation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200304351A (en) * | 2003-04-29 | 2003-09-16 | Mutual Tek Ind Co Ltd | Manufacturing method of thin integrated circuit with multi-layered circuit |
| CN102373492A (en) * | 2010-08-13 | 2012-03-14 | 北大方正集团有限公司 | Method for carrying out selective electroplating on surface of circuit board, and circuit board |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222136B1 (en) * | 1997-11-12 | 2001-04-24 | International Business Machines Corporation | Printed circuit board with continuous connective bumps |
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2013
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200304351A (en) * | 2003-04-29 | 2003-09-16 | Mutual Tek Ind Co Ltd | Manufacturing method of thin integrated circuit with multi-layered circuit |
| CN102373492A (en) * | 2010-08-13 | 2012-03-14 | 北大方正集团有限公司 | Method for carrying out selective electroplating on surface of circuit board, and circuit board |
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