CN104701381A - 一种p柱区阶梯掺杂的二维类sj/resurf ldmos器件及其制造方法 - Google Patents

一种p柱区阶梯掺杂的二维类sj/resurf ldmos器件及其制造方法 Download PDF

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CN104701381A
CN104701381A CN201510095284.1A CN201510095284A CN104701381A CN 104701381 A CN104701381 A CN 104701381A CN 201510095284 A CN201510095284 A CN 201510095284A CN 104701381 A CN104701381 A CN 104701381A
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heavy doping
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俞露露
成建兵
刘雪松
袁晴雯
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Nanjing Post and Telecommunication University
Nanjing University of Posts and Telecommunications
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Abstract

本发明公开了一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件及其制造方法，本发明创新之处在于，用RESURF结构与二维超结结构相结合的漂移区代替常规LDMOS的单一轻掺杂漂移区。如图所示，靠近源极的一侧采用二维横向超结结构，靠近漏极一侧采用RESURF结构。本发明又将变掺杂的思想引入新结构，将漂移区超结中的P柱区进行阶梯掺杂，掺杂浓度由源极到漏极逐渐降低。新型的P柱区阶梯掺杂的二维类SJ/RESURF LDMOS结构可以消除衬底辅助耗尽效应，平衡漂移区的电荷，提高器件击穿电压的同时保持了器件好的导通电阻特性。本发明的思想是从体内调制表面和体内电场，并且体内调制还有不会在表面形成场的突变的优点，因此，热载流子不容易进入其上的场氧中，如此则提高了场氧的可靠性，进而提高了器件的可靠性。此外，新结构工艺简单，可进一步降低生产成本。

Description

一种P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件及其制造方法
技术领域
本发明属于电子技术领域，特别涉及具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS半导体功率器件。
背景技术
LDMOS器件作为多子器件，由于具有良好的关断特性、高的输入阻抗、易于大规模集成电路兼容等优点，在许多领域取代传统的双极器件得到广泛的应用。对于LDMOS优化设计的最重要的目的就是在获得最大击穿电压的同时导通电阻尽可能小。由于此类多子器件导电层掺杂浓度和导电层厚度的乘积等于一常量，因此这两个参数往往是相互矛盾的，高的击穿电压必然带来高的导通电阻。然而，获得理想的击穿电压和比导通电阻性能的折中关键在于漂移区的优化设计。目前，国内外学者针对漂移区的优化提出了多种新结构，如RESURF LDMOS,SOI LDMOS,SJ-LDMOS等。
发明内容
本发明提供了一种解决上述问题的方案，提出了一种可以提高器件耐压却不增加导通电阻的具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件，与三维SJ/RESURF LDMOS器件相比，简化了工艺流程，降低了生产成本。
为解决上述技术问题，本发明提供了一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件，包括：包括衬底；衬底之上有阱；衬底之上的一侧是低掺杂N-型外延区、该N-型外延区内有作为器件漏极的重掺杂注入区，衬底之上另一侧的阱中有沟道区、该沟道区中有重掺杂阱和作为器件源极的重掺杂注入区，衬底之上漏极一侧的低掺杂N-型外延区和衬底之上源极一侧的沟道区之间是P型重掺杂注入区和N型重掺杂注入区，所述P型重掺杂注入区紧贴衬底排列，所述N型重掺杂注入区紧贴P型重掺杂注入区排列，在源极一侧形成超结结构，在漏极一侧形成RESURF结构，所述P型重掺杂注入区为阶梯掺杂，掺杂浓度从源级一侧到漏极一侧逐渐降低；沟道区上是栅氧化层和栅电极，栅电极的两端都在沟道区之上；阱之上为场氧化层。如本说明书附图4：在P型硅衬底10上具有N型阱；衬底之上一侧为低掺杂的N-型外延层11,该N-型外延层11中有一个作为器件漏极的N型重掺杂漏注入区15；衬底之上另一侧的阱中具有P型沟道区14；沟道区14中具有P型重掺杂阱17和作为器件源极的N型重掺杂注入区16；阱中具有N型重掺杂注入区12和由源端到漏端阶梯分布的P型重掺杂注入区13；沟道区14上是栅氧化层19和栅电极20，栅电极20的两端都在沟道区14之上；阱之上为场氧化层18。
本发明一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件，其掺杂类型是，所述硅衬底10、重掺杂注入区13、沟道结构的沟道区14、重掺杂阱17为P型；轻掺杂外延层11、重掺杂注入区12、重掺杂的漏注入区15、重掺杂注入区16为N型。本发明的P柱区阶梯掺杂为1阶或1阶以上阶梯掺杂。
本发明还提供了一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件的制造方法，包括以下步骤：
步骤1：在P型硅衬底10上生长一定厚度但掺杂浓度较低的轻掺杂外延层，即N-型阱，作为LDMOS的漂移区；
步骤2：在轻掺杂的外延层中分别注入重掺杂的P型区13和N型区12；
步骤3：利用同一窗口，先进行P阱注入硼，通过长时间的退火工艺使杂质向体内扩散，形成一定的结深，然后继续注入主杂质砷形成器件的源级接触16，由于硼比砷扩散快，两次注入扩散的差值就形成了沟道区14；
步骤4：在阱14中注入重掺杂区P型阱17，在衬底之上一侧的轻掺杂外延层11中离子注入形成重掺杂N型注入区阱15，重掺杂N型注入区阱15则为该LDMOS器件的漏极； 
步骤5：在硅片表面形成栅氧化层19、场氧化层18和栅电极20。
在上述步骤2中，重掺杂的N型区12的深度占轻掺杂的N型外延层的3/10，重掺杂的P型区13的深度占轻掺杂的N型外延层的7/10。
在上述步骤2中，重掺杂的N型区12的掺杂浓度为9e15cm-3，重掺杂的P型区13的掺杂浓度从源极到漏极逐渐降低，呈阶梯分布，依次为P1：5e15cm-3、P2：3.5e15cm-3、P3:1e15cm-3。
如图4结构改为N柱区阶梯掺杂，掺杂浓度由源极到漏极逐渐增加，P柱区均匀掺杂则为本发明的变形结构。
本发明所述的一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件，主要是对漂移区的结构进行的优化设计。较之普通的RESURF LDMOS结构，该器件结构的漂移区由两部分组成，在漂移区的源侧为超结区，漏测为RESURF结构区。
与三维的SJ/RESURF LDMOS相比，区别之处在于：本发明提出的新结构超结区由横向的P柱区和N柱区构成，同时，P柱区采用的是阶梯掺杂，掺杂浓度从源侧到漏测逐渐降低。此P柱区采用的原理和主要作用是：在器件反向耐压的时候，根据衬底辅助耗尽效应的机理，P柱区中会出现一些多余电荷，且多余电荷的浓度由源到漏逐渐增加，本发明提出的结构可以充分降低多余电荷的产生，经过对P柱区、N柱区宽度以及掺杂浓度的优化设计，可以使得超结中的P柱区和N柱区之间的电荷达到平衡，减弱衬底辅助衬底辅助耗尽效应对横向超 结LDMOS性能的影响。
本发明的有益效果：
1、P柱区电荷掺杂浓度的阶梯变化可以调制器件的体电场，同时使得P柱区出现多个缓变结，从而在漂移区内部产生多个电场峰值区，进而提高器件的耐压；
2、与以往的N柱区阶梯掺杂相比，本文采用的P柱区阶梯掺杂可以提高N柱区掺杂浓度，开态时导通电阻被进一步降低。
3、与三维的SJ/RESURF LDMOS结构不同，本发明器件的工艺实现更加简单，可降低生产成本。
附图说明
图1是普通RESURF LDMOS器件的剖面示意图；
图2是常规的二维SJ/RESURF LDMOS器件的剖面示意图；
图3是本发明一种具有P柱区1阶阶梯掺杂的二维类SJ/RESURF LDMOS器件；
图4是本发明一种具有P柱区2阶阶梯掺杂的二维类SJ/RESURF LDMOS器件；
标识说明：10-P型硅衬底；11-衬底之上一侧的N-型轻掺杂外延层；12-重掺杂N型注入区；13-重掺杂P型注入区；14-P型沟道；15-N型重掺杂漏注入区；16-N型重掺杂注入区；17-重掺杂P阱；18-场氧化层；19-栅氧化层；20-栅电极；
具体实施方式
下面对本发明的具体实施方式作进一步的详细描述。
如图4，本发明的具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件为：在P型硅衬底10上具有N型阱；衬底之上一侧为低掺杂的N-型外延层11,该N-型外延层11中有一个作为器件漏极的N型重掺杂漏注入区15；衬底之上另一侧的阱中具有P型沟道区14；沟道区14中具有P型重掺杂阱17和作为器件源极的N型重掺杂注入区16；阱中具有N型重掺杂注入区12和由源端到漏端阶梯分布的P型重掺杂注入区13；沟道区14上是栅氧化层19和栅电极20，栅电极20的两端都在沟道区14之上；阱之上为场氧化层18。
与传统的普通RESURF LDMOS器件相比，本发明的创新在于，将二维横向超结结构引入传统的单一掺杂的N-型漂移区，使得器件的漂移区分为两个部分，如图2所示，漂移区左侧大部分是超结区，只有靠近漏端的一小部分为RESURF区。
本发明的常规二维类SJ/RESURF LDMOS器件的制造方法包括以下步骤(如图2所示，以N型LDMOS为例进行介绍，P型LDMOS只需将各步骤的离子注入类型相反，各部分结构的掺杂类型相反即可)：
步骤1：在P型硅衬底10上生长一定厚度但掺杂浓度较低的N型外延层11，作为LDMOS的漂移区； 
步骤2：在上述轻掺杂的N型外延层11中分别注入重掺杂的P型区13和N型区12；
步骤3：利用同一窗口，先进行P阱注入硼，通过长时间的退火工艺使杂质向体内扩散，形成一定的结深，然后继续注入施主杂质砷形成源级接触16。由于硼比砷扩散快，两次注入扩散的差值就形成了沟道区14；
步骤4：在阱14中注入重掺杂区P型阱17，在阱11中离子注入形成重掺杂N型注入区阱15，重掺杂N型注入区阱15则为该LDMOS器件的漏极； 
步骤5：在硅片表面形成栅氧化层19、场氧化层18和栅电极20。
高的击穿电压与低的导通电阻对LDMOS器件而言是一个重要的性能指标，而高的击穿电压必然带来高的导通电阻，为了获得击穿电压与导通电阻间的折中，除了改变器件的结构，调整好各区的掺杂浓度与宽度也是至关重要的。
步骤1中，P型硅衬底的掺杂浓度为2e13cm-3。
步骤2中，超结区由横向的N柱和P柱构成，N柱位于P柱之上，分布在漂移区的表面，这样的一个构造比可以提高N柱的掺杂浓度，在相同耐压下降低器件的导通电阻。通过MEDICI仿真得到最优的N柱区与P柱区的深度比为3/7，最优的掺杂浓度为，超结区中N柱区的掺杂浓度为9e15cm-3，P柱的掺杂浓度为4e15cm-3，N-型RESURF区掺杂浓度为5e14cm-3。低于或高于仿真的最优值都会降低器件的击穿电压。在相同的掺杂浓度下，随着漂移区长度的增加，器件的击穿电压也会跟着提高。
与传统的普通RESURF LDMOS器件相比，本发明的创新之2，即本发明的重点在于，将超结区中的P柱区进行阶梯掺杂，掺杂浓度从源侧到漏测逐渐降低。此P柱层采用的原理和主要作用是：在器件反向耐压的时候，根据衬底辅助耗尽效应的机理，P柱中会出现一些多余电荷，且多余电荷的浓度由源到漏逐渐增加，本发明提出的结构可以充分降低多余电荷的产生，经过对P柱、N柱宽度以及掺杂浓度的优化设计，可以使得超结中的P柱区和N柱区之间的电荷达到平衡，减弱衬底辅助衬底辅助耗尽效应对横向超结LDMOS性能的影响。一方面，P柱层电荷掺杂浓度的阶梯变化可以调制器件的体电场，同时使得P柱层出现多个缓变结，从而在漂移区内部产生多个电场高峰，进一步提高器件的耐压；另一方面，与以往的N柱区阶梯掺杂相比，本文采用的P柱层阶梯掺杂可以提高N柱掺杂浓度，开态时导通电阻被进一步降低。
图3所示是P柱区具有1阶阶梯分布的二维类SJ/RESURF LDMOS，图4所示是P柱区具有2阶阶梯分布的二维类SJ/RESURF LDMOS，随着阶梯数的增加，漂移区的浓度分布接近线性分布，从而使漂移区的电场均匀分布，器件的击穿电压得到进一步的提高。
本发明所述的具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件即在原常规二维类 SJ/RESURF LDMOS器件的基础上，将P柱区进行阶梯掺杂，如图4所示，掺杂浓度从源极到漏极逐渐降低，呈阶梯分布，依次为P1：5e15cm-3、P2：3.5e15cm-3、P3:1e15cm-3。
与三维的SJ/RESURF LDMOS结构相似，本发明的器件工艺更加简单，进一步降低生产成本。
上述实施例中的结构、步骤、数值等均为示意，在不违反本发明思想的前提下，本领域的一般技术人员可以进行同等替换，也可以做出若干变形和改进，这些都属于本发明的保护范围。

Claims (6)

1.一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件，其特征在于:包括衬底；衬底之上有阱；衬底之上的一侧是低掺杂N-型外延区、该N-型外延区内有作为器件漏极的重掺杂注入区，衬底之上另一侧的阱中有沟道区、该沟道区中有重掺杂阱和作为器件源极的重掺杂注入区，衬底之上漏极一侧的低掺杂N-型外延区和衬底之上源极一侧的沟道区之间是P型重掺杂注入区和N型重掺杂注入区，所述P型重掺杂注入区紧贴衬底排列，所述N型重掺杂注入区紧贴P型重掺杂注入区排列，在源极一侧形成超结结构，在漏极一侧形成RESURF结构，所述P型重掺杂注入区为阶梯掺杂，掺杂浓度从源级一侧到漏极一侧逐渐降低；沟道区上是栅氧化层和栅电极，栅电极的两端都在沟道区之上；阱之上为场氧化层。
2.根据权利要求1所述的一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件，其特征是:在P型硅衬底(10)上具有N型阱；衬底之上一侧为低掺杂的N-型外延区(11),该N-型外延区(11)中有一个作为器件漏极的N型重掺杂漏注入区(15)；衬底之上另一侧的阱中具有P型沟道区(14)；沟道区(14)中具有P型重掺杂阱(17)和作为器件源极的N型重掺杂注入区(16)；阱中具有N型重掺杂注入区(12)和由源端到漏端阶梯分布的P型重掺杂注入区(13)；沟道区(14)上是栅氧化层(19)和栅电极(20)，栅电极(20)的两端都在沟道区(14)之上；阱之上为场氧化层(18)。
3.根据权利要求1或2所述的一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件，其特征是：P柱区为1阶或1阶以上阶梯参杂。
4.一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件的制造方法，其特征是，包括以下步骤：
步骤1：在P型硅衬底(10)上生长一定厚度但掺杂浓度较低的轻掺杂N-型阱；
步骤2：在轻掺杂的N-型阱中分别注入P型重掺杂区(13)和N型重掺杂区(12)；
步骤3：利用同一窗口，先进行P阱注入硼，通过退火工艺使杂质向体内扩散，形成结深，然后继续注入主杂质砷形成重掺杂注入区(16)形成器件的源极，由于硼比砷扩散快，两次注入扩散的差值就形成了沟道区(14)；
步骤4：在沟道区(14)中注入P型重掺杂阱(17)，在衬底之上一侧的N-型轻掺杂外延层(11)中离子注入形成N型重掺杂漏注入区(15)；
步骤5：在硅片表面形成栅氧化层(19)、场氧化层(18)和栅电极(20)。
5.根据权利要求4所述一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件的制造方法，其特征是:所述步骤2中，N型重掺杂注入区(12)的深度占轻掺杂的N-型阱的3/10，P型重掺杂注入区(13)的深度占轻掺杂的N-型阱的7/10。
6.根据权利要求4所述一种具有P柱区阶梯掺杂的二维类SJ/RESURF LDMOS器件的制造方法，其特征是:所述步骤2中，N型重掺杂注入区(12)的掺杂浓度为9e15cm-3，P型重掺杂注入区(13)的掺杂浓度从源极到漏极逐渐降低，呈阶梯分布，依次为P1：5e15cm-3、P2：3.5e15cm-3、P3:1e15cm-3。
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