CN104701268B - 智能功率模块 - Google Patents

智能功率模块 Download PDF

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CN104701268B
CN104701268B CN201310667409.4A CN201310667409A CN104701268B CN 104701268 B CN104701268 B CN 104701268B CN 201310667409 A CN201310667409 A CN 201310667409A CN 104701268 B CN104701268 B CN 104701268B
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CN104701268A (zh
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聂世义
王晓宝
赵善麒
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JIANGSU MACMIC TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

本发明涉及一种智能功率模块，集成电路芯片和器件分别通过铝丝与铝基覆铜板键合；半导体单元模块包括铜基板、半导体芯片和快恢复二极管芯片，铜基板固定在铝基覆铜板上，半导体芯片的集电极和快恢复二极管芯片的阴极与铜基板连接，半导体芯片的发射极和栅极以及快恢复二极管芯片的阳极通过铝丝与铝基覆铜板连接，各电极端子和各信号端子分别嵌接在外壳的侧壁上，各电极端子和各信号端子的下部通过铝丝与铝基覆铜板连接，外壳内填充有硅凝胶并将集成电路芯片、器件和半导体单元模块密封，盖板连接在外壳上。本发明能将半导体芯片、快恢复二极管芯片和集成电路芯片混合封装在铝基覆铜板，缩小整体尺寸，提高散热效果，并能降低制作成本。

Description

智能功率模块
技术领域
本发明涉及一种智能功率模块，属于功率模块制造技术领域。
背景技术
大功率半导体模块是一种标准外形尺寸和非标准外形尺寸模块产品。智能功率模块主要用于直流（DC）变交流(AC)的逆变转换，用于给工业和民用空调进行变频控制，提高用电效率，降低能耗。传统智能功率半导体模块主要包括外壳、主电路板和驱动电路板，半导体芯片、多个电极端子和信号端子焊接在覆金属陶瓷基板并构成主电路板，而焊接有集成电路芯片及各器件的印刷电路板构成驱动电路板，为减小功率模块的体积，是将驱动电路板通过螺钉安装外壳上，各端子需穿出外壳盖板上的端子孔和驱动电路板上的端子孔，再通过焊料将端子焊接在驱动电路板上，通过端子实现与功率半导体模块外部电路的连接以及驱动信号的输入输出，但上述结构是将半导体芯片焊接在覆金属陶瓷基板，集成电路芯片以及各器件是焊接在印刷电路板，一方面无法进一步减小智能功率模块的体积，另一方面也无法对集成电路芯片进行散热。
发明内容
本发明的目的是提供一种能将半导体芯片、快恢复二极管芯片和集成电路芯片混合封装在铝基覆铜板，缩小整体尺寸，提高散热效果，并能降低制作成本的智能功率模块。
本发明为达到上述目的的技术方案是：一种智能功率模块，其特征在于：包括外壳，固定在外壳底部的铝基覆铜板、复数个电极端子、复数个信号端子、集成电路芯片以及器件和三组以上的半导体单元模块，集成电路芯片和器件分别通过铝丝与铝基覆铜板键合；所述的半导体单元模块包括铜基板、半导体芯片和快恢复二极管芯片，铜基板固定在铝基覆铜板上，半导体芯片的集电极和快恢复二极管芯片的阴极与铜基板连接，半导体芯片的发射极和栅极以及快恢复二极管芯片的阳极通过铝丝与铝基覆铜板连接，各电极端子和各信号端子分别嵌接在外壳的侧壁上，各电极端子和各信号端子的下部通过铝丝与铝基覆铜板连接，外壳内填充有硅凝胶并将集成电路芯片、器件和半导体单元模块密封，盖板连接在外壳上。
本发明将半导体芯片及快恢复二极管芯片与铜基板连接，代替传统半导体芯片和快恢复二极管芯片先焊在覆金属陶瓷基板，再将覆金属陶瓷基板焊在铜基板上，由于省掉覆金属陶瓷基，半导体芯片的热量直接通过铜基板而传至铝基覆铜板，提高了半导体芯片的散热能力，同时也提高半导体芯片工作温度和使用效率。本发明半导体芯片及快恢复二极管芯片通过铜基板与铝基覆铜板连接，同时也将集成电路芯片连接在铝基覆铜板上，实现了裸片即半导体芯片以及快恢复二极管芯片和单管即集成电路芯片的混合封装，能进一步缩小智能功率模块的尺寸，同时也能使器件和集成电路芯片通过铝基覆铜板下部的散热器进行散热，使器件和集成电路芯片具有一个较好的工作环境，本发明通过对半导体芯片的散热改进以及对电路进行设计，能提高变频器的使用寿命。本发明将各半导体芯片的栅极通过铝丝与铝基覆铜板实现超声键合在一起，然后铝基覆铜板再通过铝丝与嵌接在外壳上的各电极端子和信号端子进行超声键合，将栅极信号、器件信号通过信号端子引出，而半导体芯片的集电极和发射极以及恢复二极管芯片的阴极和阳极均通过电极端子引出，由于电极端子和信号端子设置在外壳上，方便与外部电路的连接。本发明由于外壳中间敞开，方便硅凝胶的灌入以及硅凝胶中气泡的排除，具有较好的工艺性。
附图说明
下面结合附图对本发明的实施例作进一步的详细描述。
图1是本发明的智能功率模块的结构示意图。
图2是本发明的智能功率模块打开盖板时的结构示意图。
图3是本发明铝基覆铜板的结构示意图。
图4是本发明电极端子和信号端子固定在壳体上的结构示意图。
图5是本发明电极端子的结构示意图。
其中：1—盖板，2—信号端子，3—外壳，4—电极端子，5—衬套，6—负温度热敏电阻，7—铝丝，8—贴片电阻，9—贴片电容，10—集成电路芯片，11—铜基板，11-1—铝层，11-2—绝缘层，11-3—铜层，11-4—镀金部分，11-5—绝缘部分，12—半导体芯片，13—快恢复二极管芯片，14—铝基覆铜板。
具体实施方式
见图1～2所示，本发明的智能功率模块，包括外壳3，固定在外壳3底部的铝基覆铜板14、复数个电极端子4、复数个信号端子2、集成电路芯片10以及器件和三组以上的半导体单元模块，外壳3和铜基板11之间是通过粘合剂和衬套5连接。见图2、3所示，本发明的铝基覆铜板14包括依次相连接的底部的铝层11-1、中部的绝缘层11-2和上部的铜层11-3，且铜层11-3上部还设有用于焊接的多处镀金部分11-4和设置在各镀金部分11-4外周、且用于阻焊的绝缘部分11-5，在铜层需要钎焊和超声键合的地方具有镀金部分，使镀金部分能与贴片电阻8、贴片电容9、集成电路芯片10、铜基板11进行钎焊，同时也能进行铝丝7的超声键合，而绝缘部分可采用涂绝缘漆，在钎焊时起阻焊作用。
见图2、3所示，本发明集成电路芯片10和器件分别通过铝丝7与铝基覆铜板14键合，该器件见图2所示，包括至少一个负温度热敏电阻6、至少三个贴片电阻8和至少三个贴片电容9，各负温度热敏电阻6、贴片电阻8和贴片电容9分别通过铝丝7与铝基覆铜板14连接，通过负温度热敏电阻6检测功率模块的温度，而贴片电阻8和贴片电容9与半导体芯片12和快恢复二极管芯片13构成电路。
见图2、3所示，本发明的半导体单元模块可采用6组，各半导体单元模块包括铜基板11、半导体芯片12和快恢复二极管芯片13，半导体芯片12可采用绝缘栅双极型晶体管、或IGBT或晶闸管等，铜基板11固定在铝基覆铜板14上，半导体芯片12的集电极和快恢复二极管芯片13的阴极与铜基板11连接，半导体芯片12的集电极和快恢复二极管芯片13的阴极焊接在铜基板11上，半导体芯片12的发射极和栅极以及快恢复二极管芯片13的阳极通过铝丝7与铝基覆铜板14连接，可通过铝丝7进行超声键合，由于省掉覆铜陶瓷基板，提高芯片的散热能力，提高芯片工作温度和使用效率。
见图4、5所示，本发明各电极端子4和各信号端子2分别嵌接在外壳3的侧壁上，本发明的电极端子4和信号端子2结构相同，电极端子4和信号端子2呈L形，由于电极端子4和信号端子2嵌接在外壳3上，能提高电极端子4和信号端子2使用寿命，可简化外壳3结构，降低外壳3成本，进而降低智能功率模块的成本，各电极端子4和各信号端子2的下部通过铝丝7与铝基覆铜板14连接，外壳3内填充有硅凝胶并将集成电路芯片10、器件和半导体单元模块密封，盖板1连接在外壳3上，盖板1通过粘合剂固定外壳3上,实现智能功率模块的密封。
见图2、4所示，本发明在外壳3的两个侧壁上分别设有凸块，该凸块呈长方形，通以实现智能功率模块与外电路连接时的间隔。

Claims (4)

1.一种智能功率模块，其特征在于：包括外壳(3)，固定在外壳(3)底部的铝基覆铜板(14)、复数个电极端子(4)、复数个信号端子(2)、集成电路芯片(10)以及器件和三组以上的半导体单元模块，集成电路芯片(10)和器件分别通过铝丝(7)与铝基覆铜板(14)键合，所述的器件包括至少一个负温度热敏电阻(6)、至少三个贴片电阻(8)和至少三个贴片电容(9)，各负温度热敏电阻(6)、贴片电阻(8)和贴片电容(9)分别通过铝丝(7)与铝基覆铜板(14)连接；所述的半导体单元模块包括铜基板(11)、半导体芯片(12)和快恢复二极管芯片(13)，铜基板(11)固定在铝基覆铜板(14)上，半导体芯片(12)的集电极和快恢复二极管芯片(13)的阴极与铜基板(11)连接，半导体芯片(12)的发射极和栅极以及快恢复二极管芯片(13)的阳极通过铝丝(7)与铝基覆铜板(14)连接，各电极端子(4)和各信号端子(2)分别嵌接在外壳(3)的侧壁上，各电极端子(4)和各信号端子(2)的下部通过铝丝(7)与铝基覆铜板(14)连接，外壳(3)内填充有硅凝胶并将集成电路芯片(10)、器件和半导体单元模块密封，盖板(1)连接在外壳(3)上。
2.根据权利要求1所述的智能功率模块，其特征在于：所述的铝基覆铜板(14)包括依次相连接底部的铝层(11-1)、中部的绝缘层(11-2)和上部的铜层(11-3)，且铜层(11-3)上部还设有用于焊接的多处镀金部分(11-4)和设置在各镀金部分(11-4)外周、且用于阻焊的绝缘部分(11-5)。
3.根据权利要求1所述的智能功率模块，其特征在于：所述的电极端子(4)和信号端子(2)结构相同，电极端子(4)和信号端子(2)呈L形。
4.根据权利要求1所述的智能功率模块，其特征在于：所述外壳(3)的两个侧壁上分别设有凸块。
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