CN201741685U - 多单元功率半导体模块 - Google Patents

多单元功率半导体模块 Download PDF

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CN201741685U
CN201741685U CN2010202666103U CN201020266610U CN201741685U CN 201741685 U CN201741685 U CN 201741685U CN 2010202666103 U CN2010202666103 U CN 2010202666103U CN 201020266610 U CN201020266610 U CN 201020266610U CN 201741685 U CN201741685 U CN 201741685U
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electrode
electrodes
copper
semiconductor chip
ceramic substrate
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王晓宝
姚玉双
姚天保
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Jiangsu Macmic Science & Technology Co Ltd
Macmic Science and Technology Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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Abstract

本实用新型涉及一种多单元功率半导体模块，包括外壳、覆铜陶瓷基板、半导体芯片和电极，半导体芯片固定在覆铜陶瓷基板上，电极与覆铜陶瓷基板或/和半导体芯片连接，所述电极安装或固定在外壳的电极插槽内，电极的连接部位具有铝层，电极上的铝层通过铝丝与覆铜陶瓷基板或/和半导体芯片连接。本实用新型的电极能通过铝层与铝丝键合，在铝丝键合工艺过程中不会出现氧化，电极能与铝丝牢固键合，能大大提高电极键合丝的拉力和剪切力，由于铝丝与铝表面为欧姆接触，通流能力与机械振动都符合设计要求，同时也解决电极与覆铜陶瓷基板存在的热应力问题，提高了半导体模块长期运行可靠性。

Description

多单元功率半导体模块
技术领域
本实用新型涉及一种多单元功率半导体模块，属于功率半导体模块制造领域。
背景技术
目前功率半导体模块连接结构一种是将半导体芯片即IGBT芯片焊接到覆铜陶瓷基板上，将带有半导体芯片的覆铜陶瓷基板再焊接到铜底板上，而将装有电极的外壳装在带有半导体芯片、覆铜陶瓷基板的铜板上，通过铝丝键合工艺，将电极连接在覆铜陶瓷基板。而电极的键合工艺又决定了半导体模块产品可靠性和成品率的关键工艺，目前的电极为插针式结构，电极的键合面为镀镍表面，在铝丝键合工艺过程中很容易氧化。因此，这种半导体模块结构主要存在以下缺陷，一是由于镀镍电极氧化而造成镀镍插针表面键合铝丝拉力和剪力达不到标准值，受振动会使键合铝丝脱落，因此电极部分键合不牢固或电极键合不上，造成半导体模块的成品率低；其次，镀镍电极氧化致使键合点接触电阻大，因此长期通电会使铝丝键合点发热直至烧熔，电极通流能力差，长期运行可靠性差；再则键合工作效率低。
另一种功率半导体模块结构，首先将半导体芯片焊接到覆铜陶瓷基板上，再通过铝丝将半导体芯片的发射极、栅极与覆铜陶瓷基板上规定的位置互连而完成铝丝键合工艺，将带半导体芯片的覆铜陶瓷基板焊接到铜底板上，再将铜电极端子焊接到已固定有覆铜陶瓷基板和半导体芯片的铜底板上，最后将带有电极的铜板上装外壳并进行注胶密封。这种结构电极焊接工艺需要很多的定位夹具，因此存在着工艺复杂和热应力问题，而影响长期使用可靠性。
发明内容
本实用新型的目的是提供一种结构合理，电极连接可靠，制造成本低的多单元功率半导体模块。
本实用新型为达到上述目的的技术方案是：一种多单元功率半导体模块，包括外壳、覆铜陶瓷基板、半导体芯片和电极，半导体芯片固定在覆铜陶瓷基板上，电极与覆铜陶瓷基板或/和半导体芯片连接，其特征在于：所述电极安装或固定在外壳的电极插槽内，电极的连接部位具有铝层，电极上的铝层通过铝丝与覆铜陶瓷基板或/和半导体芯片连接。
其中：所述电极连接部位的铝层厚度在10um～40um。
本实用新型在电极的连接部位设有铝层，因此电极能通过铝层与铝丝键合，电极在铝丝键合工艺过程中不会出现氧化现象，使电极能与铝丝牢固键合，故能大大提高电极键合丝的拉力和剪切力，由于铝丝与电极的铝层为欧姆接触，电极的通流能力与机械振动部符合设计要求，提高了半导体模块长期运行可靠性。本实用新型的电极通过铝丝与覆铜陶瓷基板或/和半导体芯片连接，不仅能简化键合工艺，提高半导体模块的成品率，同时也解决电极与覆铜陶瓷基板存在的热应力问题。
附图说明
下面结合附图对本实用新型的实施例作进一步的描述。
图1是本实用新型的一种结构示意图。
图2是图1俯视结构示意图。
图3是本实用新型另一种结构示意图。
图4是图3的俯视结构示意图。
图5是本实用新型电极的结构示意图。
图6是图5的侧视结构示意图。
其中：1-外壳，1-1-电极插槽，2-铜底板，3-电极，3-1-铝层，4-铝丝，5-覆铜陶瓷基板，6-半导体芯片。
具体实施方式
见图1～6所示，本实用新型的多单元功率半导体模块，包括外壳1、覆铜陶瓷基板5、半导体芯片6和电极3，覆铜陶瓷基板5可直接固定在外壳1底部，或覆铜陶瓷基板5焊接在铜底板2上，半导体芯片6焊接在覆铜陶瓷基板5上，并通过铝丝4键合完成半导体芯片6极性与覆铜陶瓷基板5上有图形的铜箔进行互连，电极3与覆铜陶瓷基板5或/和半导体芯片6连接。见图1、2所示，本实用新型的外壳1设有电极插槽1-1，电极3安装在电极插槽1-1内，故能根据不同的电路拓扑，将电极3插入位置不同电极插槽1-1内。或见图3、4所示，本实用新型的外壳1设有电极插槽1-1，但电极3固定在电极插槽1-1内，见图5、6所示，本实用新型在电极3的连接部位具有铝层3-1，电极3连接部位的铝层3-1厚度在10um～40um，如20um或30um，该电极3连接部位如图5、6所示设置在电极的上部整个表层，或该电极3连接部位仅为表层的一部分，电极3上的铝层3-1通过铝丝4与覆铜陶瓷基板5或/和半导体芯片6连接，通过电极3上的铝层3-1与铝丝4牢固键合，大大提高电极键合丝的拉力和剪切力以及通流能力。

Claims (2)

1.一种多单元功率半导体模块，包括外壳(1)、覆铜陶瓷基板(5)、半导体芯片(6)和电极(3)，半导体芯片(6)固定在覆铜陶瓷基板(5)上，电极(3)与覆铜陶瓷基板(5)或/和半导体芯片(6)连接，其特征在于：所述电极(3)安装或固定在外壳(1)的电极插槽(1-1)内，电极(3)的连接部位具有铝层，电极(3)上的铝层(3-1)通过铝丝(4)与覆铜陶瓷基板(5)或/和半导体芯片(6)连接。
2.根据权利要求1所述的一种多单元功率半导体模块，其特征在于：所述电极(3)连接部位的铝层(3-1)厚度在10um～40um。
CN2010202666103U 2010-07-22 2010-07-22 多单元功率半导体模块 Expired - Fee Related CN201741685U (zh)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104701268A (zh) * 2013-12-10 2015-06-10 江苏宏微科技股份有限公司 智能功率模块
CN105047639A (zh) * 2015-08-26 2015-11-11 扬州虹扬科技发展有限公司 一种功率半导体模块引线端子的加工方法
CN105633036A (zh) * 2015-12-30 2016-06-01 中国电子科技集团公司第十八研究所 空间电源用的高压大功率半导体元器件结构
CN106531693A (zh) * 2015-09-15 2017-03-22 富士电机株式会社 半导体装置
CN113658875A (zh) * 2021-08-18 2021-11-16 深圳市振华微电子有限公司 一种中小功率混合集成电路的组装方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104701268A (zh) * 2013-12-10 2015-06-10 江苏宏微科技股份有限公司 智能功率模块
CN104701268B (zh) * 2013-12-10 2017-06-16 江苏宏微科技股份有限公司 智能功率模块
CN105047639A (zh) * 2015-08-26 2015-11-11 扬州虹扬科技发展有限公司 一种功率半导体模块引线端子的加工方法
CN105047639B (zh) * 2015-08-26 2017-12-01 扬州虹扬科技发展有限公司 一种功率半导体模块引线端子的加工方法
CN106531693A (zh) * 2015-09-15 2017-03-22 富士电机株式会社 半导体装置
CN106531693B (zh) * 2015-09-15 2021-06-11 富士电机株式会社 半导体装置
CN105633036A (zh) * 2015-12-30 2016-06-01 中国电子科技集团公司第十八研究所 空间电源用的高压大功率半导体元器件结构
CN113658875A (zh) * 2021-08-18 2021-11-16 深圳市振华微电子有限公司 一种中小功率混合集成电路的组装方法
CN113658875B (zh) * 2021-08-18 2022-06-21 深圳市振华微电子有限公司 一种中小功率混合集成电路的组装方法

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