CN104576567A - 包括电子器件的集成电路芯片以及电子系统 - Google Patents
包括电子器件的集成电路芯片以及电子系统 Download PDFInfo
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Abstract
一种电子器件,包括衬底晶片,该衬底晶片由许多绝缘材料层制成并且包括电连接网络。集成电路芯片被安装至衬底晶片的顶侧。衬底晶片还包括金属板,该金属板被集成到衬底晶片中并且热耦合至集成电路芯片。金属板可以具有超过衬底晶片的若干层的厚度。金属板可以包括导热流体通过其流动的导管。
Description
优先权要求
本申请要求于2013年10月15日提交的第1360007号法国专利申请的优先权,其公开内容通过引用并入本文。
技术领域
本申请涉及微电子领域。
背景技术
制作包括一个堆叠在另一个上面并且电连接在一起的电子器件的电子系统是已知的,该电子器件分别包括至少一个集成电路芯片。
堆叠的电子器件尤其具有改进电连接的性能以及减小覆盖面积的优点。然而,在特定情况下,集成电路芯片可以产生热,并且所产生的热可以使其它集成电路芯片变热,并且因此使其它集成电路芯片的性能退化。这尤其是当第一电子器件包括处理器芯片并且堆叠在第一电子器件上的第二电子器件包括存储器芯片时的情况,该处理器芯片产生热,该存储器芯片的操作在其温度增加时尤其退化。
上述情况成为提高所述电子系统的性能的障碍,诸如尤其是其运行程序的速度。然而,当前在所述电子系统所需的性能和它们的覆盖面积之间进行折中的情况并不令人满意,尤其是在手持设备(诸如移动电话)领域。
发明内容
根据一个实施例,提供了一种电子器件,其包括由绝缘材料制成的衬底晶片,该晶片配备有电连接网络并且在一侧支撑至少一个集成电路芯片,并且该器件包括被集成到所述衬底晶片中的至少一个金属板。
多个中介金属元件和多个外部金属元件可以被放置在衬底晶片的任一侧。
所述中介金属元件可以包括第一中介金属元件和第二中介金属元件,第一中介金属元件连接所述芯片与所述电连接网络,第二中介金属元件将所述芯片连接至所述金属板。
所述外部金属元件可以包括第一外部金属元件和第二外部金属元件,第一外部金属元件连接至所述电连接网络,第二外部金属元件连接至所述金属板。
所述金属板可以位于所述电连接网络的中介金属层之间。
所述金属板可以通过金属过孔连接至所述第二中介金属元件。
所述金属板可以通过金属过孔连接至所述第二外部金属元件。
所述金属板可以包括突出部,所述第二中介金属元件被放置在该突出部上。
所述金属板可以包括突出部,所述第二外部金属元件被放置在该突出部上。
所述金属板可以包含填充有导热材料的至少一个内部导管。
所述衬底晶片可以包含连接至所述金属板的所述内部导管并且连接至用于形成流体流动的装置的导管。
也提供了一种电子系统,其包括所述电子器件,并且其包括另一电子器件,该另一电子器件被放置在所述电子器件上并且包括另一衬底晶片,该另一衬底晶片配备有连接至所述电连接网络的另一电连接网络并且支撑连接至该另一电连接网络的至少一个其它集成电路芯片。
所述系统可以包括印刷电路板,该印刷电路板借由外部金属元件来支撑所述电子器件。
附图说明
现在将借由非限制性示例来描述根据本发明的特定实施例的电子器件和电子系统,这些器件和系统由附图图示出,在附图中:
图1示出了电子器件的截面;
图2示出了包括图1中的电子器件的电子系统的截面;
图3示出了图1中的电子器件的变型实施例;以及
图4示出了图1中的电子器件的另一变型实施例。
具体实施方式
如图1中所示,电子器件1包括:衬底晶片2,衬底晶片2配备有集成的金属电连接网络3,金属电连接网络3将一侧连接至另一侧;被放置在衬底晶片2一侧的集成电路芯片4;多个中介金属电连接元件5,诸如柱;以及多个外部金属电连接元件6,诸如凸块,被放置在衬底晶片2的任一侧上。
在所示的示例中,集成的电连接网络3从衬底晶片的顶部起包括平行于衬底晶片2的侧部的六个分离的金属层M1、M2、M3、M4、M5和M6,这些层分别包括由层间金属电连接过孔选择性地连接的金属焊盘。
此外,电子器件1包括至少一个金属板7,至少一个金属板7被集成或并入到衬底晶片2中并且与金属电连接网络3分离。
在所示的示例中,金属板7的厚度使得其占据在中介金属层M2和M5之间包括的厚度。
多个中介金属元件5包括第一中介金属元件5a,第一中介金属元件5a连接芯片4与电连接网络3并且被插入在芯片4的金属焊盘与这一电连接网络3的金属层M1的金属焊盘8a之间。
多个中介金属元件5也包括第二中介金属元件5b,第二中介金属元件5b被插入在芯片4与电连接网络3的金属层M1的金属焊盘8b之间。
在金属层M2中,金属焊盘9b被布置在金属板7的对应侧7a上。
金属过孔10b被布置在金属层M1的金属焊盘8b与金属层M2的金属焊盘9b之间。
多个外部金属元件6包括第一外部金属元件6a,第一外部金属元件6a被放置在电连接网络3的金属层M6的金属焊盘11a上。
多个外部金属元件6还包括第二外部金属元件6b,第二外部金属元件6b被放置在电连接网络3的金属层M6的金属焊盘11b上。
在金属层M5中,金属焊盘12b被布置在金属板7的对应侧7b上。
金属过孔13b被布置在金属焊盘12b与金属层M6的金属焊盘11b之间。
根据一个实施例,集成电路芯片4(其可以是处理器芯片)可以生成热。该热中的至少一些可以优选地借由第二中介金属元件5b、金属焊盘8b、金属过孔10b和金属焊盘9b被传送至金属板7,金属板7被集成到衬底晶片2中。
因此,被集成的或并入的金属板7,由于其相对大的体积而用作热沉或热泵,并且形成热传送装置,以这样的方式芯片4被冷却。
因此,该热中的至少一些可以被传送至第二外部金属元件6b。
可以选择用来优选地疏散热的电连接元件5b,使得它们位于芯片4的产生最多热的局部区域中。
由芯片4产生的一些热也可以借由电连接元件5a被传送至电连接网络3,随后被传送至电连接元件6a。
此外,位于芯片4的外围的辅助金属焊盘8c被布置在金属层M1中,并且在其上放置辅助金属元件14。
电子器件1还可以包括包封层15,包封层15设置在衬底晶片2上并且在芯片4周围,该层15包含其中放置辅助金属电连接元件14(诸如金属凸块)的孔16。
如图2中所示,电子系统100可以包括图1中的电子器件1以及与芯片4在同一例上堆叠在电子器件1上的另一电子器件101。
根据一个示例实施例,电子器件101包括衬底晶片102,衬底晶片102配备有电连接网络103,电连接网络103将一侧连接至另一侧,并且衬底晶片102还支撑键合至与电子器件1相对的那一侧的集成电路芯片104。
芯片104通过金属接线105连接至电连接网络103。
芯片104和电连接接线105被嵌入在设置在衬底晶片102的对应侧上的包封材料106中。
电子器件101借由电连接元件107(诸如金属凸块)被安装在电子器件1上,该元件107被插入在所述器件之间,并且电地以及选择性地将电子器件101的电连接网络103连接至电子器件1的电连接网络3,电连接网络3被焊接至被放置在焊盘8c上的电连接元件14。
此外,电子器件1以及因此电子系统100借由被焊接至该板108的金属焊盘109的电连接元件6被安装在印刷电路板108上。
在上文中借由示例所描述的布置具有以下优点。
可以是存储器芯片的芯片104远离芯片4设置,并且通过衬底晶片102以及通过分离电子器件1和电子器件101的空间而与芯片4远离设置。
如上所述,由芯片4产生并且被传送至连接元件6a并且优选地被传送至电连接元件6b的热扩散到印刷电路板108中。
由芯片4产生的热也扩散到分离电子器件1与电子器件101的空间中,以便朝着外界疏散。
从之前描述可以得到:金属板7形成用于捕获至少一些由芯片4产生的热的装置以及用于将热从芯片104传送掉的装置。
因此,由芯片4产生的热朝着芯片104的扩散以如下方式被限制,在该方式中芯片104被保护以免其温度的任何过度增加。
此外,由于连接至芯片4的金属元件5b被连接至金属元件6b,尤其是借由金属板,所以这一连接可以用于电学目的,例如为了形成去往电接地的连接。
根据电子器件1的一个变型实施例,该变型被图示在图3中,金属层M1的金属焊盘8b、金属层M2的金属焊盘9b以及将它们连接在一起的金属过孔10b可以至少部分地由金属板7中的相对于其侧部7a突出的突出部17替换,电连接元件5b与所述突出部17形成接触。
同样地,金属层M6的金属焊盘11b、金属层M5的金属焊盘12b以及将它们连接在一起的金属过孔13b可以至少部分地由金属板7中的相对于其侧部7b突出的突出部18替换,电连接元件6b与所述突出部18形成接触。
根据电子器件1的一个变型实施例,该变型被图示在图4中,金属板7由被集成在电连接网络3的中介金属层M3和M4之间的金属板19替换。
在金属层M3中,金属焊盘20b被布置在金属板19的一侧19a上,该焊盘20b通过金属过孔21b被连接至金属层M2的金属焊盘9b。
同样,在金属层M4中,金属焊盘22b被布置在金属板19的一侧19b上,该焊盘22b通过金属过孔21b被连接至金属层M5的金属焊盘12b。
根据一个变型实施例,金属板19可以包含内部导管24,内部导管24可以填充有导热或热传送流体,诸如在全氟三丁胺的名称或商标下售卖的FC电子流体之一或烯烃。
根据一个变型实施例,内部导管24可以被连接至导管25(例如供应/返回导管),导管25例如被布置在衬底晶片2的分离金属层M3和M4的层中,这些导管25横向地从衬底晶片2露出并且可能连接至适合于形成通过导管24的冷却流体流动的外部装置。
根据另一变型实施例,电子器件1可以配备有并入微泵的部件,该部件可以被固定至器件的一侧,例如通过键合,这一微泵通过合适的通道连接至内部导管25,以便进行热传送或冷却通过金属板的内部导管24的流体流动。
因此,由芯片4产生的热的疏散可以进一步改进。
金属板7和19可以在与芯片4的产生热的小区域近似对应的区域之上延伸,或者在与芯片的总区域近似对应的更大区域之上延伸,或者在相对于芯片4横向突出的区域之上延伸。
本发明并不限于如上所述的示例。特别地,器件101的结构可以不同。金属板可以位于其它金属层之间。可以提供超过一个金属板。可以提供包括被集成到衬底中的金属板的其它热捕获、热传送和冷却装置。许多其它变型实施例在不背离本发明的范围的情况下是可能的。
Claims (19)
1.一种电子器件,包括:
衬底晶片,由绝缘材料制成并且包括电连接网络;
至少一个集成电路芯片,被安装在所述衬底晶片的一侧;以及
至少一个金属板,被集成到所述衬底晶片中。
2.根据权利要求1所述的电子器件,还包括:
多个中介金属元件,被配置用于将所述集成电路芯片安装到所述衬底晶片;
多个外部金属元件,被安装在所述衬底晶片的相对侧;
其中所述中介金属元件包括:第一中介金属元件,将所述集成电路芯片连接至所述电连接网络;以及第二中介金属元件,将所述集成电路芯片连接至所述金属板;以及
其中所述外部金属元件包括连接至所述电连接网络的第一金属元件和连接至所述金属板的第二外部金属元件。
3.根据权利要求1所述的电子器件,其中所述金属板被定位在所述电连接网络的中介金属层之间。
4.根据权利要求2所述的电子器件,其中所述金属板通过金属过孔连接至所述第二中介金属元件。
5.根据权利要求2所述的电子器件,其中所述金属板通过金属过孔连接至所述第二外部金属元件。
6.根据权利要求2所述的电子器件,其中所述金属板包括突出部,所述第二中介金属元件被放置在所述突出部上。
7.根据权利要求2所述的电子器件,其中所述金属板包括突出部,所述第二外部金属元件被放置在所述突出部上。
8.根据权利要求1所述的电子器件,其中所述金属板包含填充有导热材料的至少一个内部导管。
9.根据权利要求8所述的电子器件,其中所述衬底晶片包含连接至所述金属板的所述内部导管的导管,所述导管被配置用于连接至外部装置以用于形成通过所述导管和所述内部导管的流体流动。
10.根据权利要求1所述的电子器件,其中所述衬底晶片包括多个层并且其中所述金属板具有比多个所述层更厚的厚度。
11.根据权利要求1所述的电子器件,还包括另一衬底晶片,所述另一衬底晶片具有另一电连接网络,所述另一电连接网络连接至所述电连接网络并且包括连接至所述另一电连接网络的至少一个其它集成电路芯片。
12.根据权利要求11所述的电子器件,还包括印刷电路板,所述衬底晶片使用外部金属元件被安装到所述印刷电路板。
13.一种电子器件,包括:
集成电路芯片,具有第一接触;
衬底晶片,由多个层制成并且具有顶表面和底表面,所述顶表面具有顶部接触焊盘,所述底表面具有底部接触焊盘;
其中所述集成电路芯片被安装至所述衬底晶片,其中所述第一接触连接至所述顶部接触焊盘;以及
所述衬底晶片还包括金属板,所述金属板被嵌入在所述衬底晶片内并且厚度大于多个所述层的厚度;
其中所述金属板热连接至所述集成电路芯片。
14.根据权利要求13所述的电子器件,其中所嵌入的金属板的厚度至少等于衬底晶片的厚度。
15.根据权利要求14所述的电子器件,其中所嵌入的金属板还包括突出部,所述突出部延伸通过所述衬底晶片的层以到达所述衬底晶片的所述顶表面。
16.根据权利要求14所述的电子器件,其中所嵌入的金属板还包括突出部,所述突出部延伸通过所述衬底晶片的层以到达所述衬底晶片的所述底表面。
17.一种电子器件,包括:
集成电路芯片,具有第一接触;
衬底晶片,由多个层制成并且具有顶表面和底表面,所述顶表面具有顶部接触焊盘,所述底表面具有底部接触焊盘;
其中所述集成电路芯片被安装至所述衬底晶片,其中所述第一接触连接至所述顶部接触焊盘;以及
所述衬底晶片还包括金属板,所述金属板被嵌入在所述衬底晶片内;
所述金属板包括填充有导热材料的内部导管;
其中所述金属板热连接至所述集成电路芯片。
18.根据权利要求17所述的电子器件,其中所述衬底晶片还包括延伸通过所述衬底晶片并且与所述金属板的所述内部导管流体连通的导管。
19.根据权利要求18所述的电子器件,其中延伸通过所述衬底晶片的所述导管被配置用于连接至外部装置以用于形成通过所述导管和所述内部导管的导热流体流动。
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CN111244053A (zh) * | 2018-11-28 | 2020-06-05 | 美光科技公司 | 用于连接微电子装置的中介层 |
CN113838820A (zh) * | 2020-06-24 | 2021-12-24 | 美光科技公司 | 通过微通道集成衬底对gpu-hbm封装进行热管理 |
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JP6450181B2 (ja) * | 2014-12-18 | 2019-01-09 | 株式会社ジェイデバイス | 半導体装置 |
US10163751B2 (en) * | 2016-11-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat transfer structures and methods for IC packages |
EP3716321A1 (en) * | 2019-03-29 | 2020-09-30 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded semiconductor component and embedded highly conductive block which are mutually coupled |
CN116845038B (zh) * | 2023-08-29 | 2023-12-22 | 之江实验室 | 一种针对晶圆级处理器的散热装置及其制备方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357056A (en) * | 1992-03-23 | 1994-10-18 | Nec Corporation | Chip carrier for optical device |
US5786238A (en) * | 1997-02-13 | 1998-07-28 | Generyal Dynamics Information Systems, Inc. | Laminated multilayer substrates |
US6477034B1 (en) * | 2001-10-03 | 2002-11-05 | Intel Corporation | Interposer substrate with low inductance capacitive paths |
US20020185718A1 (en) * | 2001-03-13 | 2002-12-12 | Kazuyuki Mikubo | Semiconductor device packaging structure |
US6661084B1 (en) * | 2000-05-16 | 2003-12-09 | Sandia Corporation | Single level microelectronic device package with an integral window |
CN204230225U (zh) * | 2013-10-15 | 2015-03-25 | 意法半导体(格勒诺布尔2)公司 | 电子器件 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6097089A (en) * | 1998-01-28 | 2000-08-01 | Mitsubishi Gas Chemical Company, Inc. | Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package |
US6046499A (en) * | 1996-03-27 | 2000-04-04 | Kabushiki Kaisha Toshiba | Heat transfer configuration for a semiconductor device |
JP2008166440A (ja) * | 2006-12-27 | 2008-07-17 | Spansion Llc | 半導体装置 |
US8987602B2 (en) * | 2012-06-14 | 2015-03-24 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Multilayer electronic support structure with cofabricated metal core |
-
2013
- 2013-10-15 FR FR1360007A patent/FR3011979A1/fr not_active Withdrawn
-
2014
- 2014-09-22 CN CN201410486719.0A patent/CN104576567B/zh active Active
- 2014-09-22 CN CN201420546010.0U patent/CN204230225U/zh not_active Expired - Lifetime
- 2014-10-10 US US14/511,920 patent/US9349671B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357056A (en) * | 1992-03-23 | 1994-10-18 | Nec Corporation | Chip carrier for optical device |
US5786238A (en) * | 1997-02-13 | 1998-07-28 | Generyal Dynamics Information Systems, Inc. | Laminated multilayer substrates |
US6661084B1 (en) * | 2000-05-16 | 2003-12-09 | Sandia Corporation | Single level microelectronic device package with an integral window |
US20020185718A1 (en) * | 2001-03-13 | 2002-12-12 | Kazuyuki Mikubo | Semiconductor device packaging structure |
US6477034B1 (en) * | 2001-10-03 | 2002-11-05 | Intel Corporation | Interposer substrate with low inductance capacitive paths |
CN204230225U (zh) * | 2013-10-15 | 2015-03-25 | 意法半导体(格勒诺布尔2)公司 | 电子器件 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111244053A (zh) * | 2018-11-28 | 2020-06-05 | 美光科技公司 | 用于连接微电子装置的中介层 |
US11824010B2 (en) | 2018-11-28 | 2023-11-21 | Micron Technology, Inc. | Interposers for microelectronic devices |
CN113838820A (zh) * | 2020-06-24 | 2021-12-24 | 美光科技公司 | 通过微通道集成衬底对gpu-hbm封装进行热管理 |
US11915997B2 (en) | 2020-06-24 | 2024-02-27 | Micron Technology, Inc. | Thermal management of GPU-HBM package by microchannel integrated substrate |
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