CN104471708B - 具有多个插入件的堆叠裸片组件 - Google Patents

具有多个插入件的堆叠裸片组件 Download PDF

Info

Publication number
CN104471708B
CN104471708B CN201280069303.8A CN201280069303A CN104471708B CN 104471708 B CN104471708 B CN 104471708B CN 201280069303 A CN201280069303 A CN 201280069303A CN 104471708 B CN104471708 B CN 104471708B
Authority
CN
China
Prior art keywords
insert
die
integrated circuit
interposer
circuit die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280069303.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN104471708A (zh
Inventor
艾弗伦·C·吴
巴哈瑞·巴尼杰马利
拉乌那丹·沙威尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/369,215 external-priority patent/US8704364B2/en
Priority claimed from US13/399,939 external-priority patent/US8704384B2/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of CN104471708A publication Critical patent/CN104471708A/zh
Application granted granted Critical
Publication of CN104471708B publication Critical patent/CN104471708B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201280069303.8A 2012-02-08 2012-12-03 具有多个插入件的堆叠裸片组件 Active CN104471708B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13/369,215 2012-02-08
US13/369,215 US8704364B2 (en) 2012-02-08 2012-02-08 Reducing stress in multi-die integrated circuit structures
US13/399,939 2012-02-17
US13/399,939 US8704384B2 (en) 2012-02-17 2012-02-17 Stacked die assembly
PCT/US2012/067543 WO2013119309A1 (en) 2012-02-08 2012-12-03 Stacked die assembly with multiple interposers

Publications (2)

Publication Number Publication Date
CN104471708A CN104471708A (zh) 2015-03-25
CN104471708B true CN104471708B (zh) 2017-05-24

Family

ID=47563594

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280069303.8A Active CN104471708B (zh) 2012-02-08 2012-12-03 具有多个插入件的堆叠裸片组件

Country Status (5)

Country Link
EP (1) EP2812919B1 (https=)
JP (1) JP5916898B2 (https=)
KR (1) KR101891862B1 (https=)
CN (1) CN104471708B (https=)
WO (1) WO2013119309A1 (https=)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140138815A1 (en) * 2012-11-20 2014-05-22 Nvidia Corporation Server processing module
US20150221614A1 (en) * 2014-02-06 2015-08-06 Sehat Sutardja High-bandwidth dram using interposer and stacking
US20150279431A1 (en) 2014-04-01 2015-10-01 Micron Technology, Inc. Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
US9402312B2 (en) 2014-05-12 2016-07-26 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
WO2017136289A2 (en) * 2016-02-02 2017-08-10 Xilinx, Inc. Active-by-active programmable device
TWI628742B (zh) * 2016-07-21 2018-07-01 南亞科技股份有限公司 堆疊式封裝結構
WO2018034787A1 (en) * 2016-08-15 2018-02-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (ssi) technology integration
US10784121B2 (en) 2016-08-15 2020-09-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (SSI) technology integration
US10141938B2 (en) * 2016-09-21 2018-11-27 Xilinx, Inc. Stacked columnar integrated circuits
US11183458B2 (en) 2016-11-30 2021-11-23 Shenzhen Xiuyuan Electronic Technology Co., Ltd Integrated circuit packaging structure and method
US12341096B2 (en) 2016-12-29 2025-06-24 Intel Corporation Bare-die smart bridge connected with copper pillars for system-in-package apparatus
KR102653238B1 (ko) * 2016-12-29 2024-03-29 인텔 코포레이션 시스템 인 패키지 장치를 위해 구리 필러와 연결된 베어 다이 스마트 브리지
US12424531B2 (en) 2017-03-14 2025-09-23 Mediatek Inc. Semiconductor package structure
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
CN116884452A (zh) * 2017-06-02 2023-10-13 超极存储器股份有限公司 运算处理装置
US10497689B2 (en) * 2017-08-04 2019-12-03 Mediatek Inc. Semiconductor package assembly and method for forming the same
KR102498883B1 (ko) * 2018-01-31 2023-02-13 삼성전자주식회사 전류를 분산시키는 관통 전극들을 포함하는 반도체 장치
US11652060B2 (en) 2018-12-28 2023-05-16 Intel Corporation Die interconnection scheme for providing a high yielding process for high performance microprocessors
CN118448360A (zh) * 2019-03-14 2024-08-06 联发科技股份有限公司 半导体封装结构
KR102679095B1 (ko) * 2019-05-30 2024-07-01 삼성전자주식회사 반도체 패키지
US11735533B2 (en) 2019-06-11 2023-08-22 Intel Corporation Heterogeneous nested interposer package for IC chips
US12080643B2 (en) * 2019-09-26 2024-09-03 Intel Corporation Integrated circuit structures having differentiated interconnect lines in a same dielectric layer
DE102021104688A1 (de) 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Stromverteilungsstruktur und verfahren
US12255148B2 (en) * 2020-04-30 2025-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Power distribution structure and method
CN111863780A (zh) * 2020-07-17 2020-10-30 北京灵汐科技有限公司 封装结构及电子设备
KR20220022242A (ko) 2020-08-18 2022-02-25 삼성전자주식회사 회로 기판 모듈 및 이를 포함하는 전자 장치
JP7795724B2 (ja) * 2021-02-05 2026-01-08 大日本印刷株式会社 半導体パッケージ及び半導体パッケージの製造方法並びにインターポーザ群
US11862481B2 (en) 2021-03-09 2024-01-02 Apple Inc. Seal ring designs supporting efficient die to die routing
US20220320042A1 (en) * 2021-03-30 2022-10-06 Advanced Micro Devices, Inc. Die stacking for modular parallel processors
CN114242669B (zh) * 2022-02-28 2022-07-08 甬矽电子(宁波)股份有限公司 堆叠封装结构和堆叠结构封装方法
EP4487327A1 (en) * 2022-03-01 2025-01-08 Graphcore Limited Dram module with data routing logic
US12543594B2 (en) * 2022-04-29 2026-02-03 Intel Corporation Scalable package architecture using reticle stitching and photonics for integrated circuits
CN114899185B (zh) * 2022-07-12 2022-12-02 之江实验室 一种适用于晶圆级异质异构芯粒的集成结构和集成方法
CN116775555B (zh) * 2023-06-27 2025-03-18 无锡中微亿芯有限公司 一种具有高存储带宽的多裸片存算架构fpga

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1388584A (zh) * 2001-05-25 2003-01-01 日本电气株式会社 半导体器件
CN101295693A (zh) * 2007-04-24 2008-10-29 恩益禧电子股份有限公司 半导体器件
CN101877341A (zh) * 2009-04-29 2010-11-03 国际商业机器公司 可返修的电子器件组件及方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US5672546A (en) * 1995-12-04 1997-09-30 General Electric Company Semiconductor interconnect method and structure for high temperature applications
WO2002082540A1 (en) * 2001-03-30 2002-10-17 Fujitsu Limited Semiconductor device, method of manufacture thereof, and semiconductor substrate
JP4380130B2 (ja) * 2002-09-13 2009-12-09 ソニー株式会社 半導体装置
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP4343044B2 (ja) * 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
JP2009135397A (ja) * 2007-10-31 2009-06-18 Panasonic Corp 半導体装置
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US8008764B2 (en) * 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
JPWO2011030504A1 (ja) * 2009-09-11 2013-02-04 パナソニック株式会社 電子部品実装体及びその製造方法並びにインタポーザ
JP4649531B1 (ja) * 2009-12-08 2011-03-09 新光電気工業株式会社 電子装置の切断方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1388584A (zh) * 2001-05-25 2003-01-01 日本电气株式会社 半导体器件
CN101295693A (zh) * 2007-04-24 2008-10-29 恩益禧电子股份有限公司 半导体器件
CN101877341A (zh) * 2009-04-29 2010-11-03 国际商业机器公司 可返修的电子器件组件及方法

Also Published As

Publication number Publication date
EP2812919B1 (en) 2021-07-07
WO2013119309A1 (en) 2013-08-15
EP2812919A1 (en) 2014-12-17
JP2015507372A (ja) 2015-03-05
JP5916898B2 (ja) 2016-05-11
CN104471708A (zh) 2015-03-25
KR101891862B1 (ko) 2018-08-24
KR20140111716A (ko) 2014-09-19

Similar Documents

Publication Publication Date Title
CN104471708B (zh) 具有多个插入件的堆叠裸片组件
US8704384B2 (en) Stacked die assembly
JP7523352B2 (ja) 抵抗低減型アクティブオンアクティブのダイ積層向けの電力分配
US10784121B2 (en) Standalone interface for stacked silicon interconnect (SSI) technology integration
US8704364B2 (en) Reducing stress in multi-die integrated circuit structures
EP3472861B1 (en) Heterogeneous ball pattern package
CN104350595B (zh) 克服分划板区域限制的大型硅中介板
TW202549125A (zh) 依據矽穿孔交互連接線垂直連接器建構之3d晶片封裝結構
CN104603942B (zh) 使用于多裸晶集成电路的有弹性尺寸的裸晶
KR101645507B1 (ko) 반도체 패키지 내의 다이간 간격을 감소시키는 언더필 물질 플로우 제어
KR101073709B1 (ko) 장치, 칩 및 집적 회로 패키지
US9087765B2 (en) System-in-package with interposer pitch adapter
KR102847254B1 (ko) 시스템 인 패키지, 방법 및 컴퓨터 판독가능 저장 매체
EP3373332A1 (en) Embedded multi-die interconnect bridge with improved power delivery
CN116057699A (zh) 使用混合扇出的混合密度互连架构
US9911465B1 (en) High bandwidth memory (HBM) bandwidth aggregation switch
TWI501192B (zh) 位於圖形處理單元〈ＧＰＵs〉上之動態隨機存取記憶體〈ＤＲＡＭs〉的替代立體〈３Ｄ〉堆疊架構
TW201830607A (zh) 半導體晶片封裝
TWI540653B (zh) 關於包含多記憶體晶粒之半導體封裝之方法及配置
US12237240B2 (en) Semiconductor package and method of manufacturing semiconductor package
US10756019B1 (en) Systems providing interposer structures
TW202336981A (zh) 包括中介層的半導體封裝
US9337170B1 (en) Contact arrangements for stackable microelectronic package structures
US12525578B2 (en) Thermally-aware semiconductor packages
US20230223350A1 (en) Semiconductor package and method of fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant