KR101891862B1 - 다수의 인터포저를 갖는 적층형 다이 조립체 - Google Patents

다수의 인터포저를 갖는 적층형 다이 조립체 Download PDF

Info

Publication number
KR101891862B1
KR101891862B1 KR1020147025005A KR20147025005A KR101891862B1 KR 101891862 B1 KR101891862 B1 KR 101891862B1 KR 1020147025005 A KR1020147025005 A KR 1020147025005A KR 20147025005 A KR20147025005 A KR 20147025005A KR 101891862 B1 KR101891862 B1 KR 101891862B1
Authority
KR
South Korea
Prior art keywords
interposer
die
integrated circuit
circuit die
interposers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020147025005A
Other languages
English (en)
Korean (ko)
Other versions
KR20140111716A (ko
Inventor
에프렘 씨 우
바하레 바니자말리
라구난단 차와레
Original Assignee
자일링크스 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/369,215 external-priority patent/US8704364B2/en
Priority claimed from US13/399,939 external-priority patent/US8704384B2/en
Application filed by 자일링크스 인코포레이티드 filed Critical 자일링크스 인코포레이티드
Publication of KR20140111716A publication Critical patent/KR20140111716A/ko
Application granted granted Critical
Publication of KR101891862B1 publication Critical patent/KR101891862B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020147025005A 2012-02-08 2012-12-03 다수의 인터포저를 갖는 적층형 다이 조립체 Active KR101891862B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13/369,215 2012-02-08
US13/369,215 US8704364B2 (en) 2012-02-08 2012-02-08 Reducing stress in multi-die integrated circuit structures
US13/399,939 2012-02-17
US13/399,939 US8704384B2 (en) 2012-02-17 2012-02-17 Stacked die assembly
PCT/US2012/067543 WO2013119309A1 (en) 2012-02-08 2012-12-03 Stacked die assembly with multiple interposers

Publications (2)

Publication Number Publication Date
KR20140111716A KR20140111716A (ko) 2014-09-19
KR101891862B1 true KR101891862B1 (ko) 2018-08-24

Family

ID=47563594

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147025005A Active KR101891862B1 (ko) 2012-02-08 2012-12-03 다수의 인터포저를 갖는 적층형 다이 조립체

Country Status (5)

Country Link
EP (1) EP2812919B1 (https=)
JP (1) JP5916898B2 (https=)
KR (1) KR101891862B1 (https=)
CN (1) CN104471708B (https=)
WO (1) WO2013119309A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023212453A1 (en) * 2022-04-29 2023-11-02 Intel Corporation Scalable package architecture using reticle stitching and photonics for zetta-scale integrated circuits

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140138815A1 (en) * 2012-11-20 2014-05-22 Nvidia Corporation Server processing module
US20150221614A1 (en) * 2014-02-06 2015-08-06 Sehat Sutardja High-bandwidth dram using interposer and stacking
US20150279431A1 (en) 2014-04-01 2015-10-01 Micron Technology, Inc. Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
US9402312B2 (en) 2014-05-12 2016-07-26 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
WO2017136289A2 (en) * 2016-02-02 2017-08-10 Xilinx, Inc. Active-by-active programmable device
TWI628742B (zh) * 2016-07-21 2018-07-01 南亞科技股份有限公司 堆疊式封裝結構
WO2018034787A1 (en) * 2016-08-15 2018-02-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (ssi) technology integration
US10784121B2 (en) 2016-08-15 2020-09-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (SSI) technology integration
US10141938B2 (en) * 2016-09-21 2018-11-27 Xilinx, Inc. Stacked columnar integrated circuits
US11183458B2 (en) 2016-11-30 2021-11-23 Shenzhen Xiuyuan Electronic Technology Co., Ltd Integrated circuit packaging structure and method
US12341096B2 (en) 2016-12-29 2025-06-24 Intel Corporation Bare-die smart bridge connected with copper pillars for system-in-package apparatus
KR102653238B1 (ko) * 2016-12-29 2024-03-29 인텔 코포레이션 시스템 인 패키지 장치를 위해 구리 필러와 연결된 베어 다이 스마트 브리지
US12424531B2 (en) 2017-03-14 2025-09-23 Mediatek Inc. Semiconductor package structure
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
CN116884452A (zh) * 2017-06-02 2023-10-13 超极存储器股份有限公司 运算处理装置
US10497689B2 (en) * 2017-08-04 2019-12-03 Mediatek Inc. Semiconductor package assembly and method for forming the same
KR102498883B1 (ko) * 2018-01-31 2023-02-13 삼성전자주식회사 전류를 분산시키는 관통 전극들을 포함하는 반도체 장치
US11652060B2 (en) 2018-12-28 2023-05-16 Intel Corporation Die interconnection scheme for providing a high yielding process for high performance microprocessors
CN118448360A (zh) * 2019-03-14 2024-08-06 联发科技股份有限公司 半导体封装结构
KR102679095B1 (ko) * 2019-05-30 2024-07-01 삼성전자주식회사 반도체 패키지
US11735533B2 (en) 2019-06-11 2023-08-22 Intel Corporation Heterogeneous nested interposer package for IC chips
US12080643B2 (en) * 2019-09-26 2024-09-03 Intel Corporation Integrated circuit structures having differentiated interconnect lines in a same dielectric layer
DE102021104688A1 (de) 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Stromverteilungsstruktur und verfahren
US12255148B2 (en) * 2020-04-30 2025-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Power distribution structure and method
CN111863780A (zh) * 2020-07-17 2020-10-30 北京灵汐科技有限公司 封装结构及电子设备
KR20220022242A (ko) 2020-08-18 2022-02-25 삼성전자주식회사 회로 기판 모듈 및 이를 포함하는 전자 장치
JP7795724B2 (ja) * 2021-02-05 2026-01-08 大日本印刷株式会社 半導体パッケージ及び半導体パッケージの製造方法並びにインターポーザ群
US11862481B2 (en) 2021-03-09 2024-01-02 Apple Inc. Seal ring designs supporting efficient die to die routing
US20220320042A1 (en) * 2021-03-30 2022-10-06 Advanced Micro Devices, Inc. Die stacking for modular parallel processors
CN114242669B (zh) * 2022-02-28 2022-07-08 甬矽电子(宁波)股份有限公司 堆叠封装结构和堆叠结构封装方法
EP4487327A1 (en) * 2022-03-01 2025-01-08 Graphcore Limited Dram module with data routing logic
CN114899185B (zh) * 2022-07-12 2022-12-02 之江实验室 一种适用于晶圆级异质异构芯粒的集成结构和集成方法
CN116775555B (zh) * 2023-06-27 2025-03-18 无锡中微亿芯有限公司 一种具有高存储带宽的多裸片存算架构fpga

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020175421A1 (en) * 2001-05-25 2002-11-28 Naoto Kimura Semiconductor device
JP2004327474A (ja) * 2003-04-21 2004-11-18 Elpida Memory Inc メモリモジュール及びメモリシステム
US20090267238A1 (en) * 2008-04-28 2009-10-29 Douglas James Joseph Bridges for interconnecting interposers in multi-chip integrated circuits

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US5672546A (en) * 1995-12-04 1997-09-30 General Electric Company Semiconductor interconnect method and structure for high temperature applications
WO2002082540A1 (en) * 2001-03-30 2002-10-17 Fujitsu Limited Semiconductor device, method of manufacture thereof, and semiconductor substrate
JP4380130B2 (ja) * 2002-09-13 2009-12-09 ソニー株式会社 半導体装置
JP4343044B2 (ja) * 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
JP2008294423A (ja) * 2007-04-24 2008-12-04 Nec Electronics Corp 半導体装置
JP2009135397A (ja) * 2007-10-31 2009-06-18 Panasonic Corp 半導体装置
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US7936060B2 (en) * 2009-04-29 2011-05-03 International Business Machines Corporation Reworkable electronic device assembly and method
JPWO2011030504A1 (ja) * 2009-09-11 2013-02-04 パナソニック株式会社 電子部品実装体及びその製造方法並びにインタポーザ
JP4649531B1 (ja) * 2009-12-08 2011-03-09 新光電気工業株式会社 電子装置の切断方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020175421A1 (en) * 2001-05-25 2002-11-28 Naoto Kimura Semiconductor device
JP2004327474A (ja) * 2003-04-21 2004-11-18 Elpida Memory Inc メモリモジュール及びメモリシステム
US20090267238A1 (en) * 2008-04-28 2009-10-29 Douglas James Joseph Bridges for interconnecting interposers in multi-chip integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023212453A1 (en) * 2022-04-29 2023-11-02 Intel Corporation Scalable package architecture using reticle stitching and photonics for zetta-scale integrated circuits

Also Published As

Publication number Publication date
EP2812919B1 (en) 2021-07-07
WO2013119309A1 (en) 2013-08-15
CN104471708B (zh) 2017-05-24
EP2812919A1 (en) 2014-12-17
JP2015507372A (ja) 2015-03-05
JP5916898B2 (ja) 2016-05-11
CN104471708A (zh) 2015-03-25
KR20140111716A (ko) 2014-09-19

Similar Documents

Publication Publication Date Title
KR101891862B1 (ko) 다수의 인터포저를 갖는 적층형 다이 조립체
US8704384B2 (en) Stacked die assembly
TWI890731B (zh) 依據矽穿孔交互連接線連接器及矽交互連接線橋所建構之晶片封裝結構
US12033976B2 (en) Semiconductor package having a through intervia through the molding compound and fan-out redistribution layers disposed over the respective die of the stacked fan-out system-in-package
US11670585B1 (en) Power distribution for active-on-active die stack with reduced resistance
CN112514062B (zh) 具有在芯片与封装衬底之间提供电源连接的芯片互连桥的多芯片封装结构
KR102854201B1 (ko) 선택가능한 모놀리식 또는 외부 확장가능 다이-투-다이 상호연결 시스템 방법
TW202549125A (zh) 依據矽穿孔交互連接線垂直連接器建構之3d晶片封裝結構
US8519543B1 (en) Large sized silicon interposers overcoming the reticle area limitations
US11929261B2 (en) Semiconductor package and method of manufacturing the same
KR102946228B1 (ko) 크로스오버 다이 및 관통 다이 비아를 사용하여 다이 사이의 상호접속 생성
CN116057699A (zh) 使用混合扇出的混合密度互连架构
US20130200511A1 (en) Reducing stress in multi-die integrated circuit structures
US20180047663A1 (en) Standalone interface for stacked silicon interconnect (ssi) technology integration
CN105895623B (zh) 用于半导体封装件的衬底设计及其形成方法
KR20120135897A (ko) 리세스된 반도체 기판
US10217723B2 (en) Semiconductor package with improved bandwidth
JP2023516129A (ja) 高帯域幅モジュール
TWI876303B (zh) 半導體結構與其形成方法與半導體組裝
KR102774034B1 (ko) 방열 블록을 포함한 InFO 패키지
US11728275B2 (en) Semiconductor package and manufacturing method thereof
US10756019B1 (en) Systems providing interposer structures
CN116206985A (zh) 块状硅中介层芯片封装方法
TWI866323B (zh) 半導體封裝及其製造方法
US12525578B2 (en) Thermally-aware semiconductor packages

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
A302 Request for accelerated examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20210723

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20220722

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 8

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000