CN104465779A - 漏端隔离的高压ldmos的结构及制作方法 - Google Patents
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Abstract
本发明公开了一种漏端隔离的高压LDMOS的结构，其N型漂移区和N型埋层之间有一层用于隔离漏端和N型埋层的P型区域，该P型区域与P阱相连。本发明还公开了上述结构的漏端隔离的高压LDMOS的制作方法，该方法在形成P阱后，生长栅氧前，通过高能量硼注入，在漂移区下方、N型埋层上方形成一层P型区域。本发明在常规LDMOS的制作工艺基础上，通过双深N阱扩散工艺，在漂移区下方注入一层P型区域，隔离漏端和N型埋层，使漏端对P型衬底形成N/P/N/P结构，从而使得LDMOS的漏端在有反向负载电压的情况下，和P型衬底隔离，避免了衬底漏电流的产生。
Description
技术领域
本发明涉及集成电路制造领域，具体地说，是涉及高压BCD工艺中，漏端隔离的高压LDMOS的结构及制作方法。
背景技术
在高压BCD(bipolar CMOS DMOS)工艺中，常规的LDMOS(横向扩散金属氧化物半导体)由于其N型漏端和P型衬底(Sub)形成PN结，因此在漏端有反向偏压的时候，会造成衬底端有较大的衬底漏电流，从而很容易造成电路失效。
如图1所示，在常规LDMOS结构中，N型漏端和P型衬底端是个反向二极管结构，所以在N型漏端有反向偏压时候，该二极管正向导通，使得对P型衬底端漏电；常用的解决方法是在该种LDMOS的外围加上很宽的一圈P型衬底接地引出端，目的在于在该二极管正向导通时，尽量使该衬底电流流向地而不是芯片内部，但是这种办法会使芯片面积加大，并且往往没有效果。
发明内容
本发明要解决的技术问题之一是提供一种漏端隔离的高压LDMOS的结构，它可以避免因衬底端产生漏电流而导致的电路失效问题。
为解决上述技术问题，本发明的漏端隔离的高压LDMOS的结构，其N型漂移区和N型埋层之间有一层用于隔离漏端和N型埋层的P型区域，该P型区域与P阱相连。
本发明要解决的技术问题之二是提供上述漏端隔离的高压LDMOS的制作方法，该方法工艺简单，成本低。
为解决上述技术问题，本发明的漏端隔离的高压LDMOS的制作方法，包括以下步骤：
1)在P型衬底上，用光罩定义N型埋层注入区域，注入锑，高温推阱，形成N型埋层；
2)用光罩定义P型埋层注入区域，注入硼，快速热退火，形成P型埋层；
3)淀积P型外延；
4)用光罩定义深N阱注入区域，注入磷，高温推阱，形成深N阱；
5)淀积SiN，用光罩定义有源区，刻蚀掉有源区上的SiN，然后刻蚀浅沟槽隔离，并填充HTO，磨平，去掉SiN，形成浅沟槽隔离；
6)用光罩定义N阱注入区域，注入磷，形成N阱；
7)用光罩定义N型漂移区，注入磷，形成N型漂移区；
8)用光罩定义P阱注入区域，注入硼，形成P阱；
9)用光罩定义P型区域，进行高能量硼注入，在N型漂移区和N型埋层之间形成一层用于隔离N型埋层和漏端的P型区域；
10)生长栅氧化层，并淀积多晶硅，用光罩定义P型体区，进行多晶硅刻蚀，然后进行硼注入，形成P型体区，作为LDMOS的沟道；
11)多晶硅刻蚀，形成LDMOS的栅极、源极端的场板和漏极端的场板；
12)用光罩定义N+和P+的源漏注入区域，进行离子注入，形成高压端N+的引出和低压端P+的引出，后续按照常规方法完成LDMOS的制作。
本发明在常规LDMOS的制作工艺基础上，通过双深N阱扩散工艺，在漂移区下方注入了一层P型区域，将LDMOS的漏端和下面的N型埋层隔离开，从而使得LDMOS漏端对P型衬底形成N/P/N/P的结构，在使用的时候，只要保证N型埋层电位大于等于LDMOS漏端电位和P型区域，就可以使LDMOS的漏端在有反向负载电压(最高40V)的情况下，和P型衬底隔离，避免因N型漏端与P型衬底二极管导通而漏电；同时由于这层P型区域的引入，和N型漂移区形成RESURF结构，从而还能提高LDMOS的击穿电压，降低LDMOS的导通电阻(Rdson)。
附图说明
图1是常规LDMOS的结构示意图。
图2～图11是本发明实施例的漏端隔离的高压LDMOS的制作流程示意图。
图中附图标记说明如下：
1：P型衬底
2：N型埋层
3：P型埋层
4：P型外延
5：深N阱
6：浅沟槽隔离
7：N阱
8：Ndrift
9：P阱
10：P型区域
11：栅氧化层
12：多晶硅
13：P型体区
14：N+
15：P+
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解，现结合图示的实施方式，详述如下：
本实施例的漏端隔离的高压LDMOS的具体制作流程，包括以下步骤：
步骤1，准备一片P型硅片，如图2所示。该P型硅片的掺杂浓度由器件设计的耐压决定，对于设计电压在40V的BCD工艺，通常要求硅片的电阻率在13ohm.cm左右。
步骤2，如图3所示，通过光罩定义出N型埋层(NBL)注入区域，进行锑(Sb)注入(注入剂量5E14个/cm2，注入能量80Kev)；注完之后1200℃高温推阱40分钟，形成N型埋层2；接着再通过光罩定义出P型埋层(PBL)注入区域，进行硼(B)注入(注入剂量6E12个/cm2，注入能量60Kev)，并通过1100℃快速热退火(RTA)60秒处理，形成P型埋层3。
步骤3，淀积P型外延(PEPI)4，如图4所示。P型外延4的浓度和厚度由高压LDMOS器件的耐压以及漏端隔离需要的耐压共同决定，本实施例对于40V的BCD工艺，要同时满足漏端隔离需要的耐压，P型外延4的厚度为6μm，电阻率为10ohm.cm。
步骤4，如图5所示，通过光罩定义出深N阱(DNW)注入区域，进行磷(P)的注入(注入剂量3E12个/cm2，注入能量2000Kev)，注完之后1175℃高温推阱120分钟，形成深N阱5。
深N阱5注入的区域是在漏端隔离LMDOS器件的外围一圈，其浓度和宽度需要满足横向PNP耐压的需求，深度需要和下面的N型埋层2短接在一起，使N型埋层2之内的P型区域和外面的P型区域隔离开。
步骤5，如图6所示，淀积SiN，然后通过光罩定义出有源区，刻蚀掉有源区上的SiN，然后刻蚀出浅沟槽隔离(STI)，并填充二氧化硅(HTO)，通过化学机械研磨(CMP)磨平后，去掉SiN，形成浅沟槽隔离6结构。该浅沟槽隔离6结构同时作为LDMOS的漂移区场氧。
步骤6，如图7所示，通过光罩定义出N阱(NW)注入区域，进行2次磷注入(第一次注入剂量5E12个/cm2，注入能量350Kev；第二次注入剂量2.2E12个/cm2，注入能量50Kev)，形成N阱7。然后再通过光罩定义出LDMOS的N型漂移区(Ndrift)，注入磷(注入剂量3E12个/cm2，注入能量300Kev)，形成N型漂移区8。N型漂移区8注入的能量和剂量需要满足能和后续形成的P型区域10形成RESURF(Reduced Surface Field，降低表面电场)结构。
步骤7，如图8所示，通过光罩定义出P阱(PW)注入区域，进行3次硼注入(第一次注入剂量5E11个/cm2，注入能量1200Kev；第二次注入剂量2E12个/cm2，注入能量500Kev；第三次注入剂量6E12个/cm2，注入能量100Kev)，形成P阱9；然后再通过光罩定义出用于隔离N型埋层2和漏端的P型区域，进行高能量硼注入(注入剂量3E12个/cm2，注入能量1500Kev)，形成P型区域10。
P阱9的深度要求能够和P型埋层3、P型区域10相连，以形成隔离结构；P阱9的浓度需要满足横向耐压40V的要求。
P型区域10的深度和浓度要求能够满足隔离漏端的耐压要求和对N型埋层2的耐压要求，并且能和N型漂移区8形成RESURF效果。
步骤8，如图9所示，生长栅氧化层11，并淀积多晶硅12，通过光罩定义出P型体区(Pbody)，进行多晶硅刻蚀，刻蚀完后进行硼注入(注入剂量3E13个/cm2，注入能量150Kev，注入角度30度)，形成0.5μm左右的P型体区13作为LDMOS的沟道。
步骤9，如图10所示，通过光罩定义出栅极多晶硅(gate poly)和漂移区场氧上的场板多晶硅，进行多晶硅刻蚀，形成LDMOS的栅极、源极端的场板和漏极端的场板。
步骤10，如图11所示，通过光罩定义出N+和P+的源漏注入区域，进行N+离子注入(注入砷，注入剂量5E15个/cm2，注入能量50Kev)，形成高压端N+的引出(N+14)；进行P+离子注入(注入硼，注入剂量2E15个/cm2，注入能量20Kev)，形成低压端P+的引出(P+15)。
步骤11，进行后续工艺(包括接触孔、金属层、钝化层等工艺)，将电极引出，完成LDMOS的制作。
Claims (10)
1.漏端隔离的高压LDMOS的结构，其特征在于：N型漂移区和N型埋层之间有一层用于隔离漏端和N型埋层的P型区域，该P型区域与P阱相连。
2.权利要求1所述漏端隔离的高压LDMOS的制作方法，其特征在于，步骤包括：
1)在P型衬底上，用光罩定义N型埋层注入区域，注入锑，高温推阱，形成N型埋层；
2)用光罩定义P型埋层注入区域，注入硼，快速热退火，形成P型埋层；
3)淀积P型外延；
4)用光罩定义深N阱注入区域，注入磷，高温推阱，形成深N阱；
5)淀积SiN，用光罩定义有源区，刻蚀掉有源区上的SiN，然后刻蚀浅沟槽隔离，并填充HTO，磨平，去掉SiN，形成浅沟槽隔离；
6)用光罩定义N阱注入区域，注入磷，形成N阱；
7)用光罩定义N型漂移区，注入磷，形成N型漂移区；
8)用光罩定义P阱注入区域，注入硼，形成P阱；
9)用光罩定义P型区域，进行高能量硼注入，在N型漂移区和N型埋层之间形成一层用于隔离N型埋层和漏端的P型区域；
10)生长栅氧化层，并淀积多晶硅，用光罩定义P型体区，进行多晶硅刻蚀，然后进行硼注入，形成P型体区，作为LDMOS的沟道；
11)多晶硅刻蚀，形成LDMOS的栅极、源极端的场板和漏极端的场板；
12)用光罩定义N+和P+的源漏注入区域，进行离子注入，形成高压端N+的引出和低压端P+的引出，后续按照常规方法完成LDMOS的制作。
3.根据权利要求2所述的方法，其特征在于，步骤1)，1200℃推阱40分钟。
4.根据权利要求2所述的方法，其特征在于，步骤3)，P型外延厚度为6μm，电阻率为10ohm.cm。
5.根据权利要求2所述的方法，其特征在于，步骤4)，1175℃推阱2小时。
6.根据权利要求2所述的方法，其特征在于，深N阱和N型埋层相连。
7.根据权利要求2所述的方法，其特征在于，P阱和P型埋层、P型区域相连。
8.根据权利要求2所述的方法，其特征在于，步骤9)，硼注入能量为1500Kev。
9.根据权利要求2所述的方法，其特征在于，步骤10)，硼注入角度为35度。
10.根据权利要求2所述的方法，其特征在于，P型体区的长度为0.5μm。
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