WO2022134571A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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WO2022134571A1
WO2022134571A1 PCT/CN2021/108670 CN2021108670W WO2022134571A1 WO 2022134571 A1 WO2022134571 A1 WO 2022134571A1 CN 2021108670 W CN2021108670 W CN 2021108670W WO 2022134571 A1 WO2022134571 A1 WO 2022134571A1
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region
drift region
polysilicon film
photoresist
drift
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PCT/CN2021/108670
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English (en)
French (fr)
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金宏峰
曹瑞彬
林峰
秦祥
黄宇
李春旭
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无锡华润上华科技有限公司
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Priority to US18/258,902 priority Critical patent/US20240047212A1/en
Publication of WO2022134571A1 publication Critical patent/WO2022134571A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Definitions

  • the present application relates to the technical field of semiconductors, and in particular, to a semiconductor device and a preparation method thereof.
  • the fabrication process of the channel is basically the same, including: polysilicon growth, P-Body PHO (P-type body region photolithography layer), polysilicon etching, P-Body IMP (P-type body Region implantation), through the self-alignment process, the channel length of NLDMOS is greatly shortened and the channel length is kept stable.
  • P-Body PHO P-type body region photolithography layer
  • P-Body IMP P-type body Region implantation
  • a preparation method of a semiconductor device comprising:
  • the doped region includes an adjacent first drift region and a second drift region, and the second conductivity type is opposite to the first conductivity type;
  • a polysilicon film is formed on the substrate, and the polysilicon film covers the doped region;
  • a photoresist pattern is formed on the polysilicon film, and the photoresist in the photoresist pattern covers the first drift region and the second drift region, and exposes the body region between the first drift region and the second drift region.
  • the step of forming a doped region of the second conductivity type on the substrate includes:
  • the doped region includes a first drift region, a second drift region, and a body region preset region located between the first drift region and the second drift region.
  • the step of forming a photoresist pattern on the polysilicon film includes:
  • An I-line photoresist pattern is formed on the polysilicon film, and the thickness of the photoresist pattern is greater than or equal to 1.6 microns and less than or equal to 2.5 microns.
  • the step of performing high-energy ion implantation includes:
  • High-energy ion implantation with implantation energy greater than or equal to 500 keV and less than or equal to 800 keV is performed.
  • the step of forming a photoresist pattern on the polysilicon film includes:
  • a new mask design pattern is obtained, wherein the direction of the length is the connection direction of the first drift region and the second drift region;
  • the inclination angle of the photoresist located on the first drift region and the second drift region in the new photoresist pattern is the same, and the inclination angle refers to the clamping angle between the sidewall and the bottom of the photoresist. horn.
  • the step of obtaining a new mask design pattern is realized by correcting the optical proximity effect.
  • the method further includes:
  • An etching process is performed to remove the polysilicon film on the pre-set area of the body region to obtain a polysilicon layer composed of the remaining polysilicon film.
  • the length of the upper surface of the body region is greater than the length of the lower surface of the body region.
  • a semiconductor device is produced by any one of the above-mentioned preparation methods.
  • the semiconductor device comprises a laterally diffused metal oxide semiconductor device.
  • the above-mentioned method for preparing a semiconductor device comprises forming a polysilicon film with photoresist covering the first drift region and the second drift region on the polysilicon film, and exposing the body region between the first drift region and the second drift region. After the photoresist pattern of the polysilicon film on the body region is formed, a body region of the first conductivity type is formed in the body region preset region by high-energy ion implantation. It avoids the thinning of the thickness of the photoresist covering the first drift region and the second drift region due to etching.
  • FIG. 1 is a flow chart of a method for fabricating a semiconductor device in one embodiment
  • FIG. 2 is a schematic cross-sectional view of a semiconductor device after forming a doped region on a substrate in Embodiment 1;
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device after the photoresist pattern is formed corresponding to FIG. 2;
  • FIG. 4 is a schematic cross-sectional view of the semiconductor device after the body region corresponding to FIG. 3 is formed;
  • FIG. 5 is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 4 after removing the photoresist pattern layer;
  • FIG. 6 is a side view when a photoresist pattern is formed using a conventional mask in Embodiment 2;
  • FIG. 7 is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 6 after the polysilicon layer is formed;
  • FIG. 9 is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 8 after the polysilicon layer is formed;
  • 10 is a schematic cross-sectional view of 16V, 18V, 24V, and 32V NLDMOS devices after etching to form polysilicon layers, respectively.
  • first doping type becomes the second doping type
  • second doping type can be the first doping type
  • the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the invention.
  • the steps of forming a body region are as follows: Step 1, polysilicon film growth: growing a polysilicon film on a P-type substrate formed with two N-type drift regions.
  • the second step is to form the body region photoresist pattern: use the body region photolithography to form on the polysilicon film to cover the N-type drift region, and expose the body region preset region located between the adjacent N-type drift regions (phase The photoresist pattern of the substrate between adjacent drift regions), the photoresist pattern is used to define the self-aligned implantation position of the body region.
  • the third step is to etch to form a polysilicon layer: after etching and removing the polysilicon film in the pre-set area of the body region exposed by the photoresist pattern, a polysilicon layer composed of the remaining polysilicon film is obtained.
  • body region implantation P-type ion implantation is performed using the photoresist pattern and the polysilicon layer as a barrier layer, and a P-type body region is formed in the region between adjacent drift regions.
  • the high-energy implantation ions will penetrate the photoresist pattern and the polysilicon layer and enter the N-type drift region.
  • a P-type doped region is formed between the polysilicon layers; and the photoresist in the photoresist pattern is seriously shrunk under the high-energy ion implantation, the photoresist above the drift region near the body region becomes thinner, and the high-energy implanted ions pass through the drift region.
  • the photoresist near the body region enters the substrate, so that the length of the body region increases, thereby affecting the channel length of the semiconductor device.
  • FIG. 1 it is a flow chart of a method for fabricating a semiconductor device in one embodiment.
  • the present application provides a method for preparing a semiconductor device, as shown in FIG. 1 , the method includes:
  • the substrate can be single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator Silicon (SiGeOI), germanium on insulator (GeOI), single crystal silicon doped with impurities of the first conductivity type, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator ( S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.
  • the substrate is a P-type silicon substrate (P-sub), and its specific doping concentration is not limited by the present invention.
  • the doped region includes an adjacent first drift region and a second drift region, and the second conductivity type is opposite to the first conductivity type; when the first conductivity type is P-type, the second conductivity type is N-type, and when the first conductivity type is N-type When the type is N type, the second conductivity type is P type. In this embodiment, the first conductivity type is P type, and the second conductivity type is N type.
  • a polysilicon film is formed on the substrate, and the polysilicon film covers the doped region.
  • the photoresist in the photoresist pattern covers the first drift region and the second drift region, and exposes the polysilicon film on the predetermined region of the body region between the first drift region and the second drift region; that is, photolithography
  • the glue covers the polysilicon film on the first drift region and the second drift region, exposing the polysilicon film over the region between the first drift region and the second drift region.
  • the upper surface of the body region is flush with the upper surface of the doped region, and the lower surface of the body region is not higher than the lower surface of the doped region.
  • high-energy ion implantation is performed on the substrate with a photoresist pattern formed on the surface, and dopant ions of the first conductivity type are implanted into the region (body region) on the substrate located between the first drift region and the second drift region.
  • a body region connecting the first drift region and the second drift region is formed, and the body region is a body region of the first conductivity type.
  • the upper surface of the body region is flush with the upper surface of the doped region, and the lower surface of the body region is not higher than the lower surface of the doped region, that is, the upper surface of the body region is flush with the upper surface of the substrate, and the lower surface of the body region is not higher than the lower surface of the doped region.
  • one side of the body region is in contact with the first drift region, and the other side of the body region is in contact with the second drift region.
  • step S104 includes: performing ion implantation of the second conductivity type, forming a first drift region and a second drift region on the substrate, and the first drift region and the second drift region are located in the first drift region and the second drift region.
  • the substrates between the second drift regions are separated, and at this time, the body region preset region in which the body region is subsequently formed is doped with the first conductivity type and is a part of the substrate.
  • FIG. 2 it is a schematic cross-sectional view of the semiconductor device after the doped regions are formed on the substrate in Embodiment 1.
  • FIG. 2 it is a schematic cross-sectional view of the semiconductor device after the doped regions are formed on the substrate in Embodiment 1.
  • step S104 includes:
  • the ion implantation of the second conductivity type is performed to form a doped region 200 on the substrate 100 .
  • the doped region 200 includes a first drift region 202 , a second drift region 204 , and a body region preset region 206 located between the first drift region 202 and the second drift region 204 .
  • the body region preset region 206 is a region of the second conductivity type, and the concentration of the dopant ions of the second conductivity type in the first drift region 202 and the second drift region 204 is the same.
  • the doped region 200 is formed by implantation in this solution, and the doped region 200 is divided into the first drift region 202 and the second drift region.
  • the region 204 and the three parts of the body region preset region 206 located between the first drift region 202 and the second drift region 204 can avoid using different photoresists to form photoresist patterns due to different photoresist patterns.
  • the alignment accuracy of the lithography machine is different, which leads to the problem that the alignment control ability of the two sides of the formed body region in contact with the edges of the first drift region and the second drift region, respectively, is weakened.
  • the doped region 200 is divided into three parts: the first drift region 202 , the second drift region 204 , and the body region preset region 206 located between the first drift region 202 and the second drift region 204 as an example for exemplary description. .
  • step S108 includes:
  • An I-line photoresist pattern is formed on the polysilicon film, and the thickness of the photoresist pattern is greater than or equal to 1.6 microns and less than or equal to 2.5 microns.
  • FIG. 3 it is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 2 after the photoresist pattern is formed.
  • a photoresist pattern 400 is formed on the polysilicon film 300, and the photoresist in the photoresist pattern 400 is located on the first The polysilicon thin film 300 on the drift region and the second drift region is exposed, and the polysilicon thin film 300 on the pre-set region 206 of the body region is exposed.
  • the steps of forming the photoresist pattern 400 include: the first step, coating the surface of the polysilicon film 300 with a photoresist of a preset thickness, where the preset thickness refers to the ability to block the entry of high-energy ions in the subsequent high-energy ion implantation The photoresist thickness of the doped region 200 under the photoresist.
  • the photoresist coated on the polysilicon film 300 is exposed and developed using a body region mask, and then a photoresist pattern 400 exposing the polysilicon film 300 on the body region preset region 206 is obtained.
  • step S110 includes:
  • High-energy ion implantation with implantation energy greater than or equal to 500 keV and less than or equal to 800 keV is performed.
  • FIG. 4 it is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 3 after the body region is formed.
  • the photoresist pattern 400 as a mask, high-energy ion implantation of the first conductivity type is performed, and the high-energy impurity ions enter the body region preset region 206 to form a body region 208, and the bottom of the body region 208 is not higher than The bottom of the doped region 200 .
  • the first conductivity type is P-type
  • the impurity ions implanted by the high-energy ions include boron ions.
  • FIG. 5 it is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 4 after removing the photoresist pattern layer.
  • step S110 it further includes:
  • An etching process is performed to remove the polysilicon film on the pre-set area of the body region to obtain a polysilicon layer composed of the remaining polysilicon film.
  • the etching process is performed, and after removing the polysilicon film on the predetermined region of the body region, the method further includes: removing the photoresist pattern on the surface of the substrate.
  • the polysilicon film 300 exposed by the photoresist pattern 400 is removed through an etching process to obtain a polysilicon layer 302 composed of the remaining polysilicon film 300 .
  • the photoresist pattern 400 on the substrate 100 is removed by a method commonly used by those skilled in the art to remove the photoresist pattern.
  • FIG. 6 it is a side view of forming a photoresist pattern using a conventional mask in Embodiment 2.
  • FIG. 7 it is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 6 after the polysilicon layer is formed.
  • FIG. 8 it is a side view of forming a photoresist pattern using the mask obtained after adjusting the dimensional deviation of the mask design pattern in Example 2.
  • FIG. 9 it is a schematic cross-sectional view of the semiconductor device corresponding to FIG. 8 after the polysilicon layer is formed.
  • a doped region 20 and a polysilicon film 30 covering the doped region 20 are formed on the substrate 10 , wherein the doped region 20 includes a first doped region 201A and a first doped region 201B , the second doped region 203A, the second doped region 203B, the body region preset region 205A, the body region preset region 205B and the body region preset region 205C, using the existing body region mask 40 for the polysilicon film 30
  • the first photolithography pattern 50 is obtained after the photoresist coated thereon is exposed and developed.
  • the length D1 of the second doping region 203A is smaller than the length D2 of the first doping region 201B.
  • a body region 207A is formed in the body region preset region 205A
  • a body region 207B is formed in the body region preset region 205B
  • a body region is formed in the body region preset region 205B, respectively.
  • the predetermined region 205C forms a body region 207C.
  • the amount of shrinkage of the photoresist 501 on the second drift region 203A is smaller than that of the first drift region 201B
  • the amount of shrinkage of the photoresist 503 on top, after the high-energy ion implantation, the angle A between the sidewall and the bottom of the photoresist 501 is greater than the angle B between the sidewall and the bottom of the photoresist 503 .
  • the length L1 of the first conductivity type doped region formed under the photoresist 501 is smaller than that in the photoresist.
  • a length L2 of the doped region of the first conductivity type is formed under the resist 503 .
  • the size of the drift region of NLDMOS devices with different voltage levels is different. The larger the withstand voltage, the larger the size of the drift region, and the longer the channel between the corresponding drift regions. That is, when the distance between adjacent drift regions is the same, doping The channel lengths differ between regions.
  • step S108 includes:
  • a new mask design pattern is obtained, wherein the direction of the length is the first drift region and the second drift region connection direction.
  • a mask is made according to the new mask design pattern.
  • a mask is used to form a new photoresist pattern on the polysilicon thin film; wherein, after the high-energy ion implantation step, the photolithography on the first drift region and the second drift region in the new photoresist pattern
  • the inclination angle of the photoresist is the same, and the inclination angle refers to the angle between the sidewall and the bottom of the photoresist.
  • Adjusting the size deviation of the mask design pattern by the length of the first drift region and the second drift region can eliminate the difference in the shrinkage amount of the photoresist caused by the difference in the length of the drift region.
  • the first step is to obtain the length X1 of the first drift region 201A, the length X2 of the first drift region 201B and the second drift region in the doped region 20 on the substrate 10
  • the size deviation in the mask design pattern is obtained, and a new mask design pattern is obtained.
  • a mask 60 is produced according to the new mask design pattern, wherein the mask 60 includes a new first pattern 601 , a second pattern 603 , a third pattern 605 and a fourth pattern 607 .
  • the mask 60 is used to expose and develop the photoresist coated on the polysilicon film 30 to obtain a second photoresist pattern 70.
  • the body region in FIG. 8 is preset The photoresist located between the dotted lines on the region 205A, the body region preset region 205B and the body region preset region 205C is the newly added photoresist.
  • a body region 209A is formed in the body region preset region 205A
  • a body region 209B is formed in the body region preset region 205B
  • a body region is formed in the body region preset region 205B respectively.
  • Set region 205C forms body region 209C.
  • a polysilicon layer 303 composed of the remaining polysilicon film is obtained. At this time, the angle ⁇ between the sidewall and the bottom of the photoresist 701 on the second drift region 203A is equal to the angle ⁇ between the sidewall and the bottom of the photoresist 503 on the first drift region 201B.
  • the length D1 of the second doping region 203A is smaller than the length D2 of the first doping region 201B, during the high-energy ion implantation process, the amount of shrinkage of the photoresist 701 on the second drift region 203A is smaller than that of the first drift region 201B
  • the dimensional deviation added to the mask design pattern corresponding to the mask 60 has eliminated the difference in the amount of shrinkage, and the angle between the sidewall and the bottom of the photoresist after high-energy ion implantation Impact.
  • the length of the doped region of the first conductivity type formed under the photoresist 901 is equal to the length of the doped region of the first conductivity type formed under the photoresist 703 .
  • the dimensions of the drift regions are different, when the distances between adjacent drift regions are the same, the channel lengths between the doped regions are also the same.
  • the length of the first design pattern corresponding to the first drift region in the mask design pattern is M0
  • the length of the second design pattern corresponding to the second drift region is N0.
  • the length of the first drift region in the doped region on the substrate is M1
  • the length of the second drift region is N1
  • the length of the body region in the first drift region is M2
  • the length of the body region in the second drift region is obtained.
  • the length is N2.
  • the length M0 of the first design pattern the length N0 of the second design pattern, the length M1 of the first drift region, the length N1 of the second drift region, the length M2 of the body region in the first drift region, and the length of the second drift region
  • adjust the length of the first design pattern to M and the length of the second design pattern to N for example, adjust the length M2 of the body region in the first drift region and the length of the body region in the second drift region to M2.
  • the difference between the length N2 and the preset value is added to the first design pattern and the second design pattern, respectively, to obtain the length M of the first design pattern and the length N of the second design pattern; so that the body region in the first drift region is
  • the length of the first design pattern and the length of the body region in the second drift region are both preset values.
  • a new mask design pattern is obtained with the length M of the first design pattern and the length N of the second design pattern, and then according to the new mask design pattern Design graphics to make new masks.
  • a photoresist pattern on the polysilicon film is formed with a new mask. At this time, the angle between the sidewall and the bottom of the photoresist on the first drift region is equal to the photolithography on the second drift region. The angle between the side wall and the bottom of the glue.
  • FIG. 10 cross-sectional schematic diagrams of 16V, 18V, 24V, and 32V NLDMOS devices after the polysilicon layer is formed by etching respectively, wherein the spacing refers to the sum of the length of the drift region and the distance between adjacent drift regions.
  • the size (Top CD) between the photoresists on adjacent drift regions increases with the length of the drift region (voltage of the semiconductor device). increase or decrease), that is, the channel length of the device increases with the length of the drift region.
  • the size (Top CD) between the photoresists on the adjacent drift regions is within the preset range, and does not change with the length of the drift region (the size of the semiconductor device voltage changes), that is, the channel length of the device remains unchanged, and the angle between the sidewall and the bottom of the photoresist on the drift region is basically unchanged.
  • the step of obtaining a new mask design pattern is realized by correcting the optical proximity effect.
  • the length of the upper surface of the body region is greater than the length of the lower surface of the body region, that is, the body region has a wide and narrow structure from top to bottom.
  • a semiconductor device is produced by any one of the above-mentioned preparation methods.
  • the semiconductor device comprises a laterally diffused metal oxide semiconductor device.
  • the above-mentioned method for preparing a semiconductor device comprises forming a polysilicon film with photoresist covering the first drift region and the second drift region on the polysilicon film, and exposing the body region between the first drift region and the second drift region. After the photoresist pattern of the polysilicon film on the body region is formed, a body region of the first conductivity type is formed in the body region preset region by high-energy ion implantation. It avoids the thinning of the thickness of the photoresist covering the first drift region and the second drift region due to etching.

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Abstract

本发明涉及一种半导体器件及其制备方法，包括：提供第一导电类型的衬底；在衬底上形成第二导电类型的掺杂区，掺杂区包括相邻的第一漂移区和第二漂移区，第二导电类型和所述第一导电类型相反；在衬底上形成多晶硅薄膜，多晶硅薄膜覆盖在掺杂区上；在多晶硅薄膜上形成光刻胶图形，光刻胶图形中的光刻胶覆盖在第一漂移区和第二漂移区上，且露出位于第一漂移区和第二漂移区之间的体区预设区上的多晶硅薄膜；进行高能离子注入，在体区预设区形成第一导电类型的体区，体区的上表面与掺杂区的上表面齐平，且体区的下表面不高于掺杂区的下表面。避免了光刻胶因刻蚀过程中的高温而发生形貌变化，进而对高能离子注入效果产生影响的问题。

Description

半导体器件及其制备方法 技术领域
本申请涉及半导体技术领域，特别是涉及一种半导体器件及其制备方法。
背景技术
对中低压7V～45V NLDMOS的半导体器件，沟道的制作工艺基本一致，包括：多晶硅生长、P-Body PHO(P型体区光刻层)、多晶硅刻蚀、P-Body IMP(P型体区注入)，通过自对准工艺，大大缩短了NLDMOS的沟道长度并保持沟道长度的稳定。但随着半导体工艺的发展，为了进一步降低Vt，避免寄生NPN型晶体管的触发，提升NLDMOS的BV_on及TLP(Transmission linepulse，传输线脉冲)能力，需要进一步加深PB(P-Body，P型体区)的注入深度。此时，在原有的工艺整合方式“多晶硅生长+PB PHO+多晶硅刻蚀+PB注入”的基础上，需要增加PB PHO中光刻胶的厚度，才能达到阻挡高能离子注入，保护光刻胶覆盖区域的目的。但是，进行高能离子注入存在以下问题：1、193nm DUV光刻机常用的光刻胶的厚度<1.3um，此时光刻胶的胶厚不足以阻挡高能离子的注入，更厚的DUV光刻胶成本太高；2、高能离子注入过程中，因光刻胶缩胶形貌变化严重，导致LDMOS器件沟道区域的P型注入离子的浓度增加，Vt偏高；3、在间距(pitch)变化的情况下，不同档位的LDMOS器件之间Vt均匀性的差异比较明显。
发明内容
基于此，有必要针对上述问题提供一种半导体器件及其制备方法。
一种半导体器件的制备方法，包括：
提供第一导电类型的衬底；
在衬底上形成第二导电类型的掺杂区，掺杂区包括相邻的第一漂移区和第二漂移区，第二导电类型和第一导电类型相反；
在衬底上形成多晶硅薄膜，多晶硅薄膜覆盖在掺杂区上；
在多晶硅薄膜上形成光刻胶图形，光刻胶图形中的光刻胶覆盖在第一漂移区和第二漂移区上，且露出位于第一漂移区和第二漂移区之间的体区预设区上的多晶硅薄膜；
进行高能离子注入，在体区预设区形成第一导电类型的体区，体区的上表面与掺杂区的上表面齐平，且体区的下表面不高于掺杂区的下表面。
在其中一个实施例中，在衬底上形成第二导电类型的掺杂区的步骤包括：
进行第二导电类型离子注入，在衬底上形成掺杂区；
其中，掺杂区包括第一漂移区、第二漂移区、以及位于第一漂移区和第二漂移区之间的体区预设区。
在其中一个实施例中，在多晶硅薄膜上形成光刻胶图形的步骤包括：
在多晶硅薄膜上形成I线光刻胶图形，光刻胶图形的厚度大于或等于1.6微米且小于或等于2.5微米。
在其中一个实施例中，进行高能离子注入的步骤包括：
进行注入能量大于或等于500千电子伏且小于或等于800千电子伏的高能离子注入。
在其中一个实施例中，在多晶硅薄膜上形成光刻胶图形的步骤包括：
根据第一漂移区和第二漂移区的长度调整掩膜设计图形的尺寸偏差后，得到新的掩膜设计图形，其中长度的方向为第一漂移区和第二漂移区的连线方向；
根据新的掩膜设计图形制作掩膜版；
使用掩膜版在多晶硅薄膜上形成新的光刻胶图形；
其中，进行高能离子注入步骤后，新的光刻胶图形中位于第一漂移区和第二漂移区上的光刻胶的倾角相同，倾角是指光刻胶的侧壁与底部之间的夹角。
在其中一个实施例中，根据第一漂移区和第二漂移区的长度调整掩膜设计图形的尺寸偏差后，得到新的掩膜设计图形的步骤是通过光学邻近效应矫正的方式实现的。
在其中一个实施例中，进行高能离子注入之后还包括：
进行刻蚀工艺，去除体区预设区上的多晶硅薄膜，得到由剩余多晶硅薄膜构成的多晶硅层。
在其中一个实施例中，体区的上表面的长度大于体区的下表面的长度。
一种半导体器件，是通过上述任一项所述的制备方法制成的。
在其中一个实施例中，半导体器件包括横向扩散金属氧化物半导体器件。
上述半导体器件的制备方法，在多晶硅薄膜上形成光刻胶覆盖在第一漂移区和第二漂移区上的多晶硅薄膜，且露出位于第一漂移区和第二漂移区之间的体区预设区上的多晶硅薄膜的光刻胶图形后，通过高能离子注入在体区预设区形成第一导电类型的体区，与先刻蚀去除体区预设区上的多晶硅薄膜后进行高能离子注入相比，避免了因刻蚀导致覆盖在第一漂移区和第二漂移区上的光刻胶的厚度变薄，在不影响光刻胶对高能离子注入中注入离 子的阻挡效果的情况下，需要进一步增加光刻胶的厚度，从而增加半导体器件的制备成本、增加工艺难度的问题；同时避免了光刻胶因刻蚀过程中的高温而发生形貌变化，进而对高能离子注入效果产生影响的问题。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中半导体器件的制备方法的流程图；
图2为实施例1中在衬底上形成掺杂区之后半导体器件的剖面示意图；
图3为图2对应的形成光刻胶图形之后半导体器件的剖面示意图；
图4为图3对应的形成体区之后半导体器件的剖面示意图；
图5为图4对应的去除光刻胶图形层后半导体器件的剖面示意图；
图6为实施例2中使用传统掩膜版形成光刻胶图形时的侧视图；
图7为图6对应的形成多晶硅层后半导体器件的剖面示意图；
图8为实施例2中使用调整掩膜设计图形的尺寸偏差后得到的掩膜版形成光刻胶图形时的侧视图；
图9为图8对应的形成多晶硅层后半导体器件的剖面示意图；
图10为分别刻蚀形成多晶硅层后16V、18V、24V、32V NLDMOS器件的剖面示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或 层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
典型的半导体器件的制备方法中，形成体区的步骤如下：第一步，多晶硅薄膜生长：在形成有两个N型漂移区的P型衬底上成长多晶硅薄膜。第二步，形成体区光刻胶图形： 使用体区光刻版在多晶硅薄膜上形成覆盖在N型漂移区上，且露出位于相邻N型漂移区之间的体区预设区(相邻漂移区之间的衬底)的光刻胶图形，所述光刻胶图形用于定义体区的自对准注入位置。第三步，刻蚀形成多晶硅层：刻蚀去除光刻胶图形露出的体区预设区的多晶硅薄膜后，得到由剩余多晶硅薄膜构成的多晶硅层。第四步，体区注入：以光刻胶图形和多晶硅层为阻挡层进行P型离子注入，在相邻漂移区之间的区域形成P型体区。
为了进一步降低半导体器件的Vt，避免寄生NPN的触发，并提升NLDMOS的BV_on及TLP能力，需要加深体区注入的注入深度。但是，使用提高体区注入的注入能量的高能注入来加深体区的注入深度时，高能注入离子会穿透光刻胶图形和多晶硅层后进入到N型漂移区中，在N型漂移区和多晶硅层之间形成P型掺杂区；并且高能离子注入下光刻胶图形中的光刻胶缩胶严重，漂移区靠近体区位置上方的光刻胶变薄，高能注入离子穿过漂移区靠近体区位置的光刻胶进入到衬底中，使得体区的长度增加，进而影响半导体器件的沟道长度。
参见图1，为一实施例中半导体器件的制备方法的流程图。
为了解决上述问题，本申请提供一种半导体器件的制备方法，如图1所示，该方法包括：
S102，提供第一导电类型的衬底。
衬底可以采用表面形成有第一导电类型掺杂层的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)、绝缘体上锗(GeOI)，也可以采用掺杂有第一导电类型杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)、绝缘体上锗(GeOI)等。作为示例，在本实施例中，衬底为P型硅衬底(P-sub)，其具体的掺杂浓度不受本发明限制。
S104，在衬底上形成第二导电类型的掺杂区。
掺杂区包括相邻的第一漂移区和第二漂移区，第二导电类型和第一导电类型相反；当第一导电类型为P型时，第二导电类型为N型，当第一导电类型为N型时，第二导电类型为P型。在本实施例中，第一导电类型为P型，第二导电类型为N型。
S106，在衬底上形成多晶硅薄膜，多晶硅薄膜覆盖在掺杂区上。
S108，在多晶硅薄膜上形成光刻胶图形。
光刻胶图形中的光刻胶覆盖在第一漂移区和第二漂移区上，且露出位于第一漂移区和第二漂移区之间的体区预设区上的多晶硅薄膜；即光刻胶覆盖在第一漂移区和第二漂移区上的多晶硅薄膜的上方，露出位于第一漂移区和第二漂移区之间的区域上方的多晶硅薄 膜。
S110，进行高能离子注入，在体区预设区形成第一导电类型的体区。
体区的上表面与掺杂区的上表面齐平，且体区的下表面不高于掺杂区的下表面。
具体地，对表面形成有光刻胶图形的衬底进行高能离子注入，将第一导电类型的掺杂离子注入到衬底上位于第一漂移区和第二漂移区之间的区域(体区预设区)，形成连接第一漂移区和第二漂移区的体区，所述体区为第一导电类型的体区。体区的上表面与掺杂区的上表面齐平，体区的下表面不高于掺杂区的下表面，即体区的上表面与衬底的上表面齐平，体区的下表面与掺杂区下方的衬底接触，体区的一侧与第一漂移区接触，体区的另一侧与第二漂移区接触。
在其中一个实施例中，步骤S104包括：进行第二导电类型离子注入，在衬底上形成第一漂移区和第二漂移区，第一漂移区和第二漂移区被位于第一漂移区和第二漂移区之间的衬底隔开，此时，后续形成体区的体区预设区为第一导电类型掺杂，且为衬底的一部分。
参见图2，为实施例1中在衬底上形成掺杂区之后半导体器件的剖面示意图。
如图2，在其中一个实施例中，步骤S104包括：
进行第二导电类型离子注入，在衬底100上形成掺杂区200。其中，掺杂区200包括第一漂移区202、第二漂移区204、以及位于第一漂移区202和第二漂移区204之间的体区预设区206。此时，体区预设区206为第二导电类型区域，且与第一漂移区202、第二漂移区204中第二导电类型的掺杂离子的浓度相同。与第一漂移区和第二漂移区之间的体区预设区为衬底相比，本方案通过注入形成掺杂区200，并且掺杂区200分为第一漂移区202、第二漂移区204，以及位于第一漂移区202和第二漂移区204之间的体区预设区206三部分，可以避免使用不同光刻胶形成光刻胶图形时，因形成光刻胶图形的不同光刻机台的对位精度不同，导致形成的体区的两侧分别与第一漂移区和第二漂移区的边缘接触的对位控制能力变弱的问题。以下以掺杂区200分为第一漂移区202、第二漂移区204，以及位于第一漂移区202和第二漂移区204之间的体区预设区206三部分为例进行示例性描述。
在其中一个实施例中，步骤S108包括：
在多晶硅薄膜上形成I线光刻胶图形，光刻胶图形的厚度大于或等于1.6微米且小于或等于2.5微米。
参见图3，为图2对应的形成光刻胶图形之后半导体器件的剖面示意图。
如图3，在衬底100上形成覆盖在掺杂区200上的多晶硅薄膜300之后，在多晶硅薄膜300上形成光刻胶图形400，光刻胶图形400中的光刻胶位于覆盖在第一漂移区和第二漂移区上的多晶硅薄膜300上，且露出体区预设区206上的多晶硅薄膜300。具体地，形 成光刻胶图形400的步骤包括：第一步，在多晶硅薄膜300表面涂覆预设厚度的光刻胶，预设厚度是指能够起到阻挡后续高能离子注入中的高能离子进入位于光刻胶下方的掺杂区200的光刻胶厚度。第二步，使用体区掩膜版对多晶硅薄膜300上涂覆的光刻胶进行曝光、显影，后得到露出体区预设区206上的多晶硅薄膜300的光刻胶图形400。
在其中一个实施例中，步骤S110包括：
进行注入能量大于或等于500千电子伏且小于或等于800千电子伏的高能离子注入。
参见图4，为图3对应的形成体区之后半导体器件的剖面示意图。
如图4，以光刻胶图形400为掩膜，进行第一导电类型的高能离子注入，高能杂质离子进入在体区预设区206位置后形成体区208，体区208的底部不高于掺杂区200的底部。
在其中一个实施例中，第一导电类型为P型，高能离子注入的杂质离子包括硼离子。
参见图5，为图4对应的去除光刻胶图形层后半导体器件的剖面示意图。
在其中一个实施例中，步骤S110之后还包括：
进行刻蚀工艺，去除体区预设区上的多晶硅薄膜，得到由剩余多晶硅薄膜构成的多晶硅层。
在其中一个实施例中，进行刻蚀工艺，去除体区预设区上的多晶硅薄膜之后还包括：去除衬底表面的光刻胶图形的步骤。
如图5，在形成体区208之后，通过刻蚀工艺，去除光刻胶图形400露出的多晶硅薄膜300，得到由剩余的多晶硅薄膜300构成的多晶硅层302。然后，选取本领域技术人员常用的去除光刻胶图形的方式去除衬底100上的光刻胶图形400。通过先形成体区后去除光刻胶图形400露出的体区上的多晶硅薄膜，避免了先刻蚀后注入时，刻蚀工艺对光刻胶图形中的光刻胶的厚度和形貌的影响。
参见图6，为实施例2中使用传统掩膜版形成光刻胶图形时的侧视图。参见图7，为图6对应的形成多晶硅层后半导体器件的剖面示意图。参见图8，为实施例2中使用调整掩膜设计图形的尺寸偏差后得到的掩膜版形成光刻胶图形时的侧视图。参见图9，为图8对应的形成多晶硅层后半导体器件的剖面示意图。
如图6、图7，衬底10上形成有掺杂区20、以及覆盖在掺杂区20上的多晶硅薄膜30，其中掺杂区20包括第一掺杂区201A、第一掺杂区201B、第二掺杂区203A、第二掺杂区203B、体区预设区205A、体区预设区205B和体区预设区205C，使用现有的体区掩膜版40对多晶硅薄膜30上涂覆的光刻胶进行曝光显影后得到第一光刻图形50。其中，第二掺杂区203A的长度D1小于第一掺杂区201B的长度D2。以第一光刻胶图形50和多晶硅薄膜30为阻挡层，进行高能离子注入后，分别在体区预设区205A形成体区207A、在体区 预设区205B形成体区207B、在体区预设区205C形成体区207C。然后刻蚀去除未被光刻胶覆盖的多晶硅薄膜30后，得到由剩余多晶硅薄膜构成的多晶硅层301。因第二掺杂区203A的长度D1小于第一掺杂区201B的长度D2，在进行高能离子注入过程中，第二漂移区203A上的光刻胶501的缩胶量小于第一漂移区201B上的光刻胶503的缩胶量，高能离子注入之后，光刻胶501的侧壁与底部的夹角A大于光刻胶503侧壁与底部的夹角B。高能离子注入中第一导电类型的掺杂离子穿过发生缩胶的光刻胶图形50后，在体区207B中，光刻胶501下形成第一导电类型掺杂区的长度L1小于在光刻胶503下形成第一导电类型掺杂区的长度L2。而不同电压档位的NLDMOS器件的漂移区尺寸不同，耐压越大漂移区的尺寸越大，对应漂移区之间的沟道越长，即相邻漂移区之间的距离相同时，掺杂区之间的沟道长度不同。
在其中一个实施例中，步骤S108包括：
第一步，根据第一漂移区和第二漂移区的长度调整掩膜设计图形的尺寸偏差后，得到新的掩膜设计图形，其中所述长度的方向为第一漂移区和第二漂移区的连线方向。第二步，根据新的掩膜设计图形制作掩膜版。第三步，使用掩膜版在多晶硅薄膜上形成新的光刻胶图形；其中，进行高能离子注入步骤后，新的光刻胶图形中位于第一漂移区和第二漂移区上的光刻胶的倾角相同，倾角是指光刻胶的侧壁与底部之间的夹角。通过第一漂移区和第二漂移区的长度来调整掩膜设计图形的尺寸偏差，可以消除因漂移区的长度不同引起的光刻胶的缩胶量不同，进而对高能离子注入后在长度相同的体区预设区形成不同长度的体区(不同长度的沟道)的问题。
具体地，参见图6、图8、图9，第一步，获取衬底10上掺杂区20中的第一漂移区201A的长度X1、第一漂移区201B的长度X2、第二漂移区203A的长度Y1、第二漂移区203B的长度Y2，然后分别根据长度X1、X2、Y1、Y2调整掩膜版40中的第一图形401、第二图形403、第三图形405和第四图形407在掩膜设计图形中的尺寸偏差，得到新的掩膜设计图形。第二步，根据新的掩膜设计图形制作掩膜版60，其中，掩膜版60包括新的第一图形601、第二图形603、第三图形605和第四图形607。第三步，使用掩膜版60对多晶硅薄膜30上涂覆的光刻胶进行曝光显影后得到第二光刻图形70，与第一光刻胶图形50相比，图8中体区预设区205A、体区预设区205B和体区预设区205C上位于虚线之间的光刻胶为新增的光刻胶。以第二光刻图形70和多晶硅薄膜30为阻挡层，进行高能离子注入后，分别在体区预设区205A形成体区209A、在体区预设区205B形成体区209B、在体区预设区205C形成体区209C。然后刻蚀去除未被光刻胶覆盖的多晶硅薄膜后，得到由剩余多晶硅薄膜构成的多晶硅层303。此时，第二漂移区203A上的光刻胶701的侧壁与底 部的夹角α等于第一漂移区201B上的光刻胶503的侧壁与底部的夹角β。
虽然第二掺杂区203A的长度D1小于第一掺杂区201B的长度D2，在进行高能离子注入过程中，第二漂移区203A上的光刻胶701的缩胶量小于第一漂移区201B上的光刻胶703的缩胶量，但是，掩膜版60对应的掩膜设计图形中加入的尺寸偏差已经消除了缩胶量不同对高能离子注入后光刻胶的侧壁与底部夹角的影响。使得在体区209B中，光刻胶901下形成第一导电类型掺杂区的长度等于在光刻胶703下形成第一导电类型掺杂区的长度。对于不同电压档位的NLDMOS器件来说，虽然漂移区的尺寸不同，但是相邻漂移区之间的距离相同时，掺杂区之间的沟道长度也相同。
具体的，假设掩膜设计图形中与第一漂移区对应的第一设计图形的长度为M0，与第二漂移区对应的第二设计图形的长度为N0。首先，获取衬底上掺杂区中第一漂移区的长度为M1、第二漂移区的长度为N1、位于第一漂移区中体区的长度为M2、位于第二漂移区中体区的长度为N2。其次，根据第一设计图形的长度M0、第二设计图形的长度N0、第一漂移区的长度M1、第二漂移区的长度N1、第一漂移区中体区的长度M2、第二漂移区中体区的长度N2，将第一设计图形的长度调整为M和第二设计图形的长度调整为N，例如，将第一漂移区中体区的长度M2、第二漂移区中体区的长度N2和预设值之间的差值分别增加到第一设计图形和第二设计图形中，得到第一设计图形的长度M和第二设计图形的长度N；使得第一漂移区中体区的长度和第二漂移区中体区的长度均为预设值，再次，以第一设计图形的长度M和第二设计图形的长度N得到新的掩膜设计图形，然后根据新的掩膜设计图形制作新的掩膜版。再次，以新的掩膜版形成位于多晶硅薄膜上的光刻胶图形，此时，第一漂移区上的光刻胶的侧壁与底部之间的夹角等于第二漂移区上的光刻胶的侧壁与底部之间的夹角。
参见图10，分别刻蚀形成多晶硅层后16V、18V、24V、32V NLDMOS器件的剖面示意图，其中，间距是指漂移区长度与相邻漂移区之间距离之和。由图可知，未根据漂移区的长度调整掩膜版设计图形的尺寸偏差时，相邻漂移区上的光刻胶之间的尺寸(Top CD)随漂移区的长度的增加(半导体器件的电压增减)而增大，即器件的沟道长度随漂移区的长度的增加而增大。根据漂移区的长度调整掩膜版设计图形的尺寸偏差后，相邻漂移区上的光刻胶之间的尺寸(Top CD)在预设范围内，不随漂移区的长度的变化(半导体器件的电压变化)而改变，即器件的沟道长度不变，并且漂移区上的光刻胶的侧壁与底部之间的夹角基本不变。
在其中一个实施例中，根据第一漂移区和第二漂移区的长度调整掩膜设计图形的尺寸偏差后，得到新的掩膜设计图形的步骤是通过光学邻近效应矫正的方式实现的。
在其中一个实施例中，体区的上表面的长度大于体区的下表面的长度，即体区为自上而下上宽狭窄的结构。
一种半导体器件，是通过上述任一项所述的制备方法制成的。
在其中一个实施例中，半导体器件包括横向扩散金属氧化物半导体器件。
上述半导体器件的制备方法，在多晶硅薄膜上形成光刻胶覆盖在第一漂移区和第二漂移区上的多晶硅薄膜，且露出位于第一漂移区和第二漂移区之间的体区预设区上的多晶硅薄膜的光刻胶图形后，通过高能离子注入在体区预设区形成第一导电类型的体区，与先刻蚀去除体区预设区上的多晶硅薄膜后进行高能离子注入相比，避免了因刻蚀导致覆盖在第一漂移区和第二漂移区上的光刻胶的厚度变薄，在不影响光刻胶对高能离子注入中注入离子的阻挡效果的情况下，需要进一步增加光刻胶的厚度，从而增加半导体器件的制备成本、增加工艺难度的问题；同时避免了光刻胶因刻蚀过程中的高温而发生形貌变化，进而对高能离子注入效果产生影响的问题。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种半导体器件的制备方法，其特征在于，包括：
    提供第一导电类型的衬底；
    在所述衬底上形成第二导电类型的掺杂区，所述掺杂区包括相邻的第一漂移区和第二漂移区，所述第二导电类型和所述第一导电类型相反；
    在所述衬底上形成多晶硅薄膜，所述多晶硅薄膜覆盖在所述掺杂区上；
    在所述多晶硅薄膜上形成光刻胶图形，所述光刻胶图形中的光刻胶覆盖在所述第一漂移区和第二漂移区上，且露出位于第一漂移区和第二漂移区之间的体区预设区上的多晶硅薄膜；
    进行高能离子注入，在所述体区预设区形成第一导电类型的体区，所述体区的上表面与所述掺杂区的上表面齐平，且所述体区的下表面不高于所述掺杂区的下表面。
  2. 根据权利要求1所述的制备方法，其特征在于，所述在所述衬底上形成第二导电类型的掺杂区的步骤包括：
    进行第二导电类型离子注入，在所述衬底上形成掺杂区；
    其中，所述掺杂区包括第一漂移区、第二漂移区、以及位于第一漂移区和第二漂移区之间的体区预设区。
  3. 根据权利要求1所述的制备方法，其特征在于，在所述多晶硅薄膜上形成光刻胶图形的步骤包括：
    在所述多晶硅薄膜上形成I线光刻胶图形，所述光刻胶图形的厚度大于或等于1.6微米且小于或等于2.5微米。
  4. 根据权利要求1所述的制备方法，其特征在于，所述进行高能离子注入的步骤包括：
    进行注入能量大于或等于500千电子伏且小于或等于800千电子伏的高能离子注入。
  5. 根据权利要求1所述的制备方法，其特征在于，所述在所述多晶硅薄膜上形成光刻胶图形的步骤包括：
    根据第一漂移区和第二漂移区的长度调整掩膜设计图形的尺寸偏差后，得到新的掩膜设计图形，其中，所述长度的方向为第一漂移区和第二漂移区的连线方向；
    根据所述新的掩膜设计图形制作掩膜版；
    使用所述掩膜版在所述多晶硅薄膜上形成新的光刻胶图形；
    其中，进行高能离子注入步骤后，所述新的光刻胶图形中位于第一漂移区和第二漂移区上的光刻胶的倾角相同，所述倾角是指光刻胶的侧壁与底部之间的夹角。
  6. 根据权利要求5所述的制备方法，其特征在于，所述根据第一漂移区和第二漂移区的 长度调整掩膜设计图形的尺寸偏差后，得到新的掩膜设计图形的步骤是通过光学邻近效应矫正的方式实现的。
  7. 根据权利要求1所述的制备方法，其特征在于，所述进行高能离子注入之后还包括：
    进行刻蚀工艺，去除所述体区预设区上的多晶硅薄膜，得到由剩余多晶硅薄膜构成的多晶硅层。
  8. 根据权利要求5所述的制备方法，其特征在于，体区的上表面的长度大于体区的下表面的长度。
  9. 一种半导体器件，其特征在于，所述半导体器件是通过权利要求1-8任一项所述的制备方法制成的。
  10. 根据权利要求9所述的半导体器件，其特征在于，所述半导体器件包括横向扩散金属氧化物半导体器件。
PCT/CN2021/108670 2020-12-23 2021-07-27 半导体器件及其制备方法 WO2022134571A1 (zh)

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