CN104412220B - 时钟域之间传输数据信号的系统和方法 - Google Patents
时钟域之间传输数据信号的系统和方法 Download PDFInfo
- Publication number
- CN104412220B CN104412220B CN201380034624.9A CN201380034624A CN104412220B CN 104412220 B CN104412220 B CN 104412220B CN 201380034624 A CN201380034624 A CN 201380034624A CN 104412220 B CN104412220 B CN 104412220B
- Authority
- CN
- China
- Prior art keywords
- clock
- clock domain
- detection
- input signal
- domain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1211426.0 | 2012-06-27 | ||
| GB1211426.0A GB2503474B (en) | 2012-06-27 | 2012-06-27 | Data transfer between clock domains |
| PCT/GB2013/051607 WO2014001764A1 (en) | 2012-06-27 | 2013-06-20 | Data transfer between clock domains |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104412220A CN104412220A (zh) | 2015-03-11 |
| CN104412220B true CN104412220B (zh) | 2018-08-28 |
Family
ID=46704316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201380034624.9A Expired - Fee Related CN104412220B (zh) | 2012-06-27 | 2013-06-20 | 时钟域之间传输数据信号的系统和方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US10114407B2 (https=) |
| EP (1) | EP2847666B1 (https=) |
| JP (1) | JP6356669B2 (https=) |
| KR (1) | KR20150037898A (https=) |
| CN (1) | CN104412220B (https=) |
| GB (1) | GB2503474B (https=) |
| TW (1) | TWI585570B (https=) |
| WO (1) | WO2014001764A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110502066B (zh) * | 2019-08-15 | 2021-03-02 | Oppo广东移动通信有限公司 | 时钟切换装置、方法及电子设备 |
| CN112036103B (zh) * | 2020-09-01 | 2024-03-08 | 深圳市傲立电子有限公司 | 一种从快时钟域跨慢时钟域处理多比特数据的装置及方法 |
| CN117561489A (zh) * | 2021-06-22 | 2024-02-13 | 谷歌有限责任公司 | 配置和状态寄存器的独立计时 |
| CN114185396B (zh) * | 2021-07-19 | 2026-03-17 | 芯华章科技股份有限公司 | 设计的时钟域转换方法、验证系统及存储介质 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1717643A (zh) * | 2002-11-28 | 2006-01-04 | 印芬龙科技股份有限公司 | 时钟同步电路 |
| EP1433059B1 (en) * | 2001-08-03 | 2007-05-23 | Altera Corporation | Clock loss detection circuit and corresponding method |
| CN101063894A (zh) * | 2006-06-13 | 2007-10-31 | 威盛电子股份有限公司 | 动态同步化处理器时钟与总线时钟前缘的方法与系统 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5987081A (en) * | 1997-06-27 | 1999-11-16 | Sun Microsystems, Inc. | Method and apparatus for a testable high frequency synchronizer |
| JP3560793B2 (ja) | 1997-11-27 | 2004-09-02 | 株式会社東芝 | データ転送方法 |
| US6549593B1 (en) * | 1999-07-19 | 2003-04-15 | Thomson Licensing S.A. | Interface apparatus for interfacing data to a plurality of different clock domains |
| US7085952B2 (en) * | 2001-09-14 | 2006-08-01 | Medtronic, Inc. | Method and apparatus for writing data between fast and slow clock domains |
| US7161999B2 (en) * | 2002-01-02 | 2007-01-09 | Intel Corporation | Synchronizing data or signal transfer across clocked logic domains |
| US7562244B2 (en) * | 2003-05-09 | 2009-07-14 | Koninklijke Philips Electronics N.V. | Method for data signal transfer across different clock-domains |
| US6949955B2 (en) * | 2003-11-24 | 2005-09-27 | Intel Corporation | Synchronizing signals between clock domains |
| JP4983349B2 (ja) * | 2007-04-04 | 2012-07-25 | セイコーエプソン株式会社 | クロック監視回路及びルビジウム原子発振器 |
| WO2008129364A1 (en) * | 2007-04-23 | 2008-10-30 | Nokia Corporation | Transferring data between asynchronous clock domains |
| US7733130B2 (en) * | 2008-03-06 | 2010-06-08 | Oracle America, Inc. | Skew tolerant communication between ratioed synchronous clocks |
| TWI443521B (zh) * | 2010-03-26 | 2014-07-01 | Nuvoton Technology Corp | 匯流排介面、時脈控制裝置,以及時脈頻率控制方法 |
| TWI417703B (zh) * | 2010-07-22 | 2013-12-01 | Genesys Logic Inc | 相容於通用序列匯流排協定之時脈同步方法 |
-
2012
- 2012-06-27 GB GB1211426.0A patent/GB2503474B/en not_active Expired - Fee Related
-
2013
- 2013-06-18 TW TW102121536A patent/TWI585570B/zh not_active IP Right Cessation
- 2013-06-20 KR KR20157002115A patent/KR20150037898A/ko not_active Withdrawn
- 2013-06-20 WO PCT/GB2013/051607 patent/WO2014001764A1/en not_active Ceased
- 2013-06-20 US US14/410,655 patent/US10114407B2/en active Active
- 2013-06-20 EP EP13735363.7A patent/EP2847666B1/en active Active
- 2013-06-20 JP JP2015519326A patent/JP6356669B2/ja not_active Expired - Fee Related
- 2013-06-20 CN CN201380034624.9A patent/CN104412220B/zh not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1433059B1 (en) * | 2001-08-03 | 2007-05-23 | Altera Corporation | Clock loss detection circuit and corresponding method |
| CN1717643A (zh) * | 2002-11-28 | 2006-01-04 | 印芬龙科技股份有限公司 | 时钟同步电路 |
| CN101063894A (zh) * | 2006-06-13 | 2007-10-31 | 威盛电子股份有限公司 | 动态同步化处理器时钟与总线时钟前缘的方法与系统 |
Also Published As
| Publication number | Publication date |
|---|---|
| GB201211426D0 (en) | 2012-08-08 |
| US10114407B2 (en) | 2018-10-30 |
| US20150177776A1 (en) | 2015-06-25 |
| JP2015527639A (ja) | 2015-09-17 |
| EP2847666B1 (en) | 2019-08-21 |
| TW201403289A (zh) | 2014-01-16 |
| JP6356669B2 (ja) | 2018-07-11 |
| CN104412220A (zh) | 2015-03-11 |
| EP2847666A1 (en) | 2015-03-18 |
| GB2503474A (en) | 2014-01-01 |
| WO2014001764A1 (en) | 2014-01-03 |
| TWI585570B (zh) | 2017-06-01 |
| GB2503474B (en) | 2016-06-29 |
| KR20150037898A (ko) | 2015-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6822478B2 (en) | Data-driven clock gating for a sequential data-capture device | |
| CN106487372B (zh) | 包括单线接口的装置和具有该装置的数据处理系统 | |
| CN101135921B (zh) | 多时钟切换装置及其切换方法 | |
| US7809972B2 (en) | Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain | |
| US20090150706A1 (en) | Wrapper circuit for globally asynchronous locally synchronous system and method for operating the same | |
| CN101405939A (zh) | 极低功耗的伪同步小尺寸寄存器设计及其实现方法 | |
| CN104850524A (zh) | 一种跨时钟域的ahb总线桥接方法和装置 | |
| CN104412220B (zh) | 时钟域之间传输数据信号的系统和方法 | |
| CN111949069B (zh) | 用于异步数据传送的电路 | |
| CN104412222B (zh) | 用于时钟域之间数据传输的设备 | |
| US7639764B2 (en) | Method and apparatus for synchronizing data between different clock domains in a memory controller | |
| CN114691583B (zh) | 用于将源同步数据路径与未知时钟相位对接的数据桥 | |
| KR101034338B1 (ko) | 데이터 전송회로 | |
| CN107533533A (zh) | 集成电路之间的通信 | |
| JP7692309B2 (ja) | ラッチ回路装置及びポートサンプリングシステム | |
| US11907008B2 (en) | Communication apparatus and control method thereof | |
| JPH11242651A (ja) | インターフェース |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180828 |