JP6356669B2 - クロック・ドメイン間のデータ転送 - Google Patents
クロック・ドメイン間のデータ転送 Download PDFInfo
- Publication number
- JP6356669B2 JP6356669B2 JP2015519326A JP2015519326A JP6356669B2 JP 6356669 B2 JP6356669 B2 JP 6356669B2 JP 2015519326 A JP2015519326 A JP 2015519326A JP 2015519326 A JP2015519326 A JP 2015519326A JP 6356669 B2 JP6356669 B2 JP 6356669B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- clock domain
- input signal
- domain
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1211426.0 | 2012-06-27 | ||
| GB1211426.0A GB2503474B (en) | 2012-06-27 | 2012-06-27 | Data transfer between clock domains |
| PCT/GB2013/051607 WO2014001764A1 (en) | 2012-06-27 | 2013-06-20 | Data transfer between clock domains |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015527639A JP2015527639A (ja) | 2015-09-17 |
| JP2015527639A5 JP2015527639A5 (https=) | 2016-08-12 |
| JP6356669B2 true JP6356669B2 (ja) | 2018-07-11 |
Family
ID=46704316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015519326A Expired - Fee Related JP6356669B2 (ja) | 2012-06-27 | 2013-06-20 | クロック・ドメイン間のデータ転送 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US10114407B2 (https=) |
| EP (1) | EP2847666B1 (https=) |
| JP (1) | JP6356669B2 (https=) |
| KR (1) | KR20150037898A (https=) |
| CN (1) | CN104412220B (https=) |
| GB (1) | GB2503474B (https=) |
| TW (1) | TWI585570B (https=) |
| WO (1) | WO2014001764A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110502066B (zh) * | 2019-08-15 | 2021-03-02 | Oppo广东移动通信有限公司 | 时钟切换装置、方法及电子设备 |
| CN112036103B (zh) * | 2020-09-01 | 2024-03-08 | 深圳市傲立电子有限公司 | 一种从快时钟域跨慢时钟域处理多比特数据的装置及方法 |
| CN117561489A (zh) * | 2021-06-22 | 2024-02-13 | 谷歌有限责任公司 | 配置和状态寄存器的独立计时 |
| CN114185396B (zh) * | 2021-07-19 | 2026-03-17 | 芯华章科技股份有限公司 | 设计的时钟域转换方法、验证系统及存储介质 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5987081A (en) * | 1997-06-27 | 1999-11-16 | Sun Microsystems, Inc. | Method and apparatus for a testable high frequency synchronizer |
| JP3560793B2 (ja) | 1997-11-27 | 2004-09-02 | 株式会社東芝 | データ転送方法 |
| US6549593B1 (en) * | 1999-07-19 | 2003-04-15 | Thomson Licensing S.A. | Interface apparatus for interfacing data to a plurality of different clock domains |
| JP4009592B2 (ja) * | 2001-08-03 | 2007-11-14 | アルテラ コーポレイション | クロックロス検出およびスイッチオーバー回路 |
| US7085952B2 (en) * | 2001-09-14 | 2006-08-01 | Medtronic, Inc. | Method and apparatus for writing data between fast and slow clock domains |
| US7161999B2 (en) * | 2002-01-02 | 2007-01-09 | Intel Corporation | Synchronizing data or signal transfer across clocked logic domains |
| DE10255685B3 (de) * | 2002-11-28 | 2004-07-29 | Infineon Technologies Ag | Taktsynchronisationsschaltung |
| US7562244B2 (en) * | 2003-05-09 | 2009-07-14 | Koninklijke Philips Electronics N.V. | Method for data signal transfer across different clock-domains |
| US6949955B2 (en) * | 2003-11-24 | 2005-09-27 | Intel Corporation | Synchronizing signals between clock domains |
| US7496779B2 (en) * | 2006-06-13 | 2009-02-24 | Via Technologies, Inc. | Dynamically synchronizing a processor clock with the leading edge of a bus clock |
| JP4983349B2 (ja) * | 2007-04-04 | 2012-07-25 | セイコーエプソン株式会社 | クロック監視回路及びルビジウム原子発振器 |
| WO2008129364A1 (en) * | 2007-04-23 | 2008-10-30 | Nokia Corporation | Transferring data between asynchronous clock domains |
| US7733130B2 (en) * | 2008-03-06 | 2010-06-08 | Oracle America, Inc. | Skew tolerant communication between ratioed synchronous clocks |
| TWI443521B (zh) * | 2010-03-26 | 2014-07-01 | Nuvoton Technology Corp | 匯流排介面、時脈控制裝置,以及時脈頻率控制方法 |
| TWI417703B (zh) * | 2010-07-22 | 2013-12-01 | Genesys Logic Inc | 相容於通用序列匯流排協定之時脈同步方法 |
-
2012
- 2012-06-27 GB GB1211426.0A patent/GB2503474B/en not_active Expired - Fee Related
-
2013
- 2013-06-18 TW TW102121536A patent/TWI585570B/zh not_active IP Right Cessation
- 2013-06-20 KR KR20157002115A patent/KR20150037898A/ko not_active Withdrawn
- 2013-06-20 WO PCT/GB2013/051607 patent/WO2014001764A1/en not_active Ceased
- 2013-06-20 US US14/410,655 patent/US10114407B2/en active Active
- 2013-06-20 EP EP13735363.7A patent/EP2847666B1/en active Active
- 2013-06-20 JP JP2015519326A patent/JP6356669B2/ja not_active Expired - Fee Related
- 2013-06-20 CN CN201380034624.9A patent/CN104412220B/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| GB201211426D0 (en) | 2012-08-08 |
| US10114407B2 (en) | 2018-10-30 |
| US20150177776A1 (en) | 2015-06-25 |
| CN104412220B (zh) | 2018-08-28 |
| JP2015527639A (ja) | 2015-09-17 |
| EP2847666B1 (en) | 2019-08-21 |
| TW201403289A (zh) | 2014-01-16 |
| CN104412220A (zh) | 2015-03-11 |
| EP2847666A1 (en) | 2015-03-18 |
| GB2503474A (en) | 2014-01-01 |
| WO2014001764A1 (en) | 2014-01-03 |
| TWI585570B (zh) | 2017-06-01 |
| GB2503474B (en) | 2016-06-29 |
| KR20150037898A (ko) | 2015-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8214668B2 (en) | Synchronizing circuit | |
| EP1381930B1 (en) | Synchronous receiver with digital locked loop (dll) and clock detection | |
| US8375239B2 (en) | Clock control signal generation circuit, clock selector, and data processing device | |
| JP6356669B2 (ja) | クロック・ドメイン間のデータ転送 | |
| JP2011095978A (ja) | バスシステム及びバス制御方法 | |
| CN101063894B (zh) | 动态同步化处理器时钟与总线时钟前缘的方法与系统 | |
| US20090150706A1 (en) | Wrapper circuit for globally asynchronous locally synchronous system and method for operating the same | |
| CN101135921A (zh) | 多时钟切换装置及其切换方法 | |
| JP6192065B2 (ja) | クロック・ドメイン間のデータ転送 | |
| US7639764B2 (en) | Method and apparatus for synchronizing data between different clock domains in a memory controller | |
| US8630382B2 (en) | Asynchronous data recovery methods and apparatus | |
| US7386750B2 (en) | Reduced bus turnaround time in a multiprocessor architecture | |
| JP2015527639A5 (https=) | ||
| US7966468B1 (en) | Apparatus, system, and method for fast read request transfer through clock domains | |
| US11321265B2 (en) | Asynchronous communication | |
| JP4962497B2 (ja) | クロック監視回路、情報処理装置およびクロック監視方法 | |
| US12135577B2 (en) | Low power and high speed scan dump | |
| JP2001273199A (ja) | シリアルインターフェイス |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160620 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160620 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170308 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170328 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20170620 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170828 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20171017 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20180117 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180316 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180529 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180614 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6356669 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |