KR20150037898A - 클록 도메인 간의 데이터 전송 - Google Patents

클록 도메인 간의 데이터 전송 Download PDF

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Publication number
KR20150037898A
KR20150037898A KR20157002115A KR20157002115A KR20150037898A KR 20150037898 A KR20150037898 A KR 20150037898A KR 20157002115 A KR20157002115 A KR 20157002115A KR 20157002115 A KR20157002115 A KR 20157002115A KR 20150037898 A KR20150037898 A KR 20150037898A
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KR
South Korea
Prior art keywords
clock
clock domain
domain
checking
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR20157002115A
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English (en)
Korean (ko)
Inventor
마르쿠스 바카 제르토에
아르네 반비크 베나스
Original Assignee
노르딕 세미컨덕터 에이에스에이
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 노르딕 세미컨덕터 에이에스에이 filed Critical 노르딕 세미컨덕터 에이에스에이
Publication of KR20150037898A publication Critical patent/KR20150037898A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Manipulation Of Pulses (AREA)
KR20157002115A 2012-06-27 2013-06-20 클록 도메인 간의 데이터 전송 Withdrawn KR20150037898A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB1211426.0 2012-06-27
GB1211426.0A GB2503474B (en) 2012-06-27 2012-06-27 Data transfer between clock domains
PCT/GB2013/051607 WO2014001764A1 (en) 2012-06-27 2013-06-20 Data transfer between clock domains

Publications (1)

Publication Number Publication Date
KR20150037898A true KR20150037898A (ko) 2015-04-08

Family

ID=46704316

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20157002115A Withdrawn KR20150037898A (ko) 2012-06-27 2013-06-20 클록 도메인 간의 데이터 전송

Country Status (8)

Country Link
US (1) US10114407B2 (https=)
EP (1) EP2847666B1 (https=)
JP (1) JP6356669B2 (https=)
KR (1) KR20150037898A (https=)
CN (1) CN104412220B (https=)
GB (1) GB2503474B (https=)
TW (1) TWI585570B (https=)
WO (1) WO2014001764A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110502066B (zh) * 2019-08-15 2021-03-02 Oppo广东移动通信有限公司 时钟切换装置、方法及电子设备
CN112036103B (zh) * 2020-09-01 2024-03-08 深圳市傲立电子有限公司 一种从快时钟域跨慢时钟域处理多比特数据的装置及方法
CN117561489A (zh) * 2021-06-22 2024-02-13 谷歌有限责任公司 配置和状态寄存器的独立计时
CN114185396B (zh) * 2021-07-19 2026-03-17 芯华章科技股份有限公司 设计的时钟域转换方法、验证系统及存储介质

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5987081A (en) * 1997-06-27 1999-11-16 Sun Microsystems, Inc. Method and apparatus for a testable high frequency synchronizer
JP3560793B2 (ja) 1997-11-27 2004-09-02 株式会社東芝 データ転送方法
US6549593B1 (en) * 1999-07-19 2003-04-15 Thomson Licensing S.A. Interface apparatus for interfacing data to a plurality of different clock domains
JP4009592B2 (ja) * 2001-08-03 2007-11-14 アルテラ コーポレイション クロックロス検出およびスイッチオーバー回路
US7085952B2 (en) * 2001-09-14 2006-08-01 Medtronic, Inc. Method and apparatus for writing data between fast and slow clock domains
US7161999B2 (en) * 2002-01-02 2007-01-09 Intel Corporation Synchronizing data or signal transfer across clocked logic domains
DE10255685B3 (de) * 2002-11-28 2004-07-29 Infineon Technologies Ag Taktsynchronisationsschaltung
US7562244B2 (en) * 2003-05-09 2009-07-14 Koninklijke Philips Electronics N.V. Method for data signal transfer across different clock-domains
US6949955B2 (en) * 2003-11-24 2005-09-27 Intel Corporation Synchronizing signals between clock domains
US7496779B2 (en) * 2006-06-13 2009-02-24 Via Technologies, Inc. Dynamically synchronizing a processor clock with the leading edge of a bus clock
JP4983349B2 (ja) * 2007-04-04 2012-07-25 セイコーエプソン株式会社 クロック監視回路及びルビジウム原子発振器
WO2008129364A1 (en) * 2007-04-23 2008-10-30 Nokia Corporation Transferring data between asynchronous clock domains
US7733130B2 (en) * 2008-03-06 2010-06-08 Oracle America, Inc. Skew tolerant communication between ratioed synchronous clocks
TWI443521B (zh) * 2010-03-26 2014-07-01 Nuvoton Technology Corp 匯流排介面、時脈控制裝置，以及時脈頻率控制方法
TWI417703B (zh) * 2010-07-22 2013-12-01 Genesys Logic Inc 相容於通用序列匯流排協定之時脈同步方法

Also Published As

Publication number Publication date
GB201211426D0 (en) 2012-08-08
US10114407B2 (en) 2018-10-30
US20150177776A1 (en) 2015-06-25
CN104412220B (zh) 2018-08-28
JP2015527639A (ja) 2015-09-17
EP2847666B1 (en) 2019-08-21
TW201403289A (zh) 2014-01-16
JP6356669B2 (ja) 2018-07-11
CN104412220A (zh) 2015-03-11
EP2847666A1 (en) 2015-03-18
GB2503474A (en) 2014-01-01
WO2014001764A1 (en) 2014-01-03
TWI585570B (zh) 2017-06-01
GB2503474B (en) 2016-06-29

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20150126

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid