CN104347406A - 双极晶体管、半导体装置以及双极晶体管的制造方法 - Google Patents

双极晶体管、半导体装置以及双极晶体管的制造方法 Download PDF

Info

Publication number
CN104347406A
CN104347406A CN201410369333.1A CN201410369333A CN104347406A CN 104347406 A CN104347406 A CN 104347406A CN 201410369333 A CN201410369333 A CN 201410369333A CN 104347406 A CN104347406 A CN 104347406A
Authority
CN
China
Prior art keywords
layer
side direction
collector layer
base
short side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410369333.1A
Other languages
English (en)
Other versions
CN104347406B (zh
Inventor
佐佐木健次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of CN104347406A publication Critical patent/CN104347406A/zh
Application granted granted Critical
Publication of CN104347406B publication Critical patent/CN104347406B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H01L2223/6655—Matching arrangements, e.g. arrangement of inductive and capacitive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

即使在集电极层的短边方向沿着结晶方位[011]的情况下，也能抑制基极布线的断线。本发明的双极晶体管(10)包括：俯视时具有长边方向及短边方向的集电极层(16)，该集电极层(16)的短边方向沿着结晶方位[011]，且与短边方向正交的截面形状为倒台面型，与长边方向正交的截面形状为正台面型；形成于集电极层(16)上的基极层(20)；形成于基极层(20)上的基极电极(22)；以及与基极电极(22)相连接，俯视时从集电极层(16)的短边方向的端部向集电极层(16)的外部引出的基极布线(22B)。

Description

双极晶体管、半导体装置以及双极晶体管的制造方法
技术领域
本发明涉及双极晶体管、半导体装置以及双极晶体管的制造方法。
背景技术
以往，尝试在基板上具有集电极层、基极层、发射极层的双极晶体管的开发。
专利文献1中揭示了如下双极晶体管：连接与基极层相接的基极电极的基极布线在俯视时从长方形的集电极层的长边方向的端部引出。
现有技术文献
专利文献
专利文献1：日本专利特开2004-327904号公报
发明内容
发明所要解决的技术问题
然而，在专利文献1所记载的双极晶体管中，对集电极层进行湿法蚀刻，因此依赖于集电极层的结晶方位产生蚀刻的各向异性。其结果，集电极层的与结晶方位[011]正交的截面形状为倒台面型，沿着结晶方位[011]的截面形状为正台面型。
这里，由于基极布线从集电极层的长边方向的端部引出，因此在集电极层的短边方向沿着结晶方位[011]的情况下，基极布线从倒台面型的集电极层的端部向集电极层的外部引出，由此可能由于台面的段差而导致断线。
本发明的一个目的在于，即使在集电极层的短边方向沿着结晶方位[011]的情况下，也能抑制基极布线的断线。
解决技术问题所采用的技术方案
本发明的一个侧面所涉及的双极晶体管包括：俯视时具有长边方向及短边方向的集电极层，所述集电极层的所述短边方向沿着结晶方位[011]，且与所述短边方向正交的截面形状为倒台面型，与所述长边方向正交的截面形状为正台面型；形成于所述集电极层上的基极层；形成于所述基极层上的基极电极；以及与所述基极电极相连接，俯视时从所述集电极层的所述短边方向的端部向所述集电极层的外部引出的基极布线。
发明效果
根据本发明，即使在集电极层的短边方向沿着结晶方位[011]的情况下，也能抑制基极布线的断线。
附图说明
图1是作为本发明实施方式1所涉及的双极晶体管的一个示例的HBT的俯视图。
图2是图1的A-A剖视图。
图3是图1的B-B剖视图。
图4是图1的C-C剖视图。
图5是图1的D-D剖视图。
图6是作为本发明实施方式2所涉及的双极晶体管的一个示例的HBT的俯视图。
图7是本发明实施方式3所涉及的半导体装置的俯视图。
图8是本发明实施方式4所涉及的半导体装置的俯视图。
图9是本发明实施方式5所涉及的半导体装置的俯视图。
图10是应用实施方式1所涉及的基极布线的引出方法的BiFET的剖视图。
具体实施方式
下面，参照附图说明本发明的实施方式。然而，以下说明的实施方式仅是示例，并不意图排除以下未示出的各种变形、技术的应用。即，本发明在不脱离本发明的要点的范围内可以进行各种变形来实施(对各实施例进行组合等)。在下面的附图的记载中，对同一或者类似的部分标注同一或者类似的标记来表示。附图是示意性图，实际的尺寸、比率等并不一定一致。在各附图之间也包含有彼此尺寸关系、比率不同的部分。
(实施方式1)
本发明实施方式1所涉及的双极晶体管主要在基板上包括集电极层、基极层、以及发射极层。本发明的实施方式1作为晶体管，举出了集电极层与基极层、以及基极层与发射极层的至少一方进行异质结而构成的异质结双极晶体管(以下称为“HBT(Heterojunction Bipolar Transistor)”)的一个示例。
<结构>
首先，对实施方式1所涉及的HBT的结构进行说明。图1是作为本发明实施方式1所涉及的双极晶体管的一个示例的HBT10的俯视图。图2是图1的A-A剖视图。图3是图1的B-B剖视图。图4是图1的C-C剖视图。图5是图1的D-D剖视图。
本实施方式的HBT10形成于基板，例如板状的化合物半导体基板12上。
对于化合物半导体基板12的材料并未作特别限定，例如可举出具有结晶结构的材料。作为具有结晶结构的材料可举出GaAs、Si、InP、Sic、GaN等。并且，在其中，优选为作为主要成分含有与InP等相比廉价且容易大口径化的GaAs或者Si。另外，“主要成分”是指作为主要成分的材料占某个基板或者某个层整体的比例在80质量％以上。本实施方式中，化合物半导体基板12例如由GaAs构成。图1等中作为GaAs的一部分结晶方位示出了结晶方位[011]、结晶方位[010]、以及结晶方位[01-1]。
HBT10包括子集电极层14、集电极层16、集电极电极18、基极层20、基极电极22、发射极层24、以及发射极电极26。
子集电极层14形成于化合物半导体基板12的局部表面上。对于子集电极层14的材料并未作特别限定，例如可举出具有结晶结构的材料。作为结晶结构，优选为闪锌矿型结晶结构。本实施方式中，子集电极层14作为主要成分含有例如与化合物半导体基板12相同的材料的n型GaAs(Si浓度5×1018cm-3)。另外，子集电极层14的GaAs的结晶方位例如与化合物半导体基板12的GaAs的结晶方位相一致。
子集电极层14俯视时的形状例如呈凸形状(参照图1)。该子集电极层14的突起方向与子集电极层14的结晶方位[01-1]大致平行(以下，将“大致平行”称为“沿着”。)。此外，子集电极层14中，与其结晶方位[011]正交的截面形状呈倒台面型(参照图2、图3)、沿着结晶方位[011]的截面形状呈正台面型(参照图4、图5)。换言之，子集电极层14的突起方向的两侧面为倒台面，与突起方向正交的宽度方向的两侧面为正台面。此外，子集电极层14的厚度例如大约为0.5μm。
另外，上述“正台面型”是指上方(相对于化合物半导体基板12的子集电极层14方向)较窄的梯形，上述“倒台面型”是指上方较宽的梯形。上述“正台面”是指斜面与上部平坦面构成钝角的该斜面，上述“倒台面”是指斜面与上部平坦部构成锐角的该斜面。上述“大致平行”是指与作为平行对象的方向(例如上述结晶方位[01-1])构成的角度为0度±20度。更具体而言，本实施方式中，子集电极层14的突起方向与子集电极层14的结晶方位[01-1]平行(上述角度为0度)。子集电极层14的欧姆电阻下降，并与集电极层16一起起到集电极的作用。
集电极层16在子集电极层14上形成于子集电极层14的宽度方向的中央部(参照图1、图2)。对于该集电极层16的材料并未作特别限定，例如可举出具有结晶结构的材料。作为结晶结构，优选为闪锌矿型结晶结构。本实施方式中，集电极层16作为主要成分含有例如与子集电极层14相同的材料的GaAs。另外，集电极层16的GaAs的结晶方位例如与化合物半导体基板12的GaAs的结晶方位相一致。
作为集电极层16的主要成分的GaAs与以往所使用的秩序化InGaP相比，热传导率较好，因此具有提高向集电极层16一侧进行散热的散热性、改善在高温动作或者高输出动作下的晶体管特性的效果。
另外，含有GaAs的集电极层16整体可以是n型半导体，也可以是p型半导体。在集电极层16是n型半导体的情况下，HBT10为npn结。在集电极层16是p型半导体的情况下，HBT10为pnp结。其中，由于GaAs的空穴迁移率与电子迁移率相比非常低(电子迁移率大约为0.85m2/(Vs)、空穴迁移率大约为0.04m2/(Vs))，因此从频率特性较好的观点来看相比pnp结优选为n型半导体。下面，本实施方式中，假设集电极层16是n型半导体。另外，由于集电极层16为n型，因此集电极层16中掺杂有Si、S、Se、Te、Sn等掺杂物。另外，由于集电极层16为p型，因此向集电极层16中掺杂C、Mg、Be、Zn、Cd等掺杂物。
集电极层16俯视时的形状在一个方向上较长例如呈长方形(参照图1)。该长方形(集电极层16)的长边方向沿着集电极层16的结晶方位[01-1]。集电极层16的短边方向沿着集电极层16的结晶方位[011]。此外，集电极层16中，从其结晶方位[011]观察到的形状呈倒台面型(参照图2)、从与结晶方位[011]正交的[01-1]观察到的形状呈正台面型(参照图5)。换言之，与集电极层16的短边方向正交的截面形状为倒台面型，与集电极层16的长边方向正交的截面形状为正台面型。进一步换言之，集电极层16的长边方向的两侧面为倒台面，集电极层16的短边方向的两侧面为正台面。此外，集电极层16的厚度例如大约为0.5μm以上1.5μm以下。
在子集电极层14上夹着集电极层16、在子集电极层14的宽度方向的两端部分别形成有(一对)集电极电极18(参照图1)。
一对集电极电极18的俯视形状例如分别为长方形。该长方形(集电极电极18)的长边方向沿着集电极层16的结晶方位[01-1]。对于集电极电极18的材料并未作特别限定，例如为Ti/Pt、WSi、Pt/Ti/Au或者AuGe/Ni/Au等。集电极电极18的材料优选为AuGe/Ni/Au。另外，俯视时，一对集电极电极18相比集电极层16更向集电极层16的结晶方位[01-1]一侧后退。换言之，集电极层16相对于一对集电极电极18向子集电极层14的突起方向突出。
一对集电极电极18经由各接触孔18A与集电极布线18B相连接。集电极布线18B经由其上层的接触孔19A进一步与上层的集电极收集布线19B相连接。
接触孔18A例如以与集电极布线18B相同的材料构成。接触孔18A的侧面外周例如被未图示的绝缘体的保护膜所包围。
集电极布线18B俯视时的形状例如呈凹形状(参照图1)。该凹形状的凹陷部分向子集电极层14的突起部分侧开口。该凹陷部分包围位于子集电极层14的宽度方向的中央部的基极层20、发射极层24等的一部分。
基极层20形成于集电极层16上(参照图1、图2)。对于基极层20的材料并未作特别限定，例如可举出具有结晶结构的材料。作为结晶结构，优选为闪锌矿型结晶结构。本实施方式中，基极层20作为主要成分含有例如与子集电极层14及集电极层16相同的材料的GaAs。另外，基极层20的GaAs的结晶方位例如与化合物半导体基板12的GaAs的结晶方位相一致。
作为基极层20的主要成分的GaAs可以是n型半导体，也可以是p型半导体。本实施方式中，由于集电极层16为n型半导体，因此基极层20的GaAs为p型半导体。
基极层20俯视时的形状在一个方向上较长例如呈长方形(参照图1)。该长方形(基极层20)的长边方向沿着基极层20的结晶方位[01-1]。该基极层20的短边方向沿着基极层20的结晶方位[011]。此外，基极层20中，从其结晶方位[011]观察到的形状呈倒台面型(参照图2)、从与结晶方位[011]正交的[01-1]观察到的形状呈正台面型(参照图5)。换言之，与基极层20的短边方向正交的截面形状为倒台面型，与基极层20的长边方向正交的截面形状为正台面型。进一步换言之，基极层20的长边方向的两侧面为倒台面，基极层20的短边方向的两侧面为正台面。此外，基极层20的厚度例如大约为0.05μm以上0.15μm以下。
基极电极22形成于基极层20上(参照图2、图5)。该基极电极22俯视时的形状例如呈凹形状(参照图1)。该凹形状的凹陷部分从基极层20的结晶方位[01-1]观察时开口(凹陷)。此外，该凹陷部分包围发射极层24等。对于基极电极22的材料并未作特别限定，例如为Ti/Pt、WSi、Pt/Ti/Au或者AuGe/Ni/Au等。基极电极22的材料优选为Pt/Ti/Au。
此外，该基极电极22经由接触孔22A与基极布线22B相连接。
接触孔22A例如以与基极布线22B相同的材料构成。接触孔22A的侧面外周例如被未图示的绝缘体的保护膜所包围。
基极布线22B俯视时的形状例如呈L字形(参照图1)。L字形(基极布线22B)的一个端部与基极电极22相连接。然后，基极布线22B从与基极电极22的连接区域开始，从基极层20及集电极层16的短边方向的端部引出至子集电极层14的外侧(参照图1、图5)。更具体而言，本实施方式中，基极布线22B从集电极层16的短边方向、换言之沿着集电极层16的结晶方位[011](与集电极层16的结晶方位[011]平行地)笔直引出。其结果，基极布线22B跨越基极层20、集电极层16及子集电极层14各自的正台面、即侧面。
基极布线22B在引出至子集电极层14的外侧之后，例如弯曲成直角，并沿着集电极层16的长边方向延伸。然后，作为延伸目的地的基极布线22B的另一个端部经由未图示的基极收集布线与金属焊盘等相连接。
发射极层24形成于基极层20上(参照图2)。该发射极层24呈一个方向上较长的例如长方形(参照图1)。该发射极层24的长边方向沿着基极层20的结晶方位[01-1]。
对于发射极层24的材料，只要是半导体即可，并不作特别限定。其中，本实施方式中，发射极层24与基极层20为异质结，因此发射极层24优选为由以与基极层20的主要成分晶格匹配的材料为主要成分的半导体来构成。具体而言，在基极层20以AlyGa1-yAs或者GaAs为主要成分的情况下，优选为由以InGaP或者AlyGa1-yAs为主要成分的半导体来构成。
发射极电极26形成于发射极层24上(参照图2)。对于发射极电极26的材料并未作特别限定，例如为Ti/Pt、WSi、AuGe/Ni/Au等。
此外，该发射极电极26经由接触孔26A与发射极布线26B相连接。发射极布线26B经由其上层的接触孔28A进一步与上层的发射极收集布线28B相连接。
接触孔26A例如以与发射极布线26B相同的材料构成。接触孔26A的侧面外周例如被未图示的绝缘体的保护膜所包围。
发射极布线26B俯视时的形状例如呈长方形(参照图1)。发射极布线26B的长边方向沿着基极层20的结晶方位[01-1]。
接触孔28A例如以与发射极收集布线28B相同的材料构成。接触孔28A的侧面外周例如被未图示的绝缘体的保护膜所包围。
发射极收集布线28B俯视时的形状例如呈长方形(参照图1)。发射极收集布线28B的长边方向沿着基极层20的结晶方位[011]。
<制造方法>
接着，对实施方式1所涉及的HBT10的制造方法的概要进行说明。
在化合物半导体基板12上例如利用有机金属气相沉积(MOCVD：MetalOrganic Chemical Vapor Deposition)法等依次形成子集电极层14、集电极层16、基极层20、以及发射极层24(参照图2)。
接着，利用光刻工序将发射极电极26蒸镀到发射极层24上。
对未被发射极电极26覆盖的发射极层24进行蚀刻，直至基极层20露出为止。然后，在露出后的基极层20上蒸镀基极电极22。
接着，对基极层20以及其下层的集电极层16进行湿法蚀刻，直至子集电极层14露出为止。并且，对子集电极层14进行湿法蚀刻。在对基极层20及集电极层16进行蚀刻时，以各个短边方向沿着结晶方位[011](全部均为相同方向)的方式决定各个短边方向与长边方向并进行湿法蚀刻。由于该蚀刻是湿法蚀刻，因此依赖于基极层20、集电极层16、子集电极层14的结晶方位产生蚀刻的各向异性(蚀刻的速度不同)。其结果，基极层20、集电极层16、子集电极层14从结晶方位[011]观察时的形状为倒台面型，从与结晶方位[011]正交的方向观察时的形状为正台面型。
接着，利用剥离法在子集电极层14上夹着集电极层16、在子集电极层14的宽度方向的两端部形成一对集电极电极18。
接下来，从化合物半导体基板12的形成有子集电极层14等各层的一侧开始，利用等离子体CVD等形成例如SiN膜等保护膜。
接着，对形成的保护膜进行干蚀刻，使得集电极电极18、基极电极22、发射极电极26中的至少各自的局部露出。
在露出的集电极电极18、基极电极22、发射极电极26上经由接触孔18A、22A、26A使用溅射法、蒸镀法等物理气相蒸镀法与剥离法形成所对应的集电极布线18B、基极布线22B、发射极布线26B。此处，基极布线22B以从集电极层16的短边方向的端部引出的方式形成。
接下来，从化合物半导体基板12的形成有子集电极层14等各层的一侧开始，利用MOCVD等形成例如SiN膜等保护膜。
接着，对形成的保护膜进行干蚀刻，使得集电极布线18B、基极布线22B、发射极布线26B中的至少各自的局部露出。
接着，为了平坦化而涂布聚酰亚胺膜。接着，蚀刻对上述保护膜进行蚀刻后的部位上的聚酰亚胺膜，使得集电极布线18B、基极布线22B、发射极布线26B中的至少各自的局部露出。
在露出的集电极布线18B、基极布线22B、发射极布线26B上经由接触孔19A、28A等使用溅射法、蒸镀法等物理气相蒸镀法与剥离法形成所对应的集电极收集布线19B、基极收集布线(未图示)、发射极收集布线28B。
经过以上制造工序，制造图1～图5所示的HBT10。
<作用>
以上，根据本实施方式的HBT10，具有集电极层16及基极布线22B，该集电极层16的短边方向沿着集电极层16的结晶方位[011]，与短边方向正交的截面形状为倒台面型，与长边方向正交的截面形状为正台面型，该基极布线22B从该集电极层16的短边方向的端部向集电极层16的外部引出。其结果，基极布线22B跨越作为集电极层16的正台面的侧面。因而，即使在集电极层16的短边方向沿着其结晶方位[011]的情况下，与跨越作为集电极层16的倒台面的侧面的情况相比，能抑制基极布线22B的断线。
根据本实施方式的HBT10，基极层20也同样，其短边方向沿着上述结晶方位[011]，与短边方向正交的截面形状为倒台面型，与长边方向正交的截面形状为正台面型。
其结果，基极布线22B跨越作为基极层20的正台面的侧面。因而，即使在基极层20的短边方向沿着其结晶方位[011]的情况下，与跨越作为基极层20的倒台面的侧面的情况相比，仍能抑制基极布线22B的断线。
根据本实施方式的HBT10，还具有子集电极层14，该子集电极层14形成在化合物半导体基板12与集电极层16之间，具有与集电极层16相同的结晶方位，且其与集电极层16的短边方向正交的截面形状为倒台面型，与集电极层16的长边方向正交的截面形状为正台面型。
其结果，基极布线22B跨越作为子集电极层14的正台面的侧面。因而，与跨越作为子集电极层14的倒台面的侧面的情况相比，能抑制基极布线22B的断线。
根据本实施方式的HBT10，化合物半导体基板12包含GaAs基板。在选择GaAs基板作为化合物半导体基板12情况下，与InP等相比廉价并易于大口径化。
(实施方式2)
接着，对本发明的实施方式2所涉及的HBT进行说明。
本实施方式2所涉及的HBT与实施方式1相比，基极布线的引出方法不同。其它的结构与实施方式1相同。
图6是作为本发明实施方式2所涉及的双极晶体管的一个示例的HBT40的俯视图。
如图6所示，HBT40具有经由接触孔22A与基极电极22相连的基极布线42。该基极布线42从集电极层的短边方向的端部引出。其结果，基极布线42跨越作为基极层20、集电极层16及子集电极层14各自的正台面的侧面。更具体而言，基极布线42具有第一部分42A、第二部分42B以及第三部分42C。
第一部分42A是存在于基极层20上，并与基极电极22相连的部分。该第一部分42A的形状呈大致长方形。第一部分42A的长边方向沿着集电极层16的结晶方位[011]。该第一部分42A的一个端部与第二部分42B的一个端部相连。
第二部分42B是基极布线42从基极层20上引出至子集电极层14的外侧为止的部分。该第二部分42B从集电极层16的短边方向的端部引出，但对于该端部倾斜地笔直引出。该引出目的地的第二部分42B的另一个端部与第三部分42C的一个端部相连接。
第三部分42C存在于化合物半导体基板12上，形状呈大致长方形。第三部分42C的长边方向沿着集电极层16的结晶方位[01-1]。该第三部分42C的另一个端部与未图示的基极收集布线相连接。另外，从抑制基极布线42的剥落的观点来看，位于第二部分42B与第三部分42C的边界附近的角部优选为进行倒角后的角部。
以上，根据本实施方式2所涉及的HBT40，俯视时基极布线42的第二部分42B相对于集电极层16的短边方向的端部倾斜地被引出，因此即使在制造时集电极层16等的正台面附近的第二部分42B的厚度与其它部位相比较薄的情况下，相比于与集电极层16的短边方向平行地引出的情况，仍能增大正台面附近的第二部分42B的宽度。由此，在基极布线42中，能使集电极层16等的正台面附近的截面积与其它部位的截面积更靠近，能进一步抑制基极布线42的断线。
(实施方式3)
接着，对本发明的实施方式3所涉及的半导体装置进行说明。
图7是本发明实施方式3所涉及的半导体装置50的俯视图。
本实施方式3所涉及的半导体装置50至少具有一个实施方式1所说明的HBT10，并且至少具有一个HBT60，该HBT60与HBT10的基极布线的引出方法不同。
HBT60包括子集电极层62、集电极层64、集电极电极66、基极层68、基极电极70、发射极层72、以及发射极电极74。HBT60具有集电极布线76、发射极布线78、基极布线80。
集电极层64与基极层68作为主要成分含有例如GaAs。此外，集电极层64与基极层68的形状例如为长方形。集电极层64与基极层68的长边方向沿着各自的结晶方位[011]，与短边方向正交的截面形状为倒台面型，与长边方向正交的截面形状为正台面型。同样，子集电极层62的与集电极层64的短边方向正交的截面形状也为倒台面型，与集电极层64的长边方向正交的截面形状也为正台面型。
基极布线80俯视时的形状为例如大致呈T字形。基极布线80的直线部分经由接触孔80A与基极电极70相连接。
然后，基极布线80从与基极电极22的连接区域开始，从基极层68及集电极层64的长边方向的端部引出至子集电极层62的外侧。更具体而言，本实施方式中，基极布线80从集电极层64的长边方向、换言之沿着集电极层64的结晶方位[011](与集电极层64的结晶方位[011]平行地)笔直引出。其结果，基极布线80跨越基极层68、集电极层64及子集电极层62各自的正台面、即侧面。
基极布线80在引出至子集电极层62的外侧之后，沿着集电极层64的长边方向延伸。然后，作为延伸目的地的基极布线80的另一个端部经由未图示的基极收集布线与金属焊盘等相连接。
关于HBT60的其它的结构，与实施方式1所说明的内容相同，因此省略说明。
以上，根据本实施方式3所涉及的半导体装置50，与仅排列HBT60的情况相比，增加了基极布线80的引出方向，能提高半导体装置50的布局的自由度。由此，例如能使半导体装置50小型化。
(实施方式4)
接着，对本发明的实施方式4所涉及的半导体装置进行说明。
图8是本发明实施方式4所涉及的半导体装置90的俯视图。
本实施方式4所涉及的半导体装置90至少具有2个与实施方式1所说明的HBT10相同的HBT100。
各HBT100中，共用子集电极层102、集电极层104、基极层106。各HBT100分别具有发射极层108与发射极电极110。此外，各HBT100分别具有集电极电极112A。与集电极电极112A相对的集电极电极112B为各HBT100所共用。各集电极电极112A和集电极电极112B通过集电极布线114相连接。各发射极电极110通过发射极布线116相连接。
集电极层104与基极层106作为主要成分含有例如GaAs。此外，集电极层104与基极层106的形状例如为长方形。集电极层104与基极层106的短边方向沿着各自的结晶方位[011]，与短边方向正交的截面形状为倒台面型，与长边方向正交的截面形状为正台面型。同样，子集电极层62的与集电极层104的短边方向正交的截面形状也为倒台面型，与集电极层104的长边方向正交的截面形状也为正台面型。
各HBT100中，共用基极电极118及基极布线120。
基极布线120从与基极电极118的连接区域开始，从基极层106及集电极层104的短边方向的端部引出至子集电极层102的外侧。其结果，基极布线120跨越基极层106、集电极层104及子集电极层102各自的正台面、即侧面。
基极布线120在引出至子集电极层102的外侧之后，沿着集电极层104的短边方向延伸。然后，作为延伸目的地的基极布线120的另一个端部经由未图示的基极收集布线与金属焊盘等相连接。
以上，根据本实施方式4所涉及的半导体装置90，由于使各HBT100的基极电极118及基极布线120共用化，因此抑制了基极层106与集电极层104的接触区域的扩大，抑制基极/集电极电容的增加，能实现将供电位置的平衡也考虑在内的布局。由此，例如能使半导体装置90小型化。
(实施方式5)
接着，对本发明的实施方式5所涉及的半导体装置进行说明。
图9是本发明实施方式5所涉及的半导体装置120的俯视图。
如图9所示，半导体装置120是RF功率放大器模块。在该半导体装置120中，具有至少一个实施方式1所说明的HBT10，并将用作为功率放大器。
半导体装置120除了HBT10以外，还具有HBT10的输入侧的匹配电路区域122、HBT10的输出侧的匹配电路区域124、以及控制芯片126。
以上，本实施方式5所涉及的半导体装置120中，通过将HBT10用作为功率放大器，能使RF功率放大器模块小型化。
(变形例)
此外，上述实施方式1～实施方式5用于使本发明变得容易理解，并非用于对本发明进行限定性解释。本发明能在不脱离其技术思想的情况下进行改变/改良，本发明还包含与其等同的内容。
例如，可以省略子集电极层14。同样，也可以省略发射极电极26。
在不使用化合物半导体基板12，而使用以Si为主要成分的半导体基板作为基板的情况下，可以在基板与子集电极层14之间插入一层以上的缓冲层。
如图10所示，在图5所示的结构中，也可以在化合物半导体基板12与子集电极层14之间添加源极/栅极的欧姆接触层132和FET部沟道层134，构成BiFET130。
对基极布线42的第二部分42B相对于集电极层16的短边方向的端部倾斜地笔直引出的情况进行了说明，但第二部分42B也可以为梯形，上底与第一部分42A相连，下底与第三部分42C相连。在该情况下，随着靠近引出目的地，基极布线42的宽度增大。
集电极电极18不一定需要位于两侧，也可以仅在一侧具有集电极电极18。标号说明
10、40、100   HBT(双极晶体管)
12   化合物半导体基板(基板)
14、62、102   子集电极层
16、64、104   集电极层
18、66、112A、112B   集电极电极
20、68、106   基极层
22、70、118   基极电极
22B、42、80、120   基极布线
50、90、120   半导体装置
80   基极布线

Claims (7)

1.一种双极晶体管，其特征在于，包括：
俯视时具有长边方向及短边方向的集电极层，所述集电极层的所述短边方向沿着结晶方位[011]，且与所述短边方向正交的截面形状为倒台面型，与所述长边方向正交的截面形状为正台面型；
形成于所述集电极层上的基极层；
形成于所述基极层上的基极电极；以及
与所述基极电极相连接、俯视时从所述集电极层的所述短边方向的端部向所述集电极层的外部引出的基极布线。
2.如权利要求1所述的双极晶体管，其特征在于，
所述基极布线俯视时相对于所述集电极层的短边方向倾斜地引出。
3.如权利要求1或2所述的双极晶体管，其特征在于，
所述基极层俯视时具有长边方向及短边方向，且与所述集电极层具有相同的结晶方位，所述基极层的所述短边方向沿着所述结晶方位[011]，与所述基极层的所述短边方向正交的截面的形状为倒台面型，与所述基极层的所述长边方向正交的截面的形状为正台面型。
4.如权利要求1至3中任一项所述的双极晶体管，其特征在于，
还具有形成于基板与所述集电极层之间、与所述集电极层具有相同的结晶方位的子集电极层，所述子集电极层的与所述集电极层的所述短边方向正交的截面形状为倒台面型，与所述集电极层的所述长边方向正交的截面形状为正台面型。
5.如权利要求4所述的双极晶体管，其特征在于，
所述基板是GaAs基板。
6.一种半导体装置，其特征在于，
该半导体装置具有权利要求1至5中任一项所述的双极晶体管即第一双极晶体管、以及第二双极晶体管，该第二双极晶体管包括：俯视时具有长边方向及短边方向的集电极层，所述集电极层的所述长边方向沿着结晶方位[011]，且与所述短边方向正交的截面形状为倒台面型，与所述长边方向正交的截面形状为正台面型；形成于所述集电极层上的基极层；形成于所述基极层上的基极电极；以及与所述基极电极相连接、俯视时从所述集电极层的所述长边方向的端部向所述集电极层的外部引出的基极布线。
7.一种双极晶体管的制造方法，其特征在于，包括如下工序：
在基板上形成集电极层及基极层的工序；
对所述集电极层和所述基极层进行湿法蚀刻，使得俯视时所述集电极层的短边方向沿着所述集电极层的结晶方位[011]的工序；
在所述基极层上形成基极电极的工序；以及
利用物理气相蒸镀法形成基极布线的工序，该基极布线与所述基极电极相连接，且俯视时从位于所述集电极层的短边方向的所述集电极层的端部向所述集电极层的外部引出。
CN201410369333.1A 2013-07-31 2014-07-30 双极晶体管、半导体装置以及双极晶体管的制造方法 Active CN104347406B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013159358A JP5907480B2 (ja) 2013-07-31 2013-07-31 バイポーラトランジスタ及び半導体装置並びにバイポーラトランジスタの製造方法
JP2013-159358 2013-07-31

Publications (2)

Publication Number Publication Date
CN104347406A true CN104347406A (zh) 2015-02-11
CN104347406B CN104347406B (zh) 2017-05-31

Family

ID=52426923

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410369333.1A Active CN104347406B (zh) 2013-07-31 2014-07-30 双极晶体管、半导体装置以及双极晶体管的制造方法

Country Status (4)

Country Link
US (4) US20150035121A1 (zh)
JP (1) JP5907480B2 (zh)
CN (1) CN104347406B (zh)
TW (1) TWI567983B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109390319A (zh) * 2017-08-09 2019-02-26 株式会社村田制作所 半导体装置
US11710735B2 (en) 2017-08-09 2023-07-25 Murata Manufacturing Co., Ltd. Semiconductor device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11239348B2 (en) * 2014-03-17 2022-02-01 Matthew H. Kim Wafer bonded GaN monolithic integrated circuits and methods of manufacture of wafer bonded GaN monolithic integrated circuits
JP2018026406A (ja) 2016-08-08 2018-02-15 株式会社村田製作所 ヘテロ接合バイポーラトランジスタ
US10109724B2 (en) * 2017-02-22 2018-10-23 Qualcomm Incorporated Heterojunction bipolar transistor unit cell and power stage for a power amplifier
JP2020102581A (ja) * 2018-12-25 2020-07-02 株式会社村田製作所 バイポーラトランジスタ

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010045619A1 (en) * 2000-03-30 2001-11-29 Ronald Dekker Semiconductor device and method of manufacturing same
JP2004221139A (ja) * 2003-01-09 2004-08-05 Sony Corp 半導体装置およびその製造方法
JP2004296542A (ja) * 2003-03-25 2004-10-21 Sumitomo Electric Ind Ltd ヘテロ接合バイポーラトランジスタおよびその製造方法
US20050017267A1 (en) * 2003-06-04 2005-01-27 Takeshi Kawasaki Hetero-bipolar transistor having the base interconnection provided on the normal mesa surface of the collector mesa
JP4224980B2 (ja) * 2002-04-16 2009-02-18 住友電気工業株式会社 バイポーラトランジスタ

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63287058A (ja) * 1987-05-19 1988-11-24 Sumitomo Electric Ind Ltd ヘテロ接合バイポ−ラトランジスタの製造方法
JP3278868B2 (ja) * 1991-08-20 2002-04-30 株式会社日立製作所 ヘテロ接合バイポーラトランジスタ
US5528189A (en) * 1993-12-21 1996-06-18 Texas Instruments Incorporated Noise performance of amplifiers
US5468659A (en) * 1994-03-10 1995-11-21 Hughes Aircraft Company Reduction of base-collector junction parasitic capacitance of heterojunction bipolar transistors
JPH08139101A (ja) * 1994-11-07 1996-05-31 Nippon Telegr & Teleph Corp <Ntt> ヘテロ接合バイポーラトランジスタ及びその製造方法
JP3345293B2 (ja) * 1997-02-27 2002-11-18 日本電信電話株式会社 ヘテロ接合型バイポーラトランジスタ
US5859447A (en) * 1997-05-09 1999-01-12 Yang; Edward S. Heterojunction bipolar transistor having heterostructure ballasting emitter
JP4288852B2 (ja) * 2000-12-27 2009-07-01 住友電気工業株式会社 バイポーラトランジスタの製造方法
JP3565274B2 (ja) * 2002-02-25 2004-09-15 住友電気工業株式会社 バイポーラトランジスタ
JP3846347B2 (ja) * 2002-03-27 2006-11-15 住友電気工業株式会社 バイポーラトランジスタおよびその製造方法
JP3945303B2 (ja) * 2002-04-19 2007-07-18 住友電気工業株式会社 ヘテロ接合バイポーラトランジスタ
JP3843884B2 (ja) * 2002-04-23 2006-11-08 住友電気工業株式会社 バイポーラトランジスタの製造方法
JP3885658B2 (ja) * 2002-05-13 2007-02-21 住友電気工業株式会社 ヘテロ接合バイポーラトランジスタ
JP2004327904A (ja) 2003-04-28 2004-11-18 Renesas Technology Corp バイポーラトランジスタおよびその製造方法
US7449728B2 (en) * 2003-11-24 2008-11-11 Tri Quint Semiconductor, Inc. Monolithic integrated enhancement mode and depletion mode field effect transistors and method of making the same
US7015519B2 (en) * 2004-02-20 2006-03-21 Anadigics, Inc. Structures and methods for fabricating vertically integrated HBT/FET device
JP2006147911A (ja) * 2004-11-22 2006-06-08 Renesas Technology Corp 半導体装置、半導体装置の製造方法、および電子装置
US7829917B1 (en) * 2007-06-14 2010-11-09 Hrl Laboratories, Llc Layout for self-aligned emitter-base processing
JP2017220584A (ja) * 2016-06-08 2017-12-14 株式会社村田製作所 半導体装置及び電力増幅回路
US10367084B2 (en) * 2017-07-31 2019-07-30 Globalfoundries Inc. Cascode heterojunction bipolar transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010045619A1 (en) * 2000-03-30 2001-11-29 Ronald Dekker Semiconductor device and method of manufacturing same
JP4224980B2 (ja) * 2002-04-16 2009-02-18 住友電気工業株式会社 バイポーラトランジスタ
JP2004221139A (ja) * 2003-01-09 2004-08-05 Sony Corp 半導体装置およびその製造方法
JP2004296542A (ja) * 2003-03-25 2004-10-21 Sumitomo Electric Ind Ltd ヘテロ接合バイポーラトランジスタおよびその製造方法
US20050017267A1 (en) * 2003-06-04 2005-01-27 Takeshi Kawasaki Hetero-bipolar transistor having the base interconnection provided on the normal mesa surface of the collector mesa

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109390319A (zh) * 2017-08-09 2019-02-26 株式会社村田制作所 半导体装置
CN109390319B (zh) * 2017-08-09 2022-06-28 株式会社村田制作所 半导体装置
US11710735B2 (en) 2017-08-09 2023-07-25 Murata Manufacturing Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
TWI567983B (zh) 2017-01-21
US20170186671A1 (en) 2017-06-29
JP2015032623A (ja) 2015-02-16
US10468335B2 (en) 2019-11-05
US20160204235A1 (en) 2016-07-14
US9627503B2 (en) 2017-04-18
TW201505175A (zh) 2015-02-01
CN104347406B (zh) 2017-05-31
US20150035121A1 (en) 2015-02-05
US10236237B2 (en) 2019-03-19
US20190164868A1 (en) 2019-05-30
JP5907480B2 (ja) 2016-04-26

Similar Documents

Publication Publication Date Title
CN104347406A (zh) 双极晶体管、半导体装置以及双极晶体管的制造方法
CN105849873B (zh) 半导体装置
CN103872107B (zh) 异质结双极晶体管、使用其的功率放大器及其制造方法
US20060108665A1 (en) Semiconductor device, manufacturing method of the same, and electronic device
JP2008078486A (ja) 半導体素子
WO2014025722A2 (en) Method and system for gallium nitride electronic devices using engineered substrates
KR20030081094A (ko) 반도체장치와 그 제조방법 및 전력증폭기 모듈
JP4288852B2 (ja) バイポーラトランジスタの製造方法
US20080176391A1 (en) Method for manufacturing semiconductor device
TWI523219B (zh) 化合物半導體橫向ｐｎｐ雙極電晶體
US11728419B2 (en) High electron mobility transistor
JP2006185990A (ja) 半導体装置およびその製造方法ならびに電子装置
JP2006278544A (ja) 能動素子およびその製造方法
JP5035588B2 (ja) バイポーラトランジスタを有する半導体装置
CN108063162A (zh) 双极晶体管的制作方法
JP2006165248A (ja) 半導体装置およびその製造方法
US20090085162A1 (en) Semiconductor device and integrated semiconductor circuit device
KR102008460B1 (ko) 초정렬 바이폴라 트랜지스터의 제조방법
JP5783241B2 (ja) 半導体装置
JP2002151520A (ja) 半導体装置
CN109301062A (zh) 一种集成放大器件的霍尔器件及其制备方法
JP2002025937A (ja) 半導体装置
JP2002289831A (ja) 電極、半導体素子、接合型バイポーラトランジスタ及び接合型バイポーラトランジスタの製造方法
JP2012089868A (ja) 半導体装置およびそれを用いた無線通信機器
JPS58223371A (ja) シヨツトキバリアゲ−ト電界効果トランジスタ

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant