CN104335279B - 芯片间存储器接口结构 - Google Patents

芯片间存储器接口结构 Download PDF

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Publication number
CN104335279B
CN104335279B CN201380028442.0A CN201380028442A CN104335279B CN 104335279 B CN104335279 B CN 104335279B CN 201380028442 A CN201380028442 A CN 201380028442A CN 104335279 B CN104335279 B CN 104335279B
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China
Prior art keywords
memory
physical address
tube core
address space
data
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Chinese (zh)
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CN104335279A (zh
Inventor
J·徐
D·T·全
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201380028442.0A 2012-06-01 2013-05-31 芯片间存储器接口结构 Active CN104335279B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261654156P 2012-06-01 2012-06-01
US61/654,156 2012-06-01
US13/752,427 2013-01-29
US13/752,427 US9448947B2 (en) 2012-06-01 2013-01-29 Inter-chip memory interface structure
PCT/US2013/043714 WO2013181603A2 (en) 2012-06-01 2013-05-31 Inter-chip memory interface structure

Publications (2)

Publication Number Publication Date
CN104335279A CN104335279A (zh) 2015-02-04
CN104335279B true CN104335279B (zh) 2017-08-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380028442.0A Active CN104335279B (zh) 2012-06-01 2013-05-31 芯片间存储器接口结构

Country Status (7)

Country Link
US (1) US9448947B2 (OSRAM)
EP (1) EP2856466B1 (OSRAM)
JP (1) JP6105720B2 (OSRAM)
KR (1) KR101748329B1 (OSRAM)
CN (1) CN104335279B (OSRAM)
IN (1) IN2014MN02115A (OSRAM)
WO (1) WO2013181603A2 (OSRAM)

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KR102107147B1 (ko) * 2013-02-01 2020-05-26 삼성전자주식회사 패키지 온 패키지 장치
KR102144367B1 (ko) * 2013-10-22 2020-08-14 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US9570142B2 (en) * 2015-05-18 2017-02-14 Micron Technology, Inc. Apparatus having dice to perorm refresh operations
US20170118140A1 (en) * 2015-10-21 2017-04-27 Mediatek Inc. Network switch having identical dies and interconnection network packaged in same package
KR102755934B1 (ko) 2016-10-04 2025-01-17 삼성전자 주식회사 무선 통신 장치 및 그 제어 방법
KR102400101B1 (ko) * 2017-11-03 2022-05-19 삼성전자주식회사 Pop 반도체 패키지 및 그를 포함하는 전자 시스템
US10579557B2 (en) * 2018-01-16 2020-03-03 Advanced Micro Devices, Inc. Near-memory hardened compute blocks for configurable computing substrates
KR20190087893A (ko) 2018-01-17 2019-07-25 삼성전자주식회사 클럭을 공유하는 반도체 패키지 및 전자 시스템
KR102674550B1 (ko) 2019-10-07 2024-06-13 삼성전자주식회사 온-다이 미러링 기능을 갖는 메모리 칩 및 그것을 테스트하는 방법
US11797229B2 (en) 2020-07-02 2023-10-24 Micron Technology, Inc. Multiple register clock driver loaded memory subsystem

Citations (4)

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Publication number Priority date Publication date Assignee Title
CN101461007A (zh) * 2005-12-30 2009-06-17 美光科技公司 用于存储器堆叠系统和方法的可配置输入和输出
US20100082911A1 (en) * 2008-09-30 2010-04-01 Ripan Das Low power termination for memory modules
US20120051171A1 (en) * 2010-08-31 2012-03-01 Micron Technology, Inc. Channel skewing
US20120137090A1 (en) * 2010-11-29 2012-05-31 Sukalpa Biswas Programmable Interleave Select in Memory Controller

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US5945886A (en) * 1996-09-20 1999-08-31 Sldram, Inc. High-speed bus structure for printed circuit boards
JP2008140220A (ja) 2006-12-04 2008-06-19 Nec Corp 半導体装置
US8120958B2 (en) * 2007-12-24 2012-02-21 Qimonda Ag Multi-die memory, apparatus and multi-die memory stack
US7701251B1 (en) 2008-03-06 2010-04-20 Xilinx, Inc. Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package
US20100174858A1 (en) 2009-01-05 2010-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Extra high bandwidth memory die stack
US8683164B2 (en) 2009-02-04 2014-03-25 Micron Technology, Inc. Stacked-die memory systems and methods for training stacked-die memory systems
US8713248B2 (en) * 2009-06-02 2014-04-29 Nokia Corporation Memory device and method for dynamic random access memory having serial interface and integral instruction buffer
US8296526B2 (en) * 2009-06-17 2012-10-23 Mediatek, Inc. Shared memory having multiple access configurations
US8604593B2 (en) * 2009-10-19 2013-12-10 Mosaid Technologies Incorporated Reconfiguring through silicon vias in stacked multi-die packages
US8400808B2 (en) * 2010-12-16 2013-03-19 Micron Technology, Inc. Phase interpolators and push-pull buffers
JP2013058277A (ja) * 2011-09-07 2013-03-28 Renesas Electronics Corp 半導体装置
US20130159587A1 (en) * 2011-12-15 2013-06-20 Aaron Nygren Interconnect Redundancy for Multi-Interconnect Device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101461007A (zh) * 2005-12-30 2009-06-17 美光科技公司 用于存储器堆叠系统和方法的可配置输入和输出
US20100082911A1 (en) * 2008-09-30 2010-04-01 Ripan Das Low power termination for memory modules
US20120051171A1 (en) * 2010-08-31 2012-03-01 Micron Technology, Inc. Channel skewing
US20120137090A1 (en) * 2010-11-29 2012-05-31 Sukalpa Biswas Programmable Interleave Select in Memory Controller

Also Published As

Publication number Publication date
EP2856466B1 (en) 2018-10-24
WO2013181603A2 (en) 2013-12-05
KR20150016605A (ko) 2015-02-12
JP2015525398A (ja) 2015-09-03
JP6105720B2 (ja) 2017-03-29
US20130326188A1 (en) 2013-12-05
CN104335279A (zh) 2015-02-04
EP2856466A2 (en) 2015-04-08
KR101748329B1 (ko) 2017-06-16
US9448947B2 (en) 2016-09-20
WO2013181603A3 (en) 2014-02-27
IN2014MN02115A (OSRAM) 2015-09-11

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