CN104300069B - High voltage led chip and preparation method thereof - Google Patents
High voltage led chip and preparation method thereof Download PDFInfo
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- CN104300069B CN104300069B CN201410424182.5A CN201410424182A CN104300069B CN 104300069 B CN104300069 B CN 104300069B CN 201410424182 A CN201410424182 A CN 201410424182A CN 104300069 B CN104300069 B CN 104300069B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 60
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 56
- 230000004888 barrier function Effects 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 169
- 229910052718 tin Inorganic materials 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 20
- 239000000741 silica gel Substances 0.000 claims description 12
- 229910002027 silica gel Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 230000005496 eutectics Effects 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 238000005507 spraying Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 2
- 238000004080 punching Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 19
- 230000008569 process Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 239000006071 cream Substances 0.000 description 8
- 230000008020 evaporation Effects 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N 1,4a-dimethyl-7-propan-2-yl-2,3,4,4b,5,6,10,10a-octahydrophenanthrene-1-carboxylic acid Chemical compound C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- 238000000605 extraction Methods 0.000 description 1
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- 239000007792 gaseous phase Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- 229920005989 resin Polymers 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/56—Materials, e.g. epoxy or silicone resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
High voltage LED chip and preparation method thereof, the high voltage LED chip includes substrate and M chip for insulating each other independent on substrate surface, is formed at the reflecting layer on the p-type gallium nitride layer of each chip；The epitaxial layer of covering each chip and the insulating barrier of reflection layer surface；P lead electrodes, N leads electrode and PN lead connection electrodes；Planarization layer is covered on the surface of insulating layer on the surface of P leads electrode, PN leads connection electrode and N lead electrodes and between P leads electrode, PN leads connection electrode and N lead electrodes, on the planarization layer set and the N leads electrode contact hole in the N pads being connected with the N leads electrode and with the P leads electrode contact hole in the P pads being connected with the P leads electrode.
Description
Technical field
The invention belongs to semiconductor optoelectronic chip technology field, more particularly to a kind of high voltage LED chip and preparation method thereof.
Background technology
With the continuous improvement of LED (light emitting diode) luminous efficiency, LED turned into recent years most valued light source it
One.With the development of LED techniques, directly had been carried out using the LED of high drive.The efficiency of high-voltage LED is better than general tradition
Low-voltage LED, being mainly due to low current, multiunit design uniformly can open current spread, and high-voltage LED can be realized
Direct voltage drives, so as to save the cost of LED drivings.
Existing high voltage LED chip has that power increases, radiating is difficult and reliability is reduced, and is asked for these
Topic, industry has gone out further improvement to the structure of high voltage LED chip.For example, number of patent application is 201410123492.3
Chinese invention patent application discloses a kind of high voltage LED chip and preparation method thereof, and the LED chip includes multiple LED chip lists
Unit, sets cutting groove and is isolated between each LED core blade unit, each LED core blade unit includes an independent LED chip
Device, the LED chip device include set gradually Sapphire Substrate, n-GaN layers, multi-layer quantum well layer, p-GaN layer, n-GaN
N-type electrode is formed with layer, p-type electrode is formed with p-GaN layer, insulation fluorescence coating is coated with the top of epitaxial wafer, insulated glimmering
Photosphere is filled in cutting groove, will be only used in and expose with the n-type electrode and p-type electrode of external electrical connections.But it is still used
Traditional metal salient point heat conduction, the heat conduction of LED high-voltage chip and integrity problem are not still addressed.
For high voltage LED chip, heat dissipation problem is solved, must just increase chip cooling area, this can only pass through
Design on chip forms two big pads, is then welded by tin cream heat is diffused into substrate from pad.Due to high pressure
Chip is made up of multiple chips, and to form two big pads needs new method.Due to mutually in epitaxial layer between other chip
It is spaced, there is the step more than 7um between chip so that chip surface is not at peer-level line, this can be to reflow soldering process
Impact.Meanwhile, the heat that LED chip is produced when working can raise LED chip temperature, due to fixed high voltage LED chip
Heat-conducting substrate typically use FR4 wiring boards, aluminium base or copper-based PCB, the thermal expansion system of high voltage LED chip and heat-conducting substrate
The thermal stress that number is different and produces, may result in LED chip cracking or metal salient point is peeled off, influence high voltage LED chip
Luminous efficiency and its functional reliability.
The content of the invention
It is an object of the invention to provide a kind of with the own absorption inside thermal stress for producing, the height for improving product reliability
Pressure LED chip and preparation method thereof.
To achieve these goals, the present invention takes following technical solution：
High voltage LED chip, including substrate and M chip being mutually independent on the substrate surface, M >=2,
Described each chip includes the n type gallium nitride layer, luminescent layer and the p-type gallium nitride layer that are grown on successively on the substrate surface, institute
The epitaxial layer that n type gallium nitride layer, luminescent layer and p-type gallium nitride layer constitute chip is stated, on the p-type gallium nitride layer of each chip
It is formed with reflecting layer；The epitaxial layer of covering each chip and the insulating barrier of reflection layer surface, the insulating barrier is along chip week
Avris wall and substrate attaching；The P lead electrodes electrically connected with the reflecting layer of the first chip；With the n type gallium nitride layer electricity of M chips
The N lead electrodes of connection；The reflecting layer of the n type gallium nitride layer of the i-th chip and i+1 chip is electrically connected in series successively
PN lead connection electrodes, i=1 ..., M-1, the PN lead connection electrodes of the chip that each two is serially connected are mutually independent；
Planarization layer, the planarization layer is organosilicon glue-line, and planarization layer is covered in P leads electrode, PN leads connection electrode and N and draws
On surface of insulating layer on the surface of line electrode and between P leads electrode, PN leads connection electrode and N lead electrodes；It is deposited on
The N pads being connected on the planarization layer and with the N leads electrode；Be deposited on the planarization layer and with the P leads
The P pads of electrode connection.
High voltage LED chip of the invention, also includes：Through the epitaxial layer, expose the groove of the substrate surface, it is described
Be isolated for each chip by groove；P-type gallium nitride, luminescent layer through each chip is until the N electrode of n type gallium nitride layer surface
Hole；The insulating barrier fills the groove and N electrode hole, is formed with the insulating barrier of each chip and the reflection layer surface phase
P-type contact hole even and the N-type contact hole being connected with the n type gallium nitride layer surface；The P leads electrode deposition is in the first core
On the partial insulative layer on piece surface and in p-type contact hole, by the p-type contact hole on the first chip and the reflecting layer of the first chip
Electrical connection；The N leads electrode deposition is on the partial insulative layer of M chip surfaces and in N-type contact hole, by M chips
On the n type gallium nitride layer of N-type contact hole and M chips electrically connect；The PN leads connection electrode is deposited on adjacent chips
On partial insulative layer and in N-type contact hole, p-type contact hole；It is formed with the planarization layer and the N leads electricity on M chips
The N lead electrode contact holes of pole surface connection and the P lead electrode contacts being connected with the P lead electrode surfaces on the first chip
Hole；The N pads be deposited on the planarization layer and the N leads electrode contact hole in be connected with the N leads electrode；Institute
State P pads be deposited on the planarization layer and the P leads electrode contact hole in be connected with the P leads electrode.
Insulating barrier of the invention be aluminium nitride or silica or silicon nitride or alundum (Al2O3) or Bragg reflecting layer or
Organosilicon glue-line.
Planarization layer of the invention is organosilicon glue-line of the viscosity more than 400mPa.s, thickness more than 6um.
Tin paste layer is coated with N pads of the invention and P bond pad surfaces.
The thickness of tin paste layer of the invention is 50~100um.
Tin paste layer of the invention is made up of Sn, Ag, Cu, and wherein the mass percent of Sn is the mass percent of 96.5, Ag
It is 3.0, balance of Cu.
Eutectic layer is coated with N pads of the invention and P bond pad surfaces.
The thickness of eutectic layer of the invention is 4~20um.
Planarization layer of the invention is fitted along chip perimeter side wall with insulating barrier, each chip successively by the insulating barrier and
Planarization layer is fully wrapped around.
N pads of the invention are symmetrical with P pads, and the P pads and N pad thickness are 1um~2um, P pads and N
Interval >=150um between pad.
P pads of the invention and N pads are folded and formed by aluminium, nickel, titanium, platinum, layer gold.
The preparation method of high voltage LED chip, comprises the following steps：
Step one, offer substrate, grow n type gallium nitride layer on the substrate surface, are grown on n type gallium nitride layer and sent out
Photosphere, the growing P-type gallium nitride layer on luminescent layer, the n type gallium nitride layer, luminescent layer and p-type gallium nitride layer constitute each core
The epitaxial layer of piece；
Step 2, on p-type gallium nitride layer cover reflecting layer；
Step 3, groove is formed on epitaxial layer, the depth of groove to substrate surface, expose substrate；Formed and run through p-type nitrogen
Change gallium layer, luminescent layer until the N electrode hole of n type gallium nitride layer surface；
Step 4, the surface covering insulating barrier in epitaxial layer and reflecting layer, insulating barrier fill groove and N electrode hole simultaneously；
Step 5, in surface of insulating layer punching, etch with the p-type contact hole that is connected of reflection layer surface and with N-type nitridation
The connected N-type contact hole of gallium layer surface；
Step 6, on the insulating layer P lead electrode of the formation with wiring pattern, N leads electrode and PN leads connection electricity
Pole, deposits P lead electrodes, on M chip surfaces on the partial insulative layer on the first chip surface and in p-type contact hole
Partial insulative layer on and N-type contact hole in deposition N lead electrodes, on the partial insulative layer of adjacent chips and N-type connects
Deposition PN lead connection electrodes in contact hole, p-type contact hole, PN leads connection electrode successively by the n type gallium nitride layer of the i-th chip and
The reflecting layer of i+1 chip is electrically connected in series, i=1 ..., M, and the PN leads of the chip that wherein each two is serially connected connect
Receiving electrode is mutually independent；
Step 7, forms planarization layer, planarization layer covering P leads electrode, N leads electrode and PN lead connection electrodes
Surface and the surface of the insulating barrier between P leads electrode, N leads electrode and PN lead connection electrodes；
Step 8, it is lithographically formed the N lead electrodes that are connected with the N lead electrode surfaces on M chips in planarization layer and connects
Contact hole and the P lead electrode contacts hole being connected with the P lead electrode surfaces on the first chip；
Step 9, formation N pads on the planarization layer surface of part and in N lead electrode contacts hole, planarize in part
Form P pads in layer surface and in P lead electrode contacts hole, N pads by N lead electrode contact holes with and N lead electrode phases
Contact, P pads pass through P lead electrode contact holes and P lead contact electrodes.
The step of present invention forms the planarization layer is as follows：Spraying coating process is used to form thickness flat for 6~10um
Change layer, baked at a temperature of 110 DEG C 2 minutes, then expose, development, and toasted at a temperature of 180 DEG C and solidified for 2 hours,
Planarization layer is fitted along chip perimeter side wall with insulating barrier.
From above technical scheme, the present invention forms planarization layer using the organic silica gel for possessing certain elasticity, can
Absorption causes the thermal stress that inside of high-voltage chip is damaged, so that ensure the reliability of LED high-voltage chip operation, in preferred scheme,
Insulating barrier and planarization layer are fully wrapped around by each chip along chip perimeter side wall, not only help tin cream reflow soldering process, moreover it is possible to
Tin cream climbs tin so as to cause electric leakage or short circuit when preventing welding；P pads and N pads are symmetrical, upside-down mounting contact area big, upside-down mounting
Weldering alignment is easy, and low to circuit board layout precision prescribed, flip-chip bonding process is simple.
Brief description of the drawings
Fig. 1 is the structural representation of the embodiment of the present invention；
Fig. 2 a are the structural representation that embodiment of the present invention high voltage LED chip forms epitaxial layer；
Fig. 2 b are the structural representation that high voltage LED chip forms reflecting layer；
Fig. 2 c are the structural representation that high voltage LED chip forms groove and N electrode hole；
Fig. 2 d are the structural representation that high voltage LED chip forms insulating barrier；
Fig. 2 e are the structural representation that high voltage LED chip forms p-type contact hole and N-type contact hole；
Fig. 2 f are the structural representation that high voltage LED chip forms N leads electrode, PN leads connection electrode and P lead electrodes；
Fig. 2 g are the structural representation that high voltage LED chip forms planarization layer；
Fig. 2 h are the structural representation that high voltage LED chip forms N lead electrode contact holes and P lead electrode contacts hole；
Fig. 2 i are the structural representation that high voltage LED chip forms N pads and P pads；
Fig. 3 is the structural representation of the high voltage LED chip of another embodiment of the present invention；
Fig. 4 is the structural representation of the high voltage LED chip of further embodiment of this invention.
Specific embodiment of the invention is described in more detail below in conjunction with accompanying drawing.
Specific embodiment
As shown in figure 1, high voltage LED chip of the invention includes substrate 1 and is insulated each other on the surface of substrate 1
Independent M chip 10, M is the integer more than or equal to 2, and each chip 10 includes the N-type nitrogen being grown on successively on the surface of substrate 1
Change gallium layer 11, luminescent layer 12 and p-type gallium nitride layer 13, reflecting layer 15, n type gallium nitride layer 11, hair are covered on p-type gallium nitride layer 13
Photosphere 12 and p-type gallium nitride layer 13 constitute the epitaxial layer 2 of each chip.Each chip is kept apart (Fig. 2 c) by groove 3, groove 3
Depth to the surface of substrate 1.In the epitaxial layer 2 of each chip and the surface of reflecting layer 15 covering insulating barrier 16.Set on insulating barrier 16
Put the N leads electricity of the connection of n type gallium nitride layer 11 of the P leads electrode 31 and M chips being connected with the reflecting layer 15 of the first chip
Pole 32 and the PN lead connection electrodes that the n type gallium nitride layer of a chip is sequentially connected in series with the reflecting layer of an adjacent chip
33.On the surface of P leads electrode 31, PN leads connection electrode 33 and N leads electrode 32 and positioned at P leads electrode, PN leads
Planarization layer 22 is coated with the surface of insulating barrier 16 between connection electrode and N lead electrodes, is set on planarization layer 22
There are the N pads 26 being connected with N leads electrode 32 and the P pads 27 being connected with P leads electrode 31.In N pads 26 and P pads 27
Between can fill reflective insulant, the insulating materials for possessing reflecting properties is packed between N pads and P pads, such as aoxidize
Titanium, can not only avoid occurring short circuit phenomenon between N pads and P pads, and can improve the light extraction efficiency of chip.
With reference to Fig. 2 a to Fig. 2 i, the preparation method to embodiment of the present invention high voltage LED chip is illustrated, the preparation
Method is comprised the following steps：
Step one, as shown in Figure 2 a, there is provided substrate 1, the substrate 1 of the present embodiment is Sapphire Substrate, by MOCVD
(Metal-organic Chemical Vapor Deposition, metallo-organic compound chemical gaseous phase deposition) is in the table of substrate 1
Face growing epitaxial layers 2, the growth course of epitaxial layer 2 is followed successively by：In the superficial growth n type gallium nitride of substrate 1 layer 11, in N-type nitridation
Luminescent layer 12, the growing P-type gallium nitride layer 13 on luminescent layer 12 are grown on gallium layer 11；
Step 2, as shown in Figure 2 b, reflecting layer 15 cover using evaporation and photoetching process on p-type gallium nitride layer 13, this
The material in reflecting layer 15 can be aluminium, nickel, silver-colored or above-mentioned both alloys any；
Step 3, as shown in Figure 2 c, ICP etch process is used by epitaxial layer, and groove 3, ditch are formed on epitaxial layer
The depth of groove 3 to the surface of substrate 1, expose substrate 1, groove is set on epitaxial layer, form the epitaxial layer only each other
To M chips, M is the integer more than or equal to 2 to the first vertical chip；Each chip 10 is performed etching, with each chip 10
Surface is formed through p-type gallium nitride layer 13, luminescent layer 12 until the N electrode hole 4 on 11 surface of n type gallium nitride layer, N electrode hole 4
Quantity can be multiple and is uniformly distributed in chip surface；
Alternatively, deposited n-type electrode, N-type electrode material in the n type gallium nitride layer surface of each bottom of N electrode hole 4
Expect to be the alloy of aluminium, gold or both；
Step 4, as shown in Figure 2 d, by sputtering or PECVD (Plasma Enhanced Chemical Vapor
Deposition) technique covers insulating barrier 16 on the surface in epitaxial layer and reflecting layer, and insulating barrier 16 fills groove and N electrode simultaneously
Hole, insulating barrier is fully wrapped around by each chip along chip perimeter side wall and substrate attaching；The thickness of insulating layer be 1um~
2.5um, the material of insulating barrier can for aluminium nitride or silica or silicon nitride or alundum (Al2O3) or Bragg reflecting layer DBR or
Silica gel or resin or acrylic acid, Bragg reflecting layer are silica SiO2With titanium dioxide TiO2Multilayer alternating structure；It is preferred that
Ground, insulating layer material is organic silica gel, and organic silica gel possesses high filling micron order cavity ability, can effectively fill ditch in itself
Cavity left by groove 3 and N electrode hole 4, reduces the transmitting that such cavity is formed to light, improves chip light emitting efficiency and prevents
Chip chamber leaks electricity；
Step 5, as shown in Figure 2 e, is punched, using photoetching and etching technique on the surface of insulating barrier 16 on each chip respectively
P-type contact hole 5 and N-type contact hole 6 are etched, wherein, p-type contact hole 5 is connected with the surface of reflecting layer 15, the bottom of p-type contact hole 5
Expose reflecting layer 15, N-type contact hole 6 is connected with 11 surface of n type gallium nitride layer, and reflecting layer 11 is exposed in the bottom of N-type contact hole 6；
Step 6, as shown in figure 2f, forms the P with wiring pattern on insulating barrier 16 and draws by sputtering or evaporation process
Line electrode 31, N leads electrode 32 and PN leads connection electrode 33；Wherein, on the partial insulative layer 16 on the first chip surface
And deposition P leads electrode 31 in p-type contact hole, i.e., P leads electrode 31 is by the p-type contact hole and the first core on the first chip
The reflecting layer 15 of piece is electrically connected, and N leads electricity is deposited on the partial insulative layer 16 on M chip surfaces and in N-type contact hole
Pole 32, i.e. N leads electrode 32 are electrically connected by the N-type contact hole on M chips with the n type gallium nitride layer 11 of M chips, in phase
PN leads connection electrode 33 is deposited on the partial insulative layer 16 of adjacent chip and in N-type contact hole, p-type contact hole, PN leads connect
Be electrically connected in series in the reflecting layer of the n type gallium nitride layer of the i-th chip and i+1 chip successively by receiving electrode 33, i=1 ...,
The PN leads connection electrode 33 of the chip that M, wherein each two are serially connected is mutually independent；
Step 7, as shown in Figure 2 g, planarization layer 22, the covering P lead electrodes of planarization layer 22 is formed by spraying coating process
31st, the surface of N leads electrode 32 and PN leads connection electrode 33 and positioned at P leads electrode 31, N leads electrode 32 and PN leads
The surface of the insulating barrier 16 between connection electrode 33, planarization layer 22 is fitted along chip perimeter side wall with insulating barrier；This hair
The material of bright planarization layer 22 is organic silica gel, and thickness is 6~10um, in the present embodiment, forms organic using spraying coating process
Layer of silica gel --- planarization layer 22, bakes 2 minutes at a temperature of 110 DEG C, and the thickness of planarization layer 22 is 7.3um, is then exposed
(800mJ/cm2), TMAH develop (70sec, 3 times), and are toasted at a temperature of 180 DEG C and solidified for 2 hours；
Because planarization layer uses organic silica gel, organic silica gel is the material for not absorbing visible spectrum and possessing certain elasticity
Material, can absorb the thermal stress for causing inside of high-voltage chip to be damaged, so as to ensure the reliability of high voltage LED chip work；Using
With low solidification temperature (<200 DEG C) organic silica gel, it is adaptable to thermal Finite device；Because high-voltage LED device is by many
Individual integrated chip, each chip surface shoulder height difference is big, it is impossible to use direct solder reflow process, the present invention to use viscosity
Step flatening process is carried out more than the organic silica gel of 400mPa.s and thickness more than 6um so that put down on the surface of planarization layer 22
It is smooth, and planarization layer 22 fits along chip perimeter side wall with insulating barrier, each chip is fully wrapped around, not only help tin cream
Reflow soldering process, and tin cream climbs tin so as to cause electric leakage or short circuit when preventing welding；
Step 8, as shown in fig. 2h, in planarization layer 22 forms N lead electrode contacts hole 28 and P draws by photoetching process
Line electrode contact hole 29, wherein, N lead electrode contacts hole 28 is connected with the surface of N leads electrode 32 on M chips, P leads electricity
Pole contact hole 29 is connected with the surface of P leads electrode 31 on the first chip；N lead electrode contacts hole 28 and P lead electrode contacts
Hole 29 can be multiple；
Step 9, as shown in fig. 2i, using photoetching and the N pads 26 and P pads 27, N of evaporation coating technique manufacture mutually insulated
Pad 26 is covered on the surface of part planarization layer 22 and is filled in N lead electrode contact holes and P lead electrodes with P pads 27
In contact hole, N pads 26 by N lead electrode contact holes with and N leads electrode 32 be in contact, P pads 27 are by P lead electrodes
Contact hole 29 and P leads electrode 31 are in contact, and N pads 26 are symmetrical with P pads 27, and interval is more than between P pads and N pads
Or equal to 150um, because the surface of planarization layer 22 forms horizontal plane, therefore N pads 26 are highly consistent with both P pads 27,
It is easy to be fixed with pcb board and welds；Preferably, before evaporation N pads 26 with P pads 27, first carried out slightly on the surface of planarization layer 22
Roughening technique, beneficial to raising planarization layer 22 and N pads 26 and the bonding strength of P pads 27；Preferably, P pads and N pad thickness
It is 1um~2um, P pads and N pads are folded and formed by aluminium, nickel, titanium, platinum, layer gold, and aluminium produces good adhesion with planarization layer,
Titanium, platinum are barrier layer, have when gold and tin cream Reflow Soldering and soak (wetting) effect.
As shown in figure 3, as another embodiment of the present invention, by printing or steaming on N pads 26 and the surface of P pads 27
Depositing process covers tin paste layer 9, and the thickness of tin paste layer 9 is 50~100um, and tin paste layer 9 is made up of Sn, Ag, Cu, wherein the quality of Sn
Percentage is that the mass percent of 96.5, Ag is 3.0, balance of Cu.Because the tin cream material has less voidage, can be effective
Heat dissipation channel thermal resistance is reduced, and possesses extremely strong adhesion strength and conductive capability.And, the material that tin paste layer category is directly welded
Material, is conducive to simplifying encapsulation step, and form stress buffer between high-voltage chip and PCB substrate.
As shown in figure 4, as another embodiment of the present invention, evaporation process is passed through on N pads 26 and the surface of P pads 27
Covering eutectic layer 9 ', eutectic layer 9 ' is made up of Au and Sn, and wherein the mass percent of Au is that the mass percent of 80, Sn is
20, the thickness of eutectic layer 9 ' is 4~20um.
Planarization layer of the invention uses high-viscosity organosilicon glue, belongs to the high-insulativity material of low Young's modulus, fills up
Step ability so that the planarization layer surface in same level, in series connection P leads electrode, PN lead connection electrodes
During with N lead electrodes, the sandwich of P pads and N pad metals does not result in thermal expansion coefficient difference causes stress cracking；
And high-voltage chip surrounding side be flattened layer covering, high-voltage chip can be prevented to be welded to FR4 wiring boards, aluminium base or copper
During base circuit board, the situation generation of electric leakage or short circuit caused by tin is climbed because of tin cream.
The above embodiments are merely illustrative of the technical solutions of the present invention rather than its limitations, although with reference to above-described embodiment pair
The present invention has been described in detail, it should be understood by a person of ordinary skill in the art that still can be to of the invention specific
Implementation method is modified or equivalent, and without departing from any modification of spirit and scope of the invention or equivalent,
It all should cover among scope of the presently claimed invention.
Claims (10)
1. high voltage LED chip, including substrate and M chip being mutually independent on the substrate surface, M >=2, institute
Stating each chip includes the n type gallium nitride layer, luminescent layer and the p-type gallium nitride layer that are grown on successively on the substrate surface, the N
Type gallium nitride layer, luminescent layer and p-type gallium nitride layer constitute the epitaxial layer of chip, shape on the p-type gallium nitride layer of each chip
Into there is reflecting layer；
Characterized in that, also including：
The epitaxial layer of covering each chip and the insulating barrier of reflection layer surface, the insulating barrier is along chip perimeter side wall and lining
Fit at bottom；
The P lead electrodes electrically connected with the reflecting layer of the first chip；
The N lead electrodes electrically connected with the n type gallium nitride layer of M chips；
The PN leads that the reflecting layer of the n type gallium nitride layer of the i-th chip and i+1 chip is electrically connected in series are connected into electricity successively
Pole, i=1 ..., M-1, the PN lead connection electrodes of the chip that each two is serially connected are mutually independent；
Planarization layer, the planarization layer is organosilicon glue-line, and the organosilicon glue-line is less than 200 DEG C, glues using solidification temperature
Organic silica gel spraying of the degree more than 400mPa.s is formed, and the thickness of the organosilicon glue-line is 6~10 μm, and planarization layer is covered in
On the surface of P leads electrode, PN leads connection electrode and N lead electrodes and P leads electrode, PN leads connection electrode and N leads
On surface of insulating layer between electrode, the planarization layer is fitted along chip perimeter side wall with insulating barrier, each chip successively by
The insulating barrier and planarization layer are fully wrapped around；
The N pads for being deposited on the planarization layer and being connected with the N leads electrode；
The P pads for being deposited on the planarization layer and being connected with the P leads electrode.
2. high voltage LED chip as claimed in claim 1, it is characterised in that：Also include
Through the epitaxial layer, expose the groove of the substrate surface, be isolated for each chip by the groove；
P-type gallium nitride, luminescent layer through each chip is until the N electrode hole of n type gallium nitride layer surface；
The insulating barrier fills the groove and N electrode hole, is formed with the insulating barrier of each chip and the reflection layer surface
Connected p-type contact hole and the N-type contact hole being connected with the n type gallium nitride layer surface；
The P leads electrode deposition is on the partial insulative layer of the first chip surface and in p-type contact hole, by the first chip
P-type contact hole electrically connected with the reflecting layer of the first chip；
The N leads electrode deposition is on the partial insulative layer of M chip surfaces and in N-type contact hole, by M chips
N-type contact hole is electrically connected with the n type gallium nitride layer of M chips；
The PN leads connection electrode is deposited on the partial insulative layer of adjacent chips and N-type contact hole, p-type contact hole in；
Be formed with the planarization layer N lead electrode contact holes that are connected with the N lead electrode surfaces on M chips and with
The P lead electrode contacts hole of the P leads electrode surface connection on the first chip；
The N pads be deposited on the planarization layer and the N leads electrode contact hole in be connected with the N leads electrode；
The P pads be deposited on the planarization layer and the P leads electrode contact hole in be connected with the P leads electrode.
3. high voltage LED chip as claimed in claim 1, it is characterised in that：The insulating barrier be aluminium nitride or silica or
Silicon nitride or alundum (Al2O3) or Bragg reflecting layer or organosilicon glue-line.
4. high voltage LED chip as claimed in claim 1, it is characterised in that：Tin is coated with the N pads and P bond pad surfaces
Layer of paste or eutectic layer.
5. high voltage LED chip as claimed in claim 4, it is characterised in that：The thickness of the tin paste layer is 50~100um, or
The thickness of eutectic layer described in person is 4~20um.
6. the high voltage LED chip as described in claim 4 or 5, it is characterised in that：The tin paste layer is made up of Sn, Ag, Cu, its
The mass percent of middle Sn is 3.0, balance of Cu for the mass percent of 96.5, Ag.
7. high voltage LED chip as claimed in claim 1, it is characterised in that：The N pads are symmetrical with P pads, the P
Pad and N pad thickness are 1um~2um, interval >=150um between P pads and N pads.
8. the high voltage LED chip as described in claim 1 or 7, it is characterised in that：The P pads and N pads by aluminium, nickel, titanium,
Platinum, layer gold are folded to be formed.
9. the preparation method of high voltage LED chip, it is characterised in that comprise the following steps：
Step one, offer substrate, grow n type gallium nitride layer on the substrate surface, and growth lights on n type gallium nitride layer
Layer, the growing P-type gallium nitride layer on luminescent layer, the n type gallium nitride layer, luminescent layer and p-type gallium nitride layer constitute each chip
Epitaxial layer；
Step 2, on p-type gallium nitride layer cover reflecting layer；
Step 3, groove is formed on epitaxial layer, the depth of groove to substrate surface, expose substrate；Formed and run through p-type gallium nitride
Layer, luminescent layer are until the N electrode hole of n type gallium nitride layer surface；
Step 4, the surface covering insulating barrier in epitaxial layer and reflecting layer, insulating barrier fill groove and N electrode hole simultaneously；
Step 5, in surface of insulating layer punching, etch with the p-type contact hole that is connected of reflection layer surface and with n type gallium nitride layer
The connected N-type contact hole in surface；
Step 6, on the insulating layer P lead electrode of the formation with wiring pattern, N leads electrode and PN lead connection electrodes,
P lead electrodes, the portion on M chip surfaces are deposited on partial insulative layer on first chip surface and in p-type contact hole
Deposition N lead electrodes on point insulating barrier and in N-type contact hole, on the partial insulative layer of adjacent chips and N-type contact hole,
Deposition PN lead connection electrodes in p-type contact hole, PN leads connection electrode is successively by the n type gallium nitride layer and i+1 of the i-th chip
The reflecting layer of chip is electrically connected in series, i=1 ..., M, the PN lead connection electrodes of the chip that wherein each two is serially connected
It is mutually independent；
Step 7, forms planarization layer, the surface of planarization layer covering P leads electrode, N leads electrode and PN lead connection electrodes
And the surface of the insulating barrier between P leads electrode, N leads electrode and PN lead connection electrodes, the planarization
Layer is organosilicon glue-line, and the organosilicon glue-line is using solidification temperature less than 200 DEG C, organic silica gel of the viscosity more than 400mPa.s
Spraying is formed, and the thickness of the organosilicon glue-line is 6~10 μm, and the planarization layer is pasted along chip perimeter side wall and insulating barrier
Close, each chip is fully wrapped around by the insulating barrier and planarization layer successively；
Step 8, the N lead electrode contacts hole being connected with the N lead electrode surfaces on M chips is lithographically formed in planarization layer
And the P lead electrode contacts hole being connected with the P lead electrode surfaces on the first chip；
Step 9, formation N pads on the planarization layer surface of part and in N lead electrode contacts hole, in part planarization layer table
Form P pads on face and in P lead electrode contacts hole, N pads by N lead electrode contact holes with and N lead contact electrodes,
P pads pass through P lead electrode contact holes and P lead contact electrodes.
10. the preparation method of high voltage LED chip as claimed in claim 9, it is characterised in that：Form the step of the planarization layer
It is rapid as follows：
It is the planarization layer of 6~10um to use spraying coating process to form thickness, is baked at a temperature of 110 DEG C 2 minutes, then expose,
Development, and toast at a temperature of 180 DEG C and solidified for 2 hours, the planarization layer is along chip perimeter side wall and insulating barrier patch
Close.
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| CN106159075B (en) * | 2016-09-05 | 2018-11-27 | 江苏新广联半导体有限公司 | A kind of flip LED chips and production method with low thermal resistance insulation layer structure |
| CN106159056A (en) * | 2016-09-18 | 2016-11-23 | 佛山市国星半导体技术有限公司 | A kind of upside-down mounting high-voltage chip and preparation method thereof |
| KR20180073866A (en) * | 2016-12-23 | 2018-07-03 | 엘지이노텍 주식회사 | Semiconductor device |
| CN107170856A (en) * | 2017-04-25 | 2017-09-15 | 淮安澳洋顺昌光电技术有限公司 | The preparation method of upside-down mounting high voltage LED chip |
| CN107293623A (en) * | 2017-07-12 | 2017-10-24 | 厦门乾照光电股份有限公司 | A kind of LED chip and preparation method thereof |
| CN107946426B (en) * | 2017-12-20 | 2020-03-31 | 大连德豪光电科技有限公司 | LED chip manufacturing method and LED chip |
| US10269711B1 (en) * | 2018-03-16 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method for manufacturing the same |
| CN111128899B (en) * | 2018-10-31 | 2022-03-22 | 成都辰显光电有限公司 | Epitaxial substrate and method for manufacturing same |
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