CN104300069A - High voltage LED chip and manufacturing method thereof - Google Patents
High voltage LED chip and manufacturing method thereof Download PDFInfo
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- CN104300069A CN104300069A CN201410424182.5A CN201410424182A CN104300069A CN 104300069 A CN104300069 A CN 104300069A CN 201410424182 A CN201410424182 A CN 201410424182A CN 104300069 A CN104300069 A CN 104300069A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 3
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 64
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 130
- 230000004888 barrier function Effects 0.000 claims description 37
- 229910052718 tin Inorganic materials 0.000 claims description 28
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 238000002360 preparation method Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 7
- 230000005496 eutectics Effects 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical group [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 description 16
- 239000000741 silica gel Substances 0.000 description 9
- 229910002027 silica gel Inorganic materials 0.000 description 9
- 239000006071 cream Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 230000008020 evaporation Effects 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005476 soldering Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
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- 238000005520 cutting process Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N 1,4a-dimethyl-7-propan-2-yl-2,3,4,4b,5,6,10,10a-octahydrophenanthrene-1-carboxylic acid Chemical compound C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
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- 239000007792 gaseous phase Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/56—Materials, e.g. epoxy or silicone resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
The invention relates to a high voltage LED chip and a manufacturing method of the high voltage LED chip. The high voltage LED chip comprises a substrate, M chip bodies which are located on the surface of the substrate and insulated from and independent of one another, reflection layers formed on P-type gallium nitride layers of all the chip bodies, epitaxial layers covering all the chip bodies, insulating layers on the surfaces of the reflection layers, P lead electrodes, N lead electrodes and PN lead connecting electrodes. The surfaces of the P lead electrodes, the surfaces of the PN lead connecting electrodes and the surfaces of the N lead electrodes and the surfaces of the insulating layers between the P lead electrodes, the PN lead connecting electrodes and the N lead electrodes are covered with a planarization layer. N bonding pads which are located in N lead electrode contact holes and connected with the N lead electrodes, and P bonding pads which are located in P lead electrode contact holes and connected with the P lead electrodes are arranged on the planarization layer.
Description
Technical field
The invention belongs to semiconductor optoelectronic chip technology field, particularly relate to a kind of high voltage LED chip and preparation method thereof.
Background technology
Along with improving constantly of LED (light-emitting diode) luminous efficiency, LED has become one of the most valued light source in recent years.Along with the development of LED technique, the LED of high drive is directly adopted to realize.The efficiency of high-voltage LED is better than general conventional low LED, mainly can be opened by current spread uniformly owing to small area analysis, multiunit design, and high-voltage LED can realize direct voltage driving, thus saves the cost of LED driving.
Existing high voltage LED chip also exists the problem that power increases, heat radiation is difficult and reliability reduces, and for these problems, the structure of industry to high voltage LED chip has gone out further improvement.Such as, number of patent application be 201410123492.3 Chinese invention patent application disclose a kind of high voltage LED chip and preparation method thereof, this LED chip comprises multiple LED chip unit, it is isolated that cutting groove is set between each LED chip unit, each LED chip unit comprises an independently LED chip device, this LED chip device comprises the Sapphire Substrate set gradually, n-GaN layer, multi-layer quantum well layer, p-GaN layer, n-GaN layer is formed with n-type electrode, p-GaN layer is formed with p-type electrode, the top of epitaxial wafer is coated with insulation fluorescence coating, insulation fluorescence coating is filled in cutting groove, only expose being used for the n-type electrode of external electrical connections and p-type electrode.But it still adopts traditional metal salient point heat conduction, heat conduction and the integrity problem of LED high-voltage chip are not still solved.
For high voltage LED chip, solve heat dissipation problem, just must strengthen chip cooling area, this can only form two large bonding pads by the design on chip, then by tin cream welding, heat is diffused into substrate from pad.Because high-voltage chip is made up of multiple chip, form two large bonding pads needs new method.In addition between chip owing to being mutually spaced at epitaxial loayer, have the step being greater than 7um between chip, make chip surface not be in peer-level line, this can impact reflow soldering process.Simultaneously, the heat produced during LED chip work can make LED chip temperature raise, heat-conducting substrate due to fixing high voltage LED chip generally adopts FR4 wiring board, aluminium base or copper base PCB, the thermal stress that high voltage LED chip is different from the thermal coefficient of expansion of heat-conducting substrate and produce, LED chip may be caused to ftracture or metal salient point stripping, the luminous efficiency of impact to voltage LED chip and functional reliability thereof.
Summary of the invention
The object of this invention is to provide and a kind of there is the thermal stress that own absorption inside produces, the high voltage LED chip and preparation method thereof improving product reliability.
To achieve these goals, the present invention takes following technical solution:
High voltage LED chip, comprise substrate and be positioned at M the chip that described substrate surface is mutually independent, M >=2, described each chip comprises the n type gallium nitride layer be grown on successively on described substrate surface, luminescent layer and P type gallium nitride layer, described n type gallium nitride layer, luminescent layer and P type gallium nitride layer form the epitaxial loayer of chip, and the P type gallium nitride layer of described each chip is formed with reflector; Cover the epitaxial loayer of described each chip and the insulating barrier on surface, reflector, described insulating barrier is along chip perimeter sidewall and substrate attaching; The P be electrically connected with the reflector of the first chip goes between electrode; The N be electrically connected with the n type gallium nitride layer of M chip goes between electrode; The PN being carried out being electrically connected in series in the reflector of the n type gallium nitride layer of the i-th chip and the i-th+1 chip successively goes between connecting electrode, i=1 ..., M-1, the PN lead-in wire connecting electrode of every two chips of mutually connecting is mutually independent; Planarization layer, described planarization layer is organosilicon glue-line, planarization layer be covered in P go between electrode, PN go between connecting electrode and N go between electrode surface on and go between electrode, PN of P go between on surface of insulating layer that connecting electrode and N go between electrode; To be deposited on described planarization layer and to go between the N pad of Electrode connection with described N; To be deposited on described planarization layer and to go between the P pad of Electrode connection with described P.
High voltage LED chip of the present invention, also comprises: run through described epitaxial loayer, expose the groove of described substrate surface, described groove is by isolated for each chip; Run through the P type gallium nitride of each chip, luminescent layer until the N electrode hole on n type gallium nitride layer surface; Described insulating barrier fills described groove and N electrode hole, the insulating barrier of each chip is formed with the P type contact hole be connected with surface, described reflector and the N-type contact hole be connected with described n type gallium nitride layer surface; Described P lead-in wire electrode deposition is electrically connected with the reflector of the first chip on the partial insulative layer of the first chip surface and in P type contact hole, by the P type contact hole on the first chip; Described N go between electrode deposition on the partial insulative layer of M chip surface and in N-type contact hole, be electrically connected with the n type gallium nitride layer of M chip by the N-type contact hole on M chip; Described PN goes between on partial insulative layer that connecting electrode is deposited on adjacent chips and N-type contact hole, in P type contact hole; Described planarization layer is formed with N that the electrode surface that to go between with the N on M chip is connected to go between electrode contact hole and going between electrode contact hole with go between P that electrode surface is connected of the P on the first chip; Described N pad is deposited on described planarization layer and the Electrode connection that goes between with described N in described N lead-in wire electrode contact hole; Described P pad is deposited on described planarization layer and the Electrode connection that goes between with described P in described P lead-in wire electrode contact hole.
Insulating barrier of the present invention is aluminium nitride or silicon dioxide or silicon nitride or alundum (Al2O3) or Bragg reflecting layer or organosilicon glue-line.
Planarization layer of the present invention is the organosilicon glue-line that viscosity is greater than 400mPa.s, thickness is greater than 6um.
N pad of the present invention and P bond pad surface are coated with tin paste layer.
The thickness of tin paste layer of the present invention is 50 ~ 100um.
Tin paste layer of the present invention is made up of Sn, Ag, Cu, and wherein the mass percent of Sn is the mass percent of 96.5, Ag is 3.0, and surplus is Cu.
N pad of the present invention and P bond pad surface are coated with eutectic layer.
The thickness of eutectic layer of the present invention is 4 ~ 20um.
Planarization layer of the present invention is fitted along chip perimeter sidewall and insulating barrier, and each chip is wrapped up completely by described insulating barrier and planarization layer successively.
N pad of the present invention and P pad symmetrical, described P pad and N pad thickness are interval >=150um between 1um ~ 2um, P pad and N pad.
P pad of the present invention and N pad are folded formed by aluminium, nickel, titanium, platinum, layer gold.
The preparation method of high voltage LED chip, comprises the following steps:
Step one, provide substrate, described substrate surface grows n type gallium nitride layer, light-emitting layer grows on n type gallium nitride layer, growing P-type gallium nitride layer on luminescent layer, described n type gallium nitride layer, luminescent layer and P type gallium nitride layer form the epitaxial loayer of each chip;
Step 2, on P type gallium nitride layer, cover reflector;
Step 3, on epitaxial loayer, form groove, the degree of depth of groove to substrate surface, expose substrate; Formed and run through P type gallium nitride layer, luminescent layer until the N electrode hole on n type gallium nitride layer surface;
Step 4, surface coverage insulating barrier in epitaxial loayer and reflector, insulating barrier is filling groove and N electrode hole simultaneously;
Step 5, in surface of insulating layer punching, to etch and the reflector P type contact hole that is connected of surface and the N-type contact hole that be connected surperficial with n type gallium nitride layer;
Step 6, form the P lead-in wire electrode with wiring pattern on the insulating layer, N lead-in wire electrode and PN lead-in wire connecting electrode, P lead-in wire electrode is deposited on partial insulative layer on the first chip surface and in P type contact hole, N lead-in wire electrode is deposited on partial insulative layer on M chip surface and in N-type contact hole, on the partial insulative layer of adjacent chips and N-type contact hole, deposition PN lead-in wire connecting electrode in P type contact hole, the reflector of the n type gallium nitride layer of the i-th chip and the i-th+1 chip is electrically connected in series by PN lead-in wire connecting electrode successively, i=1, M, wherein the PN lead-in wire connecting electrode of every two chips of mutually connecting is mutually independent,
Step 7, forms planarization layer, planarization layer cover P go between electrode, N go between electrode and PN go between connecting electrode surface and be positioned at P go between electrode and the PN of electrode, N that go between and go between the surface of connecting electrode insulating barrier each other;
Step 8, form in planarization layer photoetching the N that electrode surface is connected of going between with the N on M chip and to go between electrode contact hole and going between electrode contact hole with go between P that electrode surface is connected of the P on the first chip;
Step 9, part planarization layer on the surface and N go between in electrode contact hole and form N pad, P pad is formed on the surface and in P lead-in wire electrode contact hole at part planarization layer, N pad by N go between electrode contact hole with and the N electrode that go between contact, P pad is contacted by P lead-in wire electrode contact hole and P lead-in wire electrode.
The step that the present invention forms described planarization layer is as follows: adopting spraying coating process to form thickness is the planarization layer of 6 ~ 10um, bake 2 minutes at the temperature of 110 DEG C, then expose, develop, and toast at the temperature of 180 DEG C and be cured for 2 hours, planarization layer is fitted along chip perimeter sidewall and insulating barrier.
From above technical scheme, the present invention adopts possesses certain flexible organic silica gel formation planarization layer, the thermal stress causing inside of high-voltage chip to be damaged can be absorbed, thus ensure the reliability of LED high-voltage chip operation, in preferred version, each chip wraps up along chip perimeter sidewall by insulating barrier and planarization layer completely, not only helps tin cream reflow soldering process, and when can also prevent from welding, tin cream is climbed tin thus causes electric leakage or short circuit; P pad and N pad is symmetrical, upside-down mounting contact area is large, flip chip bonding is aimed at easily, and low to circuit board layout precision prescribed, flip-chip bonding process is simple.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment of the present invention;
Fig. 2 a is the structural representation that embodiment of the present invention high voltage LED chip forms epitaxial loayer;
Fig. 2 b is the structural representation that high voltage LED chip forms reflector;
Fig. 2 c is the structural representation that high voltage LED chip forms groove and N electrode hole;
Fig. 2 d is the structural representation that high voltage LED chip forms insulating barrier;
Fig. 2 e is the structural representation that high voltage LED chip forms P type contact hole and N-type contact hole;
Fig. 2 f is that high voltage LED chip forms N lead-in wire electrode, PN goes between connecting electrode and the structural representation of P lead-in wire electrode;
Fig. 2 g is the structural representation that high voltage LED chip forms planarization layer;
Fig. 2 h is the structural representation that high voltage LED chip forms N lead-in wire electrode contact hole and P lead-in wire electrode contact hole;
Fig. 2 i is the structural representation that high voltage LED chip forms N pad and P pad;
Fig. 3 is the structural representation of the high voltage LED chip of another embodiment of the present invention;
Fig. 4 is the structural representation of the high voltage LED chip of further embodiment of this invention.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in more detail.
Embodiment
As shown in Figure 1, high voltage LED chip of the present invention comprises substrate 1 and is positioned at substrate 1 and to insulate each other on the surface independently M chip 10, M be more than or equal to 2 integer, each chip 10 comprises the n type gallium nitride layer 11 be grown on successively on substrate 1 surface, luminescent layer 12 and P type gallium nitride layer 13, P type gallium nitride layer 13 covers reflector 15, and n type gallium nitride layer 11, luminescent layer 12 and P type gallium nitride layer 13 form the epitaxial loayer 2 of each chip.Each chip is kept apart (Fig. 2 c) by groove 3, and the degree of depth of groove 3 is to substrate 1 surface.At epitaxial loayer 2 and the reflector 15 surface coverage insulating barrier 16 of each chip.Insulating barrier 16 is arranged go between electrode 31, the N that is connected with the n type gallium nitride layer 11 of M chip of the P that is connected with the reflector 15 of the first chip to go between electrode 32 and connecting electrode 33 that the PN that the reflector of the n type gallium nitride layer of a chip and an adjacent chip is connected in series successively is gone between.P go between electrode 31, PN go between connecting electrode 33 and N go between electrode 32 surface on and be positioned at P electrode, PN connecting electrode and the N electrode insulating barrier 16 each other that goes between that goes between that goes between and be coated with planarization layer 22 on the surface, planarization layer 22 be provided with N pad 26 that the electrode 32 that to go between with N is connected and go between the P pad 27 that electrode 31 is connected with P.Reflective insulant can be filled between N pad 26 and P pad 27, the insulating material possessing reflecting properties is packed between N pad and P pad, as titanium oxide, not only can avoid occurring short circuit phenomenon between N pad and P pad, and the light extraction efficiency of chip can be improved.
Below in conjunction with Fig. 2 a to Fig. 2 i, be described the preparation method of embodiment of the present invention high voltage LED chip, this preparation method comprises the following steps:
Step one, as shown in Figure 2 a, substrate 1 is provided, the substrate 1 of the present embodiment is Sapphire Substrate, by MOCVD (Metal-organic Chemical Vapor Deposition, metallo-organic compound chemical gaseous phase deposition) at substrate 1 surface-borne epitaxial loayer 2, epitaxial loayer 2 growth course is followed successively by: at substrate 1 superficial growth n type gallium nitride layer 11, light-emitting layer grows 12 on n type gallium nitride layer 11, growing P-type gallium nitride layer 13 on luminescent layer 12;
Step 2, as shown in Figure 2 b, adopts evaporation and photoetching process to cover reflector 15 on P type gallium nitride layer 13, the material in this reflector 15 can be aluminium, nickel, silver or above-mentioned arbitrarily both alloy;
Step 3, as shown in Figure 2 c, by adopting ICP etch process to epitaxial loayer, epitaxial loayer is formed groove 3, the degree of depth of groove 3 to substrate 1 surface, expose substrate 1, epitaxial loayer arranges groove, the first chip described epitaxial loayer being formed be mutually independent to M chip, M be more than or equal to 2 integer; Etch each chip 10, run through P type gallium nitride layer 13, luminescent layer 12 until the N electrode hole 4 on n type gallium nitride layer 11 surface to be formed on each chip 10 surface, the quantity in N electrode hole 4 can be multiple and be uniformly distributed at chip surface;
Alternatively, the n type gallium nitride layer deposited on silicon N-type electrode bottom N electrode hole 4 described in each, N-type electrode material is aluminium, gold or both alloys;
Step 4, as shown in Figure 2 d, the surface coverage insulating barrier 16 in epitaxial loayer and reflector by sputtering or PECVD (Plasma Enhanced Chemical Vapor Deposition) technique, insulating barrier 16 is filling groove and N electrode hole simultaneously, each chip, along chip perimeter sidewall and substrate attaching, wraps up by insulating barrier completely; Described thickness of insulating layer is 1um ~ 2.5um, and the material of insulating barrier can be aluminium nitride or silicon dioxide or silicon nitride or alundum (Al2O3) or Bragg reflecting layer DBR or silica gel or resin or acrylic acid, and Bragg reflecting layer is silicon dioxide SiO
2with titanium dioxide TiO
2multilayer alternating structure; Preferably, insulating layer material is organic silica gel, and organic silica gel itself possesses high filling micron order cavity ability, can effectively filling groove 3 and the cavity left by N electrode hole 4, reduce the transmitting that this type of cavity is formed light, improve chip light emitting efficiency and prevent chip chamber from leaking electricity;
Step 5, as shown in Figure 2 e, adopt chemical etching technology in the punching of insulating barrier 16 surface, each chip etches respectively P type contact hole 5 and N-type contact hole 6, wherein, P type contact hole 5 is connected with surface, reflector 15, expose reflector 15 bottom P type contact hole 5, N-type contact hole 6 is connected with n type gallium nitride layer 11 surface, exposes reflector 11 bottom N-type contact hole 6;
Step 6, as shown in figure 2f, forms go between electrode 31, N of the P with wiring pattern by sputtering or evaporation process and to go between electrode 32 and PN lead-in wire connecting electrode 33 on insulating barrier 16, wherein, P lead-in wire electrode 31 is deposited on partial insulative layer 16 on the first chip surface and in P type contact hole, namely P lead-in wire electrode 31 is electrically connected with the reflector 15 of the first chip by the P type contact hole on the first chip, N lead-in wire electrode 32 is deposited on partial insulative layer 16 on M chip surface and in N-type contact hole, namely N lead-in wire electrode 32 is electrically connected with the n type gallium nitride layer 11 of M chip by the N-type contact hole on M chip, on the partial insulative layer 16 of adjacent chips and N-type contact hole, deposition PN lead-in wire connecting electrode 33 in P type contact hole, the reflector of the n type gallium nitride layer of the i-th chip and the i-th+1 chip is electrically connected in series by PN lead-in wire connecting electrode 33 successively, i=1, M, wherein the PN lead-in wire connecting electrode 33 of every two chips of mutually connecting is mutually independent,
Step 7, as shown in Figure 2 g, planarization layer 22 is formed by spraying coating process, planarization layer 22 covers the surface of P lead-in wire electrode 31, N lead-in wire electrode 32 and PN lead-in wire connecting electrode 33 and is positioned at the surface of P lead-in wire electrode 31, N lead-in wire electrode 32 and PN lead-in wire connecting electrode 33 insulating barrier 16 each other, and planarization layer 22 is fitted along chip perimeter sidewall and insulating barrier; The material of planarization layer 22 of the present invention is organic silica gel, thickness is 6 ~ 10um, in the present embodiment, spraying coating process is adopted to form organic layer of silica gel---planarization layer 22, bake 2 minutes at the temperature of 110 DEG C, the thickness of planarization layer 22 is 7.3um, then exposes (800mJ/cm2), TMAH develops (70sec, 3 times), and toast at the temperature of 180 DEG C and be cured for 2 hours;
Because planarization layer adopts organic silica gel, organic silica gel does not absorb visible spectrum and possesses certain flexible material, can absorb the thermal stress causing inside of high-voltage chip to be damaged, thus ensure the reliability of high voltage LED chip work; Employing has the organic silica gel of low curing temperature (<200 DEG C), is applicable to thermal Finite device; Because high-voltage LED device is by multiple integrated chip, each chip surface shoulder height difference is large, direct solder reflow process can not be adopted, the present invention adopts viscosity to be greater than 400mPa.s and thickness is greater than the organic silica gel of 6um to carry out step flatening process, make planarization layer 22 surface smooth, and planarization layer 22 is fitted along chip perimeter sidewall and insulating barrier, each chip is wrapped up completely, not only help tin cream reflow soldering process, and when preventing from welding, tin cream is climbed tin thus causes electric leakage or short circuit;
Step 8, as shown in fig. 2h, N lead-in wire electrode contact hole 28 and P lead-in wire electrode contact hole 29 is formed at planarization layer 22 by photoetching process, wherein, N lead-in wire electrode contact hole 28 and the N on M chip go between, and electrode 32 is surperficial to be connected, and P lead-in wire electrode contact hole 29 and the P on the first chip go between, and electrode 31 is surperficial to be connected; N lead-in wire electrode contact hole 28 and P lead-in wire electrode contact hole 29 can be multiple;
Step 9, as shown in fig. 2i, photoetching and evaporation coating technique is adopted to manufacture N pad 26 and the P pad 27 of mutually insulated, N pad 26 and P pad 27 cover part planarization layer 22 on the surface and be filled in go between electrode contact hole and P of N and go between in electrode contact hole, N pad 26 is contacted with the N electrode 32 that goes between by the N electrode contact hole that goes between, P pad 27 is contacted by P lead-in wire electrode contact hole 29 and P lead-in wire electrode 31, N pad 26 is symmetrical with P pad 27, between P pad and N pad, interval is more than or equal to 150um, because planarization layer 22 surface forms horizontal plane, therefore N pad 26 is highly consistent with both P pads 27, be easy to fixedly weld with pcb board, preferably, before evaporation N pad 26 with P pad 27, first carry out roughening operation on planarization layer 22 surface, be beneficial to and improve planarization layer 22 and N pad 26 and P pad 27 bonding strength, preferably, P pad and N pad thickness are that 1um ~ 2um, P pad and N pad are folded formed by aluminium, nickel, titanium, platinum, layer gold, and aluminium and planarization layer produce good adhesion, titanium, platinum are barrier layer, have and soak (wetting) effect when gold and tin cream Reflow Soldering.
As shown in Figure 3, as another embodiment of the present invention, at N pad 26 and P pad 27 on the surface by print or evaporation process covers tin paste layer 9, the thickness of tin paste layer 9 is 50 ~ 100um, tin paste layer 9 is made up of Sn, Ag, Cu, wherein the mass percent of Sn is the mass percent of 96.5, Ag is 3.0, and surplus is Cu.Because this tin cream material has less voidage, can effectively reduce heat dissipation channel thermal resistance, and possess extremely strong adhesion strength and conductive capability.And this tin paste layer belongs to the material of directly welding, be conducive to simplifying encapsulation step, and form stress buffer between high-voltage chip and PCB substrate.
As shown in Figure 4, as another embodiment of the present invention, cover eutectic layer 9 ' by evaporation process on the surface at N pad 26 and P pad 27, eutectic layer 9 ' is made up of Au and Sn, wherein the mass percent of Au is the mass percent of 80, Sn is 20, and the thickness of eutectic layer 9 ' is 4 ~ 20um.
Planarization layer of the present invention adopts high-viscosity organosilicon glue, belong to the high-insulativity material of low Young's modulus, fill up step ability, described planarization layer surface is made to be in same level, when the P that connects goes between electrode, PN lead-in wire connecting electrode and N lead-in wire electrode, the sandwich of P pad and N pad metal can not cause thermal expansion coefficient difference to cause stress cracking; And the high-voltage chip surrounding side layer that is flattened covers, when high-voltage chip can be prevented to be welded to FR4 wiring board, aluminium base or copper base circuit board, the situation of climbing electric leakage that tin causes or short circuit because of tin cream occurs.
Above embodiment is only in order to illustrate that technical scheme of the present invention is not intended to limit, although with reference to above-described embodiment to invention has been detailed description, those of ordinary skill in the field are to be understood that, still can modify to the specific embodiment of the present invention or equivalent replacement, and not departing from any amendment of spirit and scope of the invention or equivalent replacement, it all should be encompassed among right of the present invention.
Claims (12)
1. high voltage LED chip, comprise substrate and be positioned at M the chip that described substrate surface is mutually independent, M >=2, described each chip comprises the n type gallium nitride layer be grown on successively on described substrate surface, luminescent layer and P type gallium nitride layer, described n type gallium nitride layer, luminescent layer and P type gallium nitride layer form the epitaxial loayer of chip, and the P type gallium nitride layer of described each chip is formed with reflector;
It is characterized in that, also comprise:
Cover the epitaxial loayer of described each chip and the insulating barrier on surface, reflector, described insulating barrier is along chip perimeter sidewall and substrate attaching;
The P be electrically connected with the reflector of the first chip goes between electrode;
The N be electrically connected with the n type gallium nitride layer of M chip goes between electrode;
The PN being carried out being electrically connected in series in the reflector of the n type gallium nitride layer of the i-th chip and the i-th+1 chip successively goes between connecting electrode, i=1 ..., M-1, the PN lead-in wire connecting electrode of every two chips of mutually connecting is mutually independent;
Planarization layer, described planarization layer is organosilicon glue-line, planarization layer be covered in P go between electrode, PN go between connecting electrode and N go between electrode surface on and go between electrode, PN of P go between on surface of insulating layer that connecting electrode and N go between electrode;
To be deposited on described planarization layer and to go between the N pad of Electrode connection with described N;
To be deposited on described planarization layer and to go between the P pad of Electrode connection with described P.
2. high voltage LED chip as claimed in claim 1, is characterized in that: also comprise
Run through described epitaxial loayer, expose the groove of described substrate surface, described groove is by isolated for each chip;
Run through the P type gallium nitride of each chip, luminescent layer until the N electrode hole on n type gallium nitride layer surface;
Described insulating barrier fills described groove and N electrode hole, the insulating barrier of each chip is formed with the P type contact hole be connected with surface, described reflector and the N-type contact hole be connected with described n type gallium nitride layer surface;
Described P lead-in wire electrode deposition is electrically connected with the reflector of the first chip on the partial insulative layer of the first chip surface and in P type contact hole, by the P type contact hole on the first chip;
Described N go between electrode deposition on the partial insulative layer of M chip surface and in N-type contact hole, be electrically connected with the n type gallium nitride layer of M chip by the N-type contact hole on M chip;
Described PN goes between on partial insulative layer that connecting electrode is deposited on adjacent chips and N-type contact hole, in P type contact hole;
Described planarization layer is formed with N that the electrode surface that to go between with the N on M chip is connected to go between electrode contact hole and going between electrode contact hole with go between P that electrode surface is connected of the P on the first chip;
Described N pad is deposited on described planarization layer and the Electrode connection that goes between with described N in described N lead-in wire electrode contact hole; Described P pad is deposited on described planarization layer and the Electrode connection that goes between with described P in described P lead-in wire electrode contact hole.
3. high voltage LED chip as claimed in claim 1, is characterized in that: described insulating barrier is aluminium nitride or silicon dioxide or silicon nitride or alundum (Al2O3) or Bragg reflecting layer or organosilicon glue-line.
4. high voltage LED chip as claimed in claim 1, is characterized in that: described planarization layer is the organosilicon glue-line that viscosity is greater than 400mPa.s, thickness is greater than 6um.
5. high voltage LED chip as claimed in claim 1, is characterized in that: described N pad and P bond pad surface are coated with tin paste layer or eutectic layer.
6. high voltage LED chip as claimed in claim 5, is characterized in that: the thickness of described tin paste layer is 50 ~ 100um, or the thickness of described eutectic layer is 4 ~ 20um.
7. the high voltage LED chip as described in claim 5 or 6, is characterized in that: described tin paste layer is made up of Sn, Ag, Cu, and wherein the mass percent of Sn is the mass percent of 96.5, Ag is 3.0, and surplus is Cu.
8. high voltage LED chip as claimed in claim 1, is characterized in that: described planarization layer is fitted along chip perimeter sidewall and insulating barrier, and each chip is wrapped up completely by described insulating barrier and planarization layer successively.
9. high voltage LED chip as claimed in claim 1, is characterized in that: described N pad and P pad symmetrical, described P pad and N pad thickness are interval >=150um between 1um ~ 2um, P pad and N pad.
10. the high voltage LED chip as described in claim 1 or 9, is characterized in that: described P pad and N pad are folded formed by aluminium, nickel, titanium, platinum, layer gold.
The preparation method of 11. high voltage LED chip, is characterized in that, comprises the following steps:
Step one, provide substrate, described substrate surface grows n type gallium nitride layer, light-emitting layer grows on n type gallium nitride layer, growing P-type gallium nitride layer on luminescent layer, described n type gallium nitride layer, luminescent layer and P type gallium nitride layer form the epitaxial loayer of each chip;
Step 2, on P type gallium nitride layer, cover reflector;
Step 3, on epitaxial loayer, form groove, the degree of depth of groove to substrate surface, expose substrate; Formed and run through P type gallium nitride layer, luminescent layer until the N electrode hole on n type gallium nitride layer surface;
Step 4, surface coverage insulating barrier in epitaxial loayer and reflector, insulating barrier is filling groove and N electrode hole simultaneously;
Step 5, in surface of insulating layer punching, to etch and the reflector P type contact hole that is connected of surface and the N-type contact hole that be connected surperficial with n type gallium nitride layer;
Step 6, form the P lead-in wire electrode with wiring pattern on the insulating layer, N lead-in wire electrode and PN lead-in wire connecting electrode, P lead-in wire electrode is deposited on partial insulative layer on the first chip surface and in P type contact hole, N lead-in wire electrode is deposited on partial insulative layer on M chip surface and in N-type contact hole, on the partial insulative layer of adjacent chips and N-type contact hole, deposition PN lead-in wire connecting electrode in P type contact hole, the reflector of the n type gallium nitride layer of the i-th chip and the i-th+1 chip is electrically connected in series by PN lead-in wire connecting electrode successively, i=1, M, wherein the PN lead-in wire connecting electrode of every two chips of mutually connecting is mutually independent,
Step 7, forms planarization layer, planarization layer cover P go between electrode, N go between electrode and PN go between connecting electrode surface and be positioned at P go between electrode and the PN of electrode, N that go between and go between the surface of connecting electrode insulating barrier each other;
Step 8, form in planarization layer photoetching the N that electrode surface is connected of going between with the N on M chip and to go between electrode contact hole and going between electrode contact hole with go between P that electrode surface is connected of the P on the first chip;
Step 9, part planarization layer on the surface and N go between in electrode contact hole and form N pad, P pad is formed on the surface and in P lead-in wire electrode contact hole at part planarization layer, N pad by N go between electrode contact hole with and the N electrode that go between contact, P pad is contacted by P lead-in wire electrode contact hole and P lead-in wire electrode.
The preparation method of 12. high voltage LED chip as claimed in claim 11, is characterized in that: the step forming described planarization layer is as follows:
Adopting spraying coating process to form thickness is the planarization layer of 6 ~ 10um, at the temperature of 110 DEG C roasting 2 minutes, then exposes, develops, and toasts at the temperature of 180 DEG C and be cured for 2 hours, and described planarization layer is fitted along chip perimeter sidewall and insulating barrier.
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