CN107331679A - A kind of the high voltage LED chip structure and preparation method of CSP encapsulation - Google Patents
A kind of the high voltage LED chip structure and preparation method of CSP encapsulation Download PDFInfo
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- CN107331679A CN107331679A CN201710540841.5A CN201710540841A CN107331679A CN 107331679 A CN107331679 A CN 107331679A CN 201710540841 A CN201710540841 A CN 201710540841A CN 107331679 A CN107331679 A CN 107331679A
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- 238000005538 encapsulation Methods 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910017083 AlN Inorganic materials 0.000 claims description 5
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000010408 film Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 239000000843 powder Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000005507 spraying Methods 0.000 claims 1
- 239000012790 adhesive layer Substances 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- 238000000926 separation method Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 206010040844 Skin exfoliation Diseases 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000035618 desquamation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The present invention discloses a kind of the high voltage LED chip structure and preparation method of CSP encapsulation, including upside-down mounting high voltage LED chip, fluorescent adhesive layer, package substrate, the upside-down mounting high voltage LED chip is welded on package substrate, each high-voltage chip includes many sub- chips, each sub- chip is separated by isolating deep trench, every sub- chip includes n-type GaN, active layer, p-type GaN layer, current extending, and n-electrode and p-electrode on p-type GaN table tops, wherein n-electrode is connected by deep trench side-wall metallic conductive layer with n-type GaN inclined-planes, pass through insulator separation between metal conducting layer and sub- chip, the n-electrode and p-electrode of each sub- chip again respectively with electrode of substrate pad and interconnection line bonding.The present invention has the reliability that CSP encapsulation volumes are small and the low advantage of high-voltage chip power requirement, are electrically connected between the sub- chip that can further increase high-voltage chip concurrently, increases the area of chip light emitting layer under equal chip area.
Description
Technical field
The present invention relates to a kind of preparation method of high voltage LED chip, more particularly to a kind of high-voltage LED core of CSP encapsulation
Piece and preparation method thereof, belongs to semi-conductor LED chips manufacture and encapsulation field.
Background technology
Semiconductor lighting light emitting diode (LED) has light efficiency height, long lifespan, environmental protection, the saving energy etc. many excellent
Point, is described as the revolutionary technology in 21 century in new solid light source epoch, is referred to as forth generation green light source.
CSP, i.e. wafer-level package device, refer to encapsulation volume and flip-chip fixing fabric structure to identical or encapsulation volume
No more than the 20% of flip-chip volume, in LED field, CSP encapsulation is because small volume, and flexibility ratio is high, and its application is more next
It is more extensive.In addition, as LED is in the deep development of lighting field, the drawbacks of traditional low-voltage LED increasingly exposes intrinsic,
Low including driving power supply short life, conversion efficiency, low-voltage LED thermal diffusivity is bad, it is impossible to worked under high current, in solution
Problem is stated, high voltage LED chip arises in recent years, this high voltage LED chip is integrated multiple series connection on the same chip
Sub- chip, this little chip is directly just completed in chip manufacturing proces, has the advantages that power requirement is low, light efficiency is high；
Upside-down mounting high voltage LED chip emits light from substrate sapphire, and encapsulation process utilizes eutectic welding method, by chip front side
Electrode be aligned and weld with the electrode pad on substrate, it is not necessary to carry out electrode connection with gold thread, add the steady of encapsulation
It is qualitative, in addition, the heat that the high-voltage LED luminescent layer of inverted structure is produced is directly transmitted to substrate, with more preferable radiating effect.Cause
This, the high-voltage chip of CSP encapsulation had both reduced the volume of encapsulation, and had had high voltage LED chip excellent compared to conventional low chip again
Gesture.
A kind of CSP packaged chip structures and making disclosed in Chinese invention patent application Publication No. CN 105633240
Method, the loss of light-emitting area is reduced by using n-type GaN sloped sidewalls formation n-electrode, but it only produces pressure common
It is related to the technique for forming slope twice in the LED chip of CSP encapsulation, manufacturing process.
A kind of upside-down mounting high-voltage LED disclosed in Chinese invention patent application Publication No. CN 103855149 and
Preparation method, being interconnected on flip-chip substrate between sub- chip is completed, solution is got over due to interconnection line caused by deep trench
Metal conducting layer is made in less reliable's problem, but the sub- chip sides of vertical stratification, metal in uneven thickness is easily formed
Film, high current by when easily cause open circuit.
The content of the invention
It is an object of the invention to provide the high voltage LED chip structure and preparation method of a kind of CSP encapsulation, existing skill is solved
In art, the intrinsic drawback that the conventional low voltage LED that CSP is encapsulated exposes, including driving power supply short life, conversion efficiency are low, scattered
Hot bad the shortcomings of；Meanwhile, the integrity problem of electrical interconnection between the sub- chip of Conventional flip high-voltage LED is improved, maximally
Increase the luminescent layer area under equal chip area.
To achieve these goals, the present invention is adopted the following technical scheme that：A kind of CSP encapsulation high voltage LED chips and its system
Make method, including upside-down mounting high voltage LED chip, fluorescent glue, package substrate, the upside-down mounting high voltage LED chip is welded on package substrate
On, each high-voltage chip includes many sub- chips, and each sub- chip is separated by isolating deep trench, and every sub- chip includes n
Type GaN, active layer, p-type GaN layer, current extending and n-electrode and p-electrode, the n-electrode pass through deep trench side-wall metallic
Conductive layer is connected with n-type GaN inclined-planes, by isolating the insulating barrier covered on deep trench footwear slope between metal conducting layer and sub- chip
Isolation, the n-electrode and p-electrode of each sub- chip again respectively with electrode of substrate pad and interconnection wire bonding, fluorescent adhesive layer is positioned at upside-down mounting
On the upside of chip.
Further, metal conducting layer, n-electrode, p-electrode are preferably golden using the electric conductivity such as Ag, Ni, Al and reflecting properties
Category, can be single-layer metal structure, it would however also be possible to employ multi-layer metal structure or the alloy-layer that they are constituted；
Further, current-diffusion layer can be ito thin film or metallic film or other conductive films；
Further, insulating barrier can be the materials such as silicon nitride, silica or aluminium nitride composition or these materials
Combination or composition dbr structure；
Further, n-electrode, p-electrode are respectively positioned on p-type GaN table tops, electric isolution, n-electrode and current extending between them
Between with insulator separation；
Further, electrical interconnection line and electrode pad between sub- chip are provided with package substrate；
Further, upside-down mounting high voltage LED chip electrode to substrate with after package substrate electrode pad and interconnection line bonding, carrying out
Laser lift-off, and sprayed with fluorescent powder layer and protection glue-line on n-type GaN；
Further, package substrate uses AlN, Si or metal material, baseplate material and electrode of substrate pad and interconnection line it
Between be electrically isolated with insulating barrier.
Brief description of the drawings
Fig. 1 is the high voltage LED chip structural representation that CSP of the present invention is encapsulated；
Fig. 2 is the preparation method flow chart of the high voltage LED chip of CSP encapsulation in one embodiment of the invention；
Fig. 3 is the three-dimensional view before one embodiment of the invention mesohigh LED chip is encapsulated；
Fig. 4-10 is each step structural representation for the high voltage LED chip manufacturing process that CSP of the present invention is encapsulated；
Embodiment
In order that those skilled in the art more fully understand the present invention program, more detailed is made to the present invention below according to accompanying drawing
Thin explanation.All features, method or step disclosed in this specification, in addition to mutually exclusive feature or step,
Combine in any way.Any feature disclosed in this specification, unless specifically stated otherwise, can be replaced by other equivalent features
Change, each feature be equivalent or similar characteristics in an example, unless there are special narration.
Refering to a kind of high voltage LED chip constructive embodiment one for CSP encapsulation that shown in Fig. 1 to Figure 10, the present invention is disclosed, bag
Include：N-type GaN layer 2, active layer 3, p-type GaN layer 4, current extending 5, isolation deep trench 6, insulating barrier 7, metal conducting layer 8, n
Electrode 9a and p-electrode 9b, package substrate 10, electrode of substrate pad 11 and fluorescent adhesive layer 12.The isolation deep trench 6 is high pressure
Chip epitaxial layer is separated into two or more sub- chips, and every sub- chip has p-electrode independent of each other and n-electrode, insulated
Layer 7 isolates metal conducting layer 8 and p-type GaN, and the metal conducting layer 8 and p-electrode 9a, n-electrode 9b are the conductions such as Ag, Ni, Al
Property and all preferable metal of reflecting properties, can use single-layer metal structure, it would however also be possible to employ multi-layer metal structure；Sub- chip it
Between lateral wall slope is formed by deep isolated groove 8, and be formed on forming metal on insulating barrier 7, the slope of n-type GaN layer 2
Conductive layer 8, and extended to along the insulating barrier 7 on oblique wave n-electrode is formed in p-type GaN layer 4, n-electrode and p-electrode respectively with base
Plate counter electrode pad 11 is welded.After high-voltage chip and electrode of substrate pad solder, using laser lift-off substrate desquamation, and
Sprayed with fluorescent powder and protection glue-line 12 in the n-type GaN layer 2 exposed.
A kind of high voltage LED chip of CSP encapsulation, its preparation method such as Fig. 4-10 comprise the following steps：
Step S1, as shown in Figure 4 there is provided substrate 1, can be Sapphire Substrate, in its growing epitaxial layers, be followed successively by n
Type GaN layer 2, active layer 3, p-type GaN layer 4, and prepare on epitaxial layer current extending 5；
Walk poly- S2, as shown in figure 5, etching epitaxial layer and current extending are to Sapphire Substrate, formed sub- chip chamber every
Slope 61 is formed from deep trench 6, and in side, Fig. 5 illustrate only 3 sub- chips, but the invention is not restricted to 3 sub- chips, can
To be many sub- chips；
Walk poly- S3, as shown in fig. 6, isolation deep trench after the completion of, insulating barrier 7 is prepared on whole chip, the insulating barrier by
Combination or the dbr structure of composition of the insulating materials such as silicon nitride, silica or aluminium nitride composition or these materials, can
To be formed by modes such as sputtering or CVD, insulating barrier compactness is good enough, it is to avoid form pin hole or leak channel, then exhausted to this
Edge layer is etched, and forms the n-electrode through hole 72 and p-electrode through hole 71 of each sub- chip respectively, and wherein n-electrode through hole is located at isolation zanjon
On groove n-type GaN slopes, it is electrically isolated between sub- chip；
Step S4, as shown in fig. 7, using magnetron sputtering, thermal evaporation techniques, electron beam evaporation technique or other methods,
The metal conducting layer with high reflectance is formed on insulating barrier, the conductive layer can be the metals such as Ag, Ni, Al, can be individual layer
Metal structure, it would however also be possible to employ multi-layer metal structure or the alloy-layer that they are constituted；Metal conducting layer is etched again, respectively
The n-electrode 9b and p-electrode 9a of each sub- chip are formed, is electrically isolated between n-electrode and p-electrode, n-electrode is connected by metal conducting layer 8
It is connected on n-type GaN slopes；
Poly- S5 is walked, as shown in figure 8, using the AlN ceramic by directly covering copper method (DBC) metallization, being used as upside-down mounting
The package substrate material of high voltage LED chip is welded, and metal electrode pad is prepared with galvanoplastic thereon；Using hot pressing ultrasonic bond
Connection technology or other technologies, have welded n-electrode 9b and p-electrode 9a with the corresponding electrode pad of package substrate 10 and interconnection line 11
Come, welding manner includes eutectic weldering, bonding or conducting resinl bonding etc.；
Poly- S6 is walked, as shown in figure 9, laser lift-off substrate 1, and sprayed with fluorescent powder and protection glue-line 12 in n-type GaN layer 2；
Step S7, as shown in Figure 10, cuts into the high voltage LED chip device of independent CSP encapsulation.
In the case where not departing from spirit of the invention or necessary characteristic, the present invention can be embodied in other specific forms.Should
The specific embodiment each side is considered merely as illustrative and non-limiting.Therefore, scope of the invention such as appended claims
It is shown in scope rather than shown as indicated above.It is all fall change in the equivalent meaning and scope of claim should be regarded as
Fall in the category of claim.
Claims (6)
1. a kind of high voltage LED chip structure of CSP encapsulation, including high voltage LED chip, fluorescent glue, package substrate, its feature exist
In the LED high-voltage flip-chip is connected on package substrate, and each high-voltage chip includes many sub- chips, and each sub- chip leads to
Cross isolation deep trench to separate, every sub- chip includes n-type GaN layer, active layer, p-type GaN layer, current extending and n electricity
Pole and p-electrode, wherein n-electrode are extended on n-type GaN slopes by metal conducting layer, and this metal conducting layer passes through insulating barrier and p
Type GaN and the isolation of active layer side wall；The n-electrode and p-electrode are respectively positioned on above p-type GaN and are electrically isolated, n-electrode and p-electrode with
Package substrate counter electrode pad and interconnection line are welded.
2. the high voltage LED chip structure of CSP according to claim 1 encapsulation, it is characterised in that the n-electrode, p-electrode with
And metal conducting layer, using three kinds of electric conductivity and all preferable metals of reflecting properties such as Ag, Al, Ni, it uses single-layer metal structure
Or multi-layer metal structure.
3. the high voltage LED chip structure of CSP encapsulation according to claim 1, it is characterised in that the current-diffusion layer can
To be ito thin film or metallic film.
4. the high voltage LED chip structure of CSP according to claim 1 encapsulation, it is characterised in that the insulating barrier can be
The dbr structure of silicon nitride, silica or aluminium nitride material composition or these combinations of materials.
5. the high voltage LED chip structure of CSP encapsulation according to claim 1, it is characterised in that in n-type behind peeling liner bottom
Spraying forms fluorescent material and protection glue-line on GaN.
6. a kind of preparation method of the high voltage LED chip of CSP encapsulation, comprises the following steps：
Step 1 is there is provided substrate, in its growing epitaxial layers, is followed successively by n-type GaN layer, active layer, p-type GaN layer, current spread
Layer；
Poly- 2 are walked, etching epitaxial layer is to n-type GaN layer, the wall formation inclined-plane in side, after forming table top on n-type GaN surfaces, vertical etching
To substrate, the deep isolated groove of sub- chip chamber is formed；
Poly- 3 are walked, insulating barrier is covered in chip surface, and insulating barrier is etched, the n-electrode and p-electrode of each sub- chip is formed
Through hole；
Step 4, the metal conducting layer of high reflectance is formed on the insulating layer, and graphically forms the p-electrode pad of each sub- chip
With n-electrode pad, n-electrode pad is extended on n-type GaN table tops by metal conducting layer；
Poly- 5 are walked, the n-electrode and p-electrode electrode pad corresponding with package substrate and interconnection wire bonding of each sub- chip of high-voltage chip
Pick up and；
Walk poly- 6, laser lift-off substrate, and sprayed with fluorescent powder and protection glue-line on n-type GaN；
Step 7, individual devices are cut into.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710540841.5A CN107331679A (en) | 2017-07-05 | 2017-07-05 | A kind of the high voltage LED chip structure and preparation method of CSP encapsulation |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108288666A (en) * | 2018-01-26 | 2018-07-17 | 扬州乾照光电有限公司 | A kind of light emitting diode and electronic equipment of included radiator structure |
| CN109545917A (en) * | 2018-11-30 | 2019-03-29 | 扬州乾照光电有限公司 | A kind of quaternary crystal covering type LED structure and production method |
| CN109643643A (en) * | 2018-11-30 | 2019-04-16 | 长江存储科技有限责任公司 | Bond memory part and its manufacturing method |
| CN110071202A (en) * | 2018-01-24 | 2019-07-30 | 夏普株式会社 | Miniature LED element and image-displaying member |
| WO2019210516A1 (en) * | 2018-05-04 | 2019-11-07 | 厦门三安光电有限公司 | Light-emitting element, and light-emitting element array and light-emitting apparatus thereof |
| CN111463329A (en) * | 2019-01-18 | 2020-07-28 | 北京北方华创微电子装备有限公司 | L ED chip and manufacturing method thereof |
| CN111933768A (en) * | 2019-04-25 | 2020-11-13 | 深圳第三代半导体研究院 | Vertical integrated unit diode chip |
| JP2020202351A (en) * | 2019-06-13 | 2020-12-17 | 日亜化学工業株式会社 | Manufacturing method of light emitting element |
| CN112802953A (en) * | 2020-12-28 | 2021-05-14 | 厦门三安光电有限公司 | Light-emitting diode and preparation method thereof |
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| CN112968096A (en) * | 2020-11-25 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Light emitting diode chip, manufacturing method thereof and display device |
| CN113903834A (en) * | 2021-08-23 | 2022-01-07 | 华灿光电（浙江）有限公司 | Flip-chip red light diode chip and preparation method thereof |
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