CN113903834A - Flip-chip red light diode chip and preparation method thereof - Google Patents

Flip-chip red light diode chip and preparation method thereof Download PDF

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Publication number
CN113903834A
CN113903834A CN202110968669.XA CN202110968669A CN113903834A CN 113903834 A CN113903834 A CN 113903834A CN 202110968669 A CN202110968669 A CN 202110968669A CN 113903834 A CN113903834 A CN 113903834A
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layer
ohmic contact
electrode
supporting substrate
chip
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CN113903834B (en
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肖和平
朱迪
郭磊
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Abstract

The disclosure provides a flip-chip red light diode chip and a preparation method thereof, belonging to the technical field of light emitting diodes. The material of the supporting substrate is aluminum oxide, the supporting substrate and the epitaxial structure stacked on the supporting substrate are connected in a bonding mode through a silicon oxide bonding layer, on one hand, bonding cost is low, on the other hand, the first oxygen plasma processing structure on the surface of the supporting substrate is a thin Al-O-bond formed by oxygen and aluminum in the aluminum oxide, the second oxygen plasma processing structure on the surface of the silicon oxide bonding layer is a thin Si-O-bond formed by oxygen and silicon, the Al-O-bond and the Si-O-bond can be recombined in the bonding process to form a stable Al-O-Si bond with strong bonding force, a bonding interface with good repeatability and high stability is obtained, and the connection stability between the supporting substrate and the epitaxial structure stacked on the surface of the supporting substrate is improved, so that the device has high reliability.

Description

Flip-chip red light diode chip and preparation method thereof
Technical Field
The disclosure relates to the technical field of light emitting diodes, in particular to a flip-chip red light diode chip and a preparation method thereof.
Background
The red light emitting diode is a common light source device and is widely applied to remote control, vehicle sensing, closed circuit television and the like, and the red light emitting diode chip is a basic structure for preparing the red light emitting diode. The red led chip generally includes an epitaxial wafer and p and n electrodes. The epitaxial wafer comprises a supporting substrate, and an n-AlGaInP current expansion layer, an n-AlGaInP ohmic contact layer, an n-AlInP limiting layer, an active layer, a p-AlInP limiting layer, a Bragg reflector and a p-GaP ohmic contact layer which are sequentially stacked on the supporting substrate. The p-GaP ohmic contact layer is provided with a groove extending to the n-AlGaInP ohmic contact layer, the p electrode of the red light emitting diode chip can be arranged on the p-GaP ohmic contact layer, and the n electrode of the red light emitting diode chip can be arranged on the surface of the n-AlGaInP ohmic contact layer exposed by the groove.
The support substrate is not a growth substrate for growing the epitaxial structure on the support substrate, and the support substrate and the epitaxial structure are connected by bonding, which has a lower stability than direct growth and may affect the reliability of the finally obtained flip-chip red diode chip.
Disclosure of Invention
The embodiment of the disclosure provides a flip-chip red light-emitting diode chip and a preparation method thereof, which can improve the quality of the obtained red light-emitting diode chip and the overall stability and reliability. The technical scheme is as follows:
the disclosed embodiment provides a flip-chip red light diode chip, which comprises an epitaxial wafer, a p electrode and an n electrode,
the epitaxial wafer comprises a supporting substrate, and a silicon oxide bonding layer, a p-GaP ohmic contact layer, a p-AlInP limiting layer, an active layer, an n-AlInP limiting layer, an n-AlGaInP window layer and an n-GaAs ohmic contact layer which are sequentially laminated on the supporting substrate,
the material of the supporting substrate is aluminum oxide, the surface of the silicon oxide bonding layer which is laminated on the supporting substrate and the surface of the silicon oxide bonding layer which is in contact with the supporting substrate are respectively provided with a first oxygen plasma processing structure and a second oxygen plasma processing structure,
the p electrode is communicated with the p-GaP ohmic contact layer, and the n electrode is communicated with the n-GaAs ohmic contact layer.
Optionally, the surface of the p-GaP ohmic contact layer contacting the silicon oxide bonding layer has a roughened structure.
Optionally, the surface of the n-GaAs ohmic contact layer is provided with a groove extending to the p-GaP ohmic contact layer, the epitaxial wafer further comprises an insulating isolation layer and a conductive metal layer,
the insulating isolation layer covers the surface of the p-GaP ohmic contact layer exposed by the groove and extends to the n-GaAs ohmic contact layer, the conductive metal layer is positioned on the insulating isolation layer and is communicated with the p-GaP ohmic contact layer,
the p-electrode is laminated on the conductive metal layer.
Optionally, an included angle between the side wall of the groove and the surface of the supporting substrate is 40-50 degrees.
Optionally, the material of the insulating isolation layer is SixN。
Optionally, the maximum distance from the p-electrode to the supporting substrate is equal to the maximum distance from the n-electrode to the supporting substrate.
Optionally, the conductive metal layer comprises a first sub-layer and a second sub-layer stacked in sequence,
the first sub-layer is an Au/AuZn/Au structure laminated on the p-GaP ohmic contact layer, and the second sub-layer comprises a Ti/Pt/Ti structure laminated on the first sub-layer and the insulating isolation layer.
The embodiment of the disclosure provides a preparation method of a flip-chip red light diode chip, which comprises the following steps:
providing a support substrate and an epitaxial structure, wherein the support substrate is made of aluminum oxide;
the epitaxial structure comprises a growth substrate, and an n-GaAs ohmic contact layer, an n-AlGaInP window layer, an n-AlInP limiting layer, an active layer, a p-AlInP limiting layer, a p-GaP ohmic contact layer and a silicon oxide bonding layer which are sequentially stacked on the growth substrate;
forming a first oxygen plasma processing structure and a second oxygen plasma processing structure on the surface of the supporting substrate and the surface of the silicon oxide bonding layer respectively;
bonding the support substrate and the surface of the silicon oxide bonding layer with an oxygen plasma treatment structure;
removing the growth substrate;
forming a p electrode on one surface of the supporting substrate far away from the n-GaAs ohmic contact layer;
and forming a p electrode on the surface of the p-GaP ohmic contact layer, and forming an n electrode on the surface of the n-GaAs ohmic contact layer.
Optionally, the epitaxial wafer further comprises an insulating isolation layer and a conductive metal layer, the insulating isolation layer covers the surface of the p-GaP ohmic contact layer exposed by the groove and extends to the n-GaAs ohmic contact layer, the conductive metal layer is positioned on the insulating isolation layer and is communicated with the p-GaP ohmic contact layer, the p electrode is laminated on the conductive metal layer, and the insulating isolation layer is made of SixN，
The growth conditions of the insulating isolation layer include: the temperature is 280-320 ℃, the power is 50-120W, and the pressure is 50-150 pa.
Optionally, before bonding the supporting substrate and the surface of the silicon oxide bonding layer with the oxygen plasma processing structure, the method for preparing a flip-chip red light diode chip further includes:
and thinning the thickness of the supporting substrate and the silicon oxide bonding layer.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure include:
the material of the supporting substrate is aluminum oxide, the supporting substrate and the epitaxial structure stacked on the supporting substrate are connected in a bonding mode through a silicon oxide bonding layer, on one hand, bonding cost is low, on the other hand, the first oxygen plasma processing structure on the surface of the supporting substrate is a thin Al-O-bond formed by oxygen and aluminum in the aluminum oxide, the second oxygen plasma processing structure on the surface of the silicon oxide bonding layer is a thin Si-O-bond formed by oxygen and silicon, the Al-O-bond and the Si-O-bond can be recombined in the bonding process to form a stable Al-O-Si bond with strong bonding force, a bonding interface with good repeatability and high stability is obtained, and the connection stability between the supporting substrate and the epitaxial structure stacked on the surface of the supporting substrate is improved, so that the device has high reliability.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a flip-chip red light diode chip according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of another flip-chip red led chip according to an embodiment of the disclosure;
fig. 3 is a top view of another flip-chip red led chip according to an embodiment of the disclosure;
fig. 4 is a flowchart of a method for manufacturing a flip-chip red light diode chip according to an embodiment of the disclosure;
fig. 5 is a flowchart of another method for manufacturing a flip-chip red led chip according to an embodiment of the disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a flip-chip red light diode chip according to an embodiment of the present disclosure, and it can be seen from fig. 1 that the embodiment of the present disclosure provides a flip-chip red light diode chip, which includes an epitaxial wafer 1, a p electrode 2, and an n electrode 3.
The epitaxial wafer 1 includes a support substrate 11, and a silicon oxide bonding layer 12, a p-GaP ohmic contact layer 13, a p-AlInP confinement layer 14, an active layer 15, an n-AlInP confinement layer 16, an n-AlGaInP window layer 17, and an n-GaAs ohmic contact layer 18 laminated in this order on the support substrate 11.
The material of the supporting substrate 11 is alumina, and the surface of the laminated silicon oxide bonding layer 12 of the supporting substrate 11 and the surface of the laminated silicon oxide bonding layer 12 in contact with the supporting substrate 11 have a first oxygen plasma processing structure and a second oxygen plasma processing structure, respectively.
The p-electrode 2 communicates with the p-GaP ohmic contact layer 13, and the n-electrode 3 communicates with the n-GaAs ohmic contact layer 18.
The material of the supporting substrate 11 is alumina, the supporting substrate 11 and the epitaxial structure stacked on the supporting substrate 11 are bonded and connected through a silicon oxide bonding layer 12, on one hand, the bonding cost is low, on the other hand, the first oxygen plasma processing structure on the surface of the supporting substrate 11 is a thin Al-O-bond formed by oxygen and aluminum in the alumina, the second oxygen plasma processing structure on the surface of the silicon oxide bonding layer 12 is a thin Si-O-bond formed by oxygen and silicon, and the Al-O-bond and the Si-O-bond can be recombined to form a stable Al-O-Si bond with strong bonding force in the bonding process, so that a bonding interface with good repeatability and high stability is obtained, the connection stability between the supporting substrate 11 and the epitaxial structure stacked on the surface of the supporting substrate 11 is improved, and the device has high reliability.
The first oxygen plasma-treated structure and the second oxygen plasma-treated structure are microscopic atomic structures.
Illustratively, the thickness of the silicon oxide bonding layer 12 is 1.6-2.5 um.
When the thickness of the silicon oxide bonding layer 12 is within the above range, the bonding quality of the silicon oxide bonding layer 12 can be controlled to be good, and the stability of the obtained red light diode chip is improved.
Optionally, the surface of the p-GaP ohmic contact layer 13 in contact with the silicon oxide bonding layer 12 has a roughened structure.
The contact surface of the p-GaP ohmic contact layer 13 and the silicon oxide bonding layer 12 is provided with a roughening structure, so that the connection stability of the p-GaP ohmic contact layer 13 and the silicon oxide bonding layer 12 can be improved, the stable bonding between the silicon oxide bonding layer 12 and the supporting substrate 11 can be ensured, and the stability and reliability of the finally obtained red light diode chip can be improved.
Fig. 2 is a schematic structural diagram of another flip-chip red diode chip according to an embodiment of the disclosure, and referring to fig. 2, the flip-chip red diode chip includes an epitaxial wafer 1, a p electrode 2, and an n electrode 3.
The epitaxial wafer 1 includes a support substrate 11, and a silicon oxide bonding layer 12, a p-GaP ohmic contact layer 13, a p-AlInP confinement layer 14, an AlInP transition layer 202, a first AlGaInP waveguide layer 203, an active layer 15, a second AlGaInP waveguide layer 204, an n-AlInP confinement layer 16, an n-AlGaInP current blocking layer 205, an n-AlGaInP window layer 17, an n-GaAs ohmic contact layer 18, an insulating isolation layer 19, a conductive metal layer 20, and a passivation layer 201 which are sequentially stacked on the support substrate 11. The material of the supporting substrate 11 is alumina, and the surface of the laminated silicon oxide bonding layer 12 of the supporting substrate 11 and the surface of the laminated silicon oxide bonding layer 12 in contact with the supporting substrate 11 have a first oxygen plasma processing structure and a second oxygen plasma processing structure, respectively. The surface of the n-GaAs ohmic contact layer 18 is provided with a groove extending to the p-GaP ohmic contact layer 13, the insulating isolation layer 19 covers the surface of the p-GaP ohmic contact layer 13 exposed by the groove and the insulating isolation layer 19 extends to the n-GaAs ohmic contact layer 18, the conductive metal layer 20 is positioned on the insulating isolation layer 19 and the conductive metal layer 20 is communicated with the p-GaP ohmic contact layer 13. The p-electrode 2 is laminated on the conductive metal layer 20. The passivation layer 201 covers the surface of the epitaxial wafer 1, and through holes corresponding to the n-electrode 3 and the p-electrode 2 are left in the passivation layer 201.
The structures of the support substrate 11 and the silicon oxide bonding layer 12 shown in fig. 2 are the same as the structures of the support substrate 11 and the silicon oxide bonding layer 12 shown in fig. 1, respectively, and thus are not described in detail here.
For ease of understanding, some of the hierarchy in the red diode chip is provided in detail below.
Optionally, the thickness of the p-GaP ohmic contact layer 13 is 5-8 μm.
The thickness of the p-GaP ohmic contact layer 13 can meet the requirement of preparing the p electrode 2 on the p-GaP ohmic contact layer 13, and the p-GaP ohmic contact layer 13 with the thickness within the range has better overall quality, thereby ensuring the stable preparation and connection of the p electrode 2 and ensuring the luminous efficiency of the finally obtained red light emitting diode.
Optionally, the thickness of the p-AlInP limiting layer 14 is 280-400 nm. The obtained red light-emitting diode chip has better quality.
Optionally, the thickness of the AlInP transition layer 202 is 250-350 nm. The obtained red light-emitting diode chip has better quality.
Illustratively, the first AlGaInP waveguide layer 203 has a thickness of 50 to 90 nm.
Alternatively, the active layer 15 is provided to include a plurality of periodically alternately grown AlGaInP well layers and AlGaInP barrier layers in which Al has a different composition.
Illustratively, the overall thickness of the active layer 15 may be 150-200 nm.
Optionally, the second AlGaInP waveguide layer 204112 has a thickness of 40-90 um.
Optionally, the thickness of the n-AlInP limiting layer 16 is 200-500 nm. The obtained red light-emitting diode chip has better quality.
Illustratively, the thickness of the n-AlGaInP window layer 17 is 0.4-0.8 um. Sufficient light emitting space can be provided.
Optionally, the thickness of the n-AlGaInP current spreading layer is 1-2 um. The obtained red light-emitting diode chip has better quality.
Illustratively, the thickness of the n-AlGaInP window layer 17 is 1-2 um. The obtained red light-emitting diode chip has better quality.
Illustratively, the surface of the n-GaAs ohmic contact layer 18 is provided with a groove extending to the p-GaP ohmic contact layer 13, and the epitaxial wafer 1 further comprises an insulating isolation layer 19 and a conductive metal layer 20. The insulating isolation layer 19 covers the surface of the p-GaP ohmic contact layer 13 exposed by the groove and the insulating isolation layer 19 extends to the n-GaAs ohmic contact layer 18, the conductive metal layer 20 is positioned on the insulating isolation layer 19 and the conductive metal layer 20 is communicated with the p-GaP ohmic contact layer 13. The p-electrode 2 is laminated on the conductive metal layer 20.
The surface of the n-GaAs ohmic contact layer 18 is provided with a groove extending to the p-GaP ohmic contact layer 13, so that the growth and the use of the p electrode 2 on the p-GaP ohmic contact layer 13 can be realized. The insulating isolation layer 19 covers the surface of the p-GaP ohmic contact layer 13 exposed by the groove, so that the p-GaP ohmic contact layer 13 can be protected on one hand, the insulating isolation layer 19 extends to the n-GaAs ohmic contact layer 18 on the other hand, and the p electrode 2 is connected to the p-GaP ohmic contact layer 13 through the conductive metal layer 20 covering the insulating isolation layer 19, so that the normal use of the p electrode 2 can be ensured, the distance between the p electrode 2 and the n electrode 3 in the direction vertical to the surface of the substrate is reduced, the n electrode 3 and the p electrode 2 can be conveniently manufactured synchronously, and the manufacturing cost is reduced.
It should be noted that the bottom surface of the recess may be the surface of the p-GaP ohmic contact layer 13 exposed by the recess, and the sidewall of the recess is a surface of the recess not parallel to the surface of the support substrate 11. The surface of the support substrate 11 is a surface of the support substrate 11 for stacking epitaxial structures.
Optionally, an included angle between the side wall of the groove and the surface of the support substrate 11 is 40-50 °.
The included angle between the side wall of the groove and the surface of the supporting substrate 11 is in the above range, so that the side wall of the groove can be guaranteed to have a good supporting effect on the insulating isolation layer 19, the insulating isolation layer 19 can be guaranteed to cover the whole side wall of the groove, and the use stability of the red light diode chip is improved.
Illustratively, the material of the insulating spacer layer 19 is SixN。
The material of the insulating spacer layer 19 is SixAnd N has good high dielectric constant and insulating property, effectively avoids the possibility of electric leakage of the electrode and the pn junction, ensures the stable use of the red light diode chip, effectively reduces the possibility of electric leakage, and improves the reliability of the red light diode chip.
Optionally, the material of the insulating spacer layer 19 is SixOn the premise of N, the thickness of the insulating isolation layer 19 can be 300-500 nm.
The thickness of the insulating isolation layer 19 is within the above range, so that the probability of pn junction leakage and the possibility of contact between the p electrode 2 and the n-GaAs ohmic contact layer 18 can be effectively avoided, and the use stability of the red light diode chip is improved.
Alternatively, the maximum distance of the p-electrode 2 from the support substrate 11 is equal to the maximum distance of the n-electrode 3 from the support substrate 11.
The maximum distance from the p electrode 2 to the supporting substrate 11 is equal to the maximum distance from the n electrode 3 to the supporting substrate 11, so that the height difference between the p electrode 2 and the n electrode 3 is avoided, the n electrode 3 and the p electrode 2 can be synchronously prepared under the condition that the n electrode 3 and the p electrode 2 need to be prepared, the consistency of the quality of the n electrode 3 and the p electrode 2 is ensured, and better consistency and integrity can be achieved when photoetching patterns are made on the n electrode 3 and the p electrode 2.
In the case where the maximum distance from the p-electrode 2 to the supporting substrate 11 is equal to the maximum distance from the n-electrode 3 to the supporting substrate 11, the p-electrode 2 may be formed on the insulating spacer 19 covering the n-GaAs ohmic contact layer 18, and the n-electrode 3 may be formed on the n-GaAs ohmic contact layer 18.
Illustratively, the conductive metal layer 20 may include a first sublayer 2001 and a second sublayer 2002 stacked in sequence. The first sublayer 2001 is an Au/AuZn/Au structure laminated on the p-GaP ohmic contact layer 13, and the second sublayer 2002 includes a Ti/Pt/Ti structure laminated on the first sublayer 2001 and the insulating spacer layer 19.
The first sublayer 2001 is made of the above materials, the first sublayer 2001 has good stability and can ensure good ohmic contact with the p-GaP ohmic contact layer 13, and the second sublayer 2002 has good viscosity and conductivity by adopting a Ti/Pt/Ti structure, so that current can be stably transmitted to the p electrode 2.
It should be noted that the Au/AuZn/Au structure includes a first Au metal layer, an AuZn metal layer, and a second Au metal layer sequentially stacked on the p-GaP ohmic contact layer 13, and the Ti/Pt/Ti structure includes a first Ti metal layer, a Pt metal layer, and a second Ti metal layer sequentially stacked on the first sublayer 2001.
Optionally, the thicknesses of the first Au metal layer, the AuZn metal layer and the second Au metal layer may be 45-55 nm, 190-210 nm and 280-310 nm, respectively. The quality and stability of the first sublayer 2001 can be ensured.
Illustratively, the thicknesses of the first Ti metal layer, the Pt metal layer and the second Ti metal layer can be respectively 45-55 nm, 480-520 nm and 18-22 nm. The quality and stability of the second sublayer 2002 can be guaranteed.
To facilitate understanding, fig. 3 is provided here, and fig. 3 is a top view of the flip-chip red light emitting diode chip provided in the embodiment of the disclosure, and referring to fig. 3, it can be seen that, in the conductive metal layer 20, an orthographic projection of the first sub-layer 2001 on the surface of the substrate may be in a circular shape, the second sub-layer 2002 includes a first strip portion 2002a and a second strip portion 2002b, one end of each of the first strip portion 2002a and the second strip portion 2002b is connected to the first sub-layer 2001, and the other end of each of the first strip portion 2002a and the second strip portion 2002b is spaced apart from each other at a portion of the insulating isolation layer 19 covering the n-GaAs ohmic contact layer 18. The p-electrode 2 may include two p-pads spaced apart from each other at the other ends of the first strip portion 2002a and the second strip portion 2002 b. The n-electrode 3 may include an n-pad 3001 and two fingers 3002 having end portions corresponding to the two p-pads, respectively.
The n electrode 3 and the p electrode 2 respectively adopt the structures, so that the light-emitting uniformity of the finally obtained red light diode chip can be improved.
Illustratively, the p-electrode 2 may comprise Ti/Al/Ti/Al/Ti/Pt/Ni/Sn/Au. The quality of the p-electrode 2 can be ensured to be better. And the increase of the Ni metal layer and the Sn metal layer in the p electrode 2 can control the cladding property of the p electrode 2 to be better, and can also facilitate wire bonding of the electrode.
Optionally, the thicknesses of the metal layers in the structure of Ti/Al/Ti/Al/Ti/Pt/Ni/Sn/Au in the p-electrode 2 can respectively correspond to 90-110 nm, 280-320 nm, 450-550 nm, 3-5 μm and 5-10 nm. The quality of the obtained p-electrode 2 can be ensured to be better and more stable.
Illustratively, the n-electrode 3 includes Au/AuGeNi/Au/Pt/Au. The quality of the n-electrode 3 can be ensured to be better.
In other implementations provided by the present disclosure, the material of the electrode may also include one or more of Cr, Au, Ge, Ni, which is not limited by the present disclosure.
Fig. 4 is a flowchart of a method for manufacturing a flip-chip red led chip according to an embodiment of the disclosure, and referring to fig. 4, the method for manufacturing a red led chip includes:
s101: a supporting substrate and an epitaxial structure are provided, wherein the supporting substrate is made of aluminum oxide. The epitaxial structure comprises a growth substrate, and an n-GaAs ohmic contact layer, an n-AlGaInP window layer, an n-AlInP limiting layer, an active layer, a p-AlInP limiting layer, a p-GaP ohmic contact layer and a silicon oxide bonding layer which are sequentially stacked on the growth substrate.
S102: and respectively forming a first oxygen plasma processing structure and a second oxygen plasma processing structure on the surface of the support substrate and the surface of the silicon oxide bonding layer.
S103: the bonding support substrate and the silicon oxide bonding layer have surfaces with oxygen plasma-treated structures.
S104: and removing the growth substrate.
S105: and forming a p electrode on one surface of the supporting substrate far away from the n-GaAs ohmic contact layer.
S106: and forming a p electrode on the surface of the p-GaP ohmic contact layer and forming an n electrode on the surface of the n-GaAs ohmic contact layer.
The technical effect of the method for manufacturing the red light emitting diode chip shown in fig. 4 can refer to the technical effect of the structure of the red light emitting diode chip shown in fig. 1, and therefore, the technical effect of the method for manufacturing the red light emitting diode epitaxial wafer in fig. 4 is not described herein again.
The structure of the red led chip after step S106 is executed can refer to fig. 1.
Optionally, step S102 includes: and controlling the oxygen plasma to process the surface of the supporting substrate and the surface of the silicon oxide bonding layer under the conditions that the temperature is 20-150 ℃ and the power is 30-150 w. So as to form a first oxygen plasma processing structure and a second oxygen plasma processing structure on the surface of the support substrate and the surface of the silicon oxide bonding layer respectively. And because the power is lower, the oxygen plasma can not cause damage to the surfaces of the supporting substrate and the silicon oxide bonding layer. And the bonding stability of the finally obtained red light diode chip is ensured.
For example, in step S103, the supporting substrate and the silicon oxide bonding layer may be bonded at 300-500 ℃ and 1800-2000 pa. The bonding stability between the two can be improved.
Fig. 5 is a flowchart of another method for manufacturing a flip-chip red led chip according to an embodiment of the disclosure, and referring to fig. 5, the method for manufacturing a red led chip includes:
s201: a supporting substrate and an epitaxial structure are provided, wherein the supporting substrate is made of aluminum oxide. The epitaxial structure comprises a growth substrate, and a GaInP cut-off layer, an n-GaAs ohmic contact layer, an n-AlGaInP window layer, an n-AlGaInP current blocking layer, an n-AlInP limiting layer, a second AlGaInP waveguide layer, an active layer, a first AlGaInP waveguide layer, a p-AlInP limiting layer, a p-GaP ohmic contact layer and a silicon oxide bonding layer which are sequentially stacked on the growth substrate.
Alternatively, the material of the growth substrate may be gallium arsenide. The obtained flip-chip red light diode chip is convenient to obtain, and the growth quality of the obtained flip-chip red light diode chip is good.
In step S201, the growth of each layer may be as follows:
illustratively, the growth conditions of the GaInP layer include: the growth temperature is 650-670 ℃, the thickness is 150-300nm, the V/III is 20-30, and the growth rate is 0.5-0.8 nm/s.
Optionally, the growth conditions of the n-GaAs ohmic contact layer include: the growth temperature is 650-670 ℃, the thickness is 150-300nm, the V/III is 20-30, and the growth rate is 0.5-0.8 nm/s.
Optionally, the growth conditions of the n-AlGaInP current spreading layer and the n-AlGaInP ohmic contact layer include: the growth temperature is 670-.
Optionally, the n-AlInP confinement layer growth conditions include: the growth temperature is 670-.
Optionally, the first AlGaInP waveguide layer growth conditions include: the growth temperature is 670-.
Optionally, the growth conditions of the AlGaInP well layer and the AlGaInP barrier layer in the active layer include: the growth temperature is 650-660 ℃, the thickness is 20-22nm, the V/III is 40-50, and the growth rate is 1-2 nm/s. An active layer of good quality can be obtained.
Optionally, the growth conditions for the second AlGaInP waveguide layer include: the growth temperature is 670-.
Optionally, the growth conditions of the AlInP transition layer and the p-AlInP confinement layer include: the growth temperature is 670-.
Optionally, between the silicon oxide bonding layers formed on the p-GaP ohmic contact layer, the method for preparing a flip-chip red light diode chip further comprises: and carrying out wet coarsening treatment on the surface of the p-GaP ohmic contact layer.
The diffused reflection at the surface of the p-GaP ohmic contact layer can be reduced, and the connection stability between the p-GaP ohmic contact layer and the silicon oxide bonding layer can be improved.
Illustratively, the growing process of the silicon oxide bonding layer may include: depositing a silicon oxide film layer on the p-GaP ohmic contact layer; and polishing the surface of the silicon oxide film layer to reduce the thickness of the silicon oxide film layer and improve the surface flatness of the silicon oxide film layer to obtain the silicon oxide bonding layer. The connection stability between the resulting support substrate and the silicon oxide bonding layer can be improved.
Optionally, step S201 may further include: and polishing and thinning the surface of the growth substrate, which is far away from the silicon oxide bonding layer.
The surface flatness of the growth substrate can be improved, so that subsequent stable bonding is facilitated. The thickness of the growth substrate can be reduced while polishing, and the subsequent removal of the growth substrate can be facilitated.
The step of polishing and thinning the growth substrate can be performed before polishing the silicon oxide film layer, and the surface flatness of the obtained silicon oxide bonding layer can be improved. And after the growth substrate is polished and before the silicon oxide film layer is polished, a blue film can be attached to one surface of the growth substrate, which is far away from the silicon oxide film layer. The blue film plays a supporting and buffering role.
S202: and respectively forming a first oxygen plasma processing structure and a second oxygen plasma processing structure on the surface of the support substrate and the surface of the silicon oxide bonding layer.
S203: the bonding support substrate and the silicon oxide bonding layer have surfaces with oxygen plasma-treated structures.
S204: and removing the growth substrate and the GaInP cut-off layer.
The growth substrate and the GaInP stop layer can be removed by wet etching.
S205: and preparing a groove extending from the n-GaAs ohmic contact layer to the p-GaP ohmic contact layer by a photoetching process.
S206: and forming an n electrode on the n-GaAs ohmic contact layer, and forming a first sub-layer of the metal conducting layer on the p-GaP ohmic contact layer.
The n electrode and the first sublayer can be formed by vapor deposition and matching with a photoetching process.
Step S206 may further include: and annealing the n electrode and the first sublayer. And good ohmic contact between the epitaxial structure and the substrate can be ensured.
S207: and forming an insulating isolation layer, wherein the insulating isolation layer covers the surface of the p-GaP ohmic contact layer exposed by the groove and extends to the n-GaAs ohmic contact layer, and a second sub-layer of the metal conducting layer and the p electrode are sequentially formed on the insulating isolation layer.
Illustratively, the material of the insulating spacer layer is SixOn the premise of N, the growth conditions of the insulating isolation layer comprise: the temperature is 280-320 ℃, the power is 50-120W, and the pressure is 50-150 pa.
When the growth condition of the insulating isolation layer is within the above range, the insulating property of the obtained insulating isolation layer can be controlled to be higher.
Optionally, the material of the insulating isolation layer is SixOn the premise of N, the growth conditions of the insulating isolation layer further comprise: SiH of 100-300 sccm is passed into a reaction chamber with a pressure of 100pa41400-1600 sccm of N 215 to 25 sccm NH3To grow an insulating isolation layer. The obtained insulating isolation layer has better quality.
S208: and growing a passivation layer, wherein the passivation layer covers the surface of the epitaxial wafer and is provided with through holes corresponding to the n electrode and the p electrode.
The structure of the red led chip after step S208 is completed can be seen in fig. 2.
As required by those skilled in the art, after the step S208 is performed, the supporting substrate may be thinned and the flip-chip red diode chip may be subjected to a splitting process. The present disclosure is not so limited.
It should be noted that, in the embodiment of the present disclosure, a VeecoK 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition) apparatus is used to realize the growth of the epitaxial layer of the light emitting diode. By using high-purity H2(Hydrogen) or high purity N2(Nitrogen) or high purity H2And high purity N2The mixed gas of (2) is used as a carrier gas, high-purity NH3As N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as gallium source, trimethyl indium (TMIn) as indium source, silane (SiH4) as N-dopant, trimethyl aluminum (TMAl) as aluminum source, magnesium diclocide (CP)2Mg) as P-dopant.
Although the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims (10)

1. A flip-chip red light diode chip is characterized in that the flip-chip red light diode chip comprises an epitaxial wafer, a p electrode and an n electrode,
the epitaxial wafer comprises a supporting substrate, and a silicon oxide bonding layer, a p-GaP ohmic contact layer, a p-AlInP limiting layer, an active layer, an n-AlInP limiting layer, an n-AlGaInP window layer and an n-GaAs ohmic contact layer which are sequentially laminated on the supporting substrate,
the material of the supporting substrate is aluminum oxide, the surface of the silicon oxide bonding layer which is laminated on the supporting substrate and the surface of the silicon oxide bonding layer which is in contact with the supporting substrate are respectively provided with a first oxygen plasma processing structure and a second oxygen plasma processing structure,
the p electrode is communicated with the p-GaP ohmic contact layer, and the n electrode is communicated with the n-GaAs ohmic contact layer.
2. The flip-chip red led chip of claim 1, wherein the surface of the p-GaP ohmic contact layer contacting the silicon oxide bonding layer has a roughened structure.
3. The flip-chip red diode chip of claim 1, wherein the n-GaAs ohmic contact layer has a recess on its surface extending to the p-GaP ohmic contact layer, the epitaxial wafer further comprises an insulating isolation layer and a conductive metal layer,
the insulating isolation layer covers the surface of the p-GaP ohmic contact layer exposed by the groove and extends to the n-GaAs ohmic contact layer, the conductive metal layer is positioned on the insulating isolation layer and is communicated with the p-GaP ohmic contact layer,
the p-electrode is laminated on the conductive metal layer.
4. The flip-chip red diode chip of claim 3, wherein an included angle between the sidewall of the recess and the surface of the supporting substrate is 40-50 °.
5. The flip-chip red diode chip of claim 3, wherein the insulating isolation layer is made of SixN。
6. The flip-chip red diode chip as claimed in any one of claims 3 to 5, wherein the maximum distance from the p-electrode to the supporting substrate is equal to the maximum distance from the n-electrode to the supporting substrate.
7. The flip-chip red diode chip as claimed in any one of claims 3 to 5, wherein the conductive metal layer comprises a first sub-layer and a second sub-layer stacked in sequence,
the first sub-layer is an Au/AuZn/Au structure laminated on the p-GaP ohmic contact layer, and the second sub-layer comprises a Ti/Pt/Ti structure laminated on the first sub-layer and the insulating isolation layer.
8. A preparation method of a flip-chip red light diode chip is characterized by comprising the following steps:
providing a support substrate and an epitaxial structure, wherein the support substrate is made of aluminum oxide;
the epitaxial structure comprises a growth substrate, and an n-GaAs ohmic contact layer, an n-AlGaInP window layer, an n-AlInP limiting layer, an active layer, a p-AlInP limiting layer, a p-GaP ohmic contact layer and a silicon oxide bonding layer which are sequentially stacked on the growth substrate;
forming a first oxygen plasma processing structure and a second oxygen plasma processing structure on the surface of the supporting substrate and the surface of the silicon oxide bonding layer respectively;
bonding the support substrate and the surface of the silicon oxide bonding layer with an oxygen plasma treatment structure;
removing the growth substrate;
forming a p electrode on one surface of the supporting substrate far away from the n-GaAs ohmic contact layer;
and forming a p electrode on the surface of the p-GaP ohmic contact layer, and forming an n electrode on the surface of the n-GaAs ohmic contact layer.
9. The method of claim 8, wherein the chip comprises an insulating isolation layer and a conductive metal layer, the insulating isolation layer covers a portion of the p-GaP ohmic contact layer and extends to the n-GaAs ohmic contact layer, the conductive metal layer is on the insulating isolation layer and communicates with the p-GaP ohmic contact layer, the p-electrode is stacked on the conductive metal layer, and the insulating isolation layer is made of SixN，
The growth conditions of the insulating isolation layer include: the temperature is 280-320 ℃, the power is 50-120W, and the pressure is 50-150 pa.
10. The method of claim 8, wherein before bonding the support substrate to the surface of the silicon oxide bonding layer having the oxygen plasma treated structure, the method further comprises:
and thinning the thickness of the supporting substrate and the silicon oxide bonding layer.
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