CN104779339B - Upside-down mounting high voltage LED chip and preparation method thereof - Google Patents
Upside-down mounting high voltage LED chip and preparation method thereof Download PDFInfo
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- CN104779339B CN104779339B CN201510022007.8A CN201510022007A CN104779339B CN 104779339 B CN104779339 B CN 104779339B CN 201510022007 A CN201510022007 A CN 201510022007A CN 104779339 B CN104779339 B CN 104779339B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 96
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 55
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000010438 heat treatment Methods 0.000 claims abstract description 28
- 230000008021 deposition Effects 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 13
- 230000005611 electricity Effects 0.000 claims description 10
- 238000004080 punching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 110
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052718 tin Inorganic materials 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 239000000741 silica gel Substances 0.000 description 7
- 229910002027 silica gel Inorganic materials 0.000 description 7
- 229910052733 gallium Inorganic materials 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000006071 cream Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N 1,4a-dimethyl-7-propan-2-yl-2,3,4,4b,5,6,10,10a-octahydrophenanthrene-1-carboxylic acid Chemical compound C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- -1 gallium nitrides Chemical class 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
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- 239000002344 surface layer Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
- Led Device Packages (AREA)
Abstract
Upside-down mounting high voltage LED chip and preparation method thereof, upside-down mounting high voltage LED chip includes substrate and M chip, each chip includes n type gallium nitride layer, luminescent layer, p-type gallium nitride layer, reflecting layer, the first insulating barrier, P leads electrode, N leads electrode and PN lead connection electrodes, and radiating groove is formed on P leads electrode and/or N leads electrode and/or PN lead connection electrodes；Second insulating barrier be covered on the surface of P leads electrode, PN leads connection electrode and N lead electrodes and its between the first surface of insulating layer on, and fill the groove that completely radiates, heat emission hole is formed on second insulating barrier, the projection of heat emission hole in the horizontal plane is located in radiating groove；The full heating column of filling in second insulating layer deposition N pads and P pads, heat emission hole, heating column is connected with the P pads and N pads.The present invention sets thermal column between P pads, N pads and lead electrode so that faster, heating is few for LED upside-down mounting high-voltage chips radiating rate.
Description
Technical field
The invention belongs to semiconductor optoelectronic chip technology field, more particularly to a kind of upside-down mounting high voltage LED chip and its preparation
Method.
Background technology
With the continuous improvement of LED (light emitting diode) luminous efficiency, LED turn into recent years most valued light source it
One.With the development of LED techniques, directly had been carried out using the LED of high drive.The efficiency of high-voltage LED is better than general tradition
Low-voltage LED, being mainly due to low current, multiunit design uniformly can open current spread, and high-voltage LED can be realized
Direct voltage drives, so as to save the cost of LED drivings.
Existing high voltage LED chip has the problem of power increase, radiating hardly possible and reliability are reduced, and is asked for these
Topic, industry has gone out further improvement to the structure of high voltage LED chip.For example, number of patent application is 201310465534.7
Chinese invention patent application discloses a kind of LED upside-down mountings high-voltage chip and preparation method thereof, and it is on the second insulating barrier of chip
Heat, substrate is diffused into by AuSn or tin cream welding by the two big pad of covering from pad.Above-mentioned LED upside-down mountings high-voltage chip master
Will by heat loss through conduction, but its second insulating barrier be made of organic silica gel and thickness be more than 6um, due to the second insulating barrier compared with
Thick and thermal conductivity factor is relatively low, so heat is still difficult to export, heat, which is gathered on chip, can influence chip reliability, increase
Light decay and reduction chip life-span, the heat conduction of LED high-voltage chip and integrity problem are not still resolved.
The content of the invention
It is an object of the invention to provide a kind of upside-down mounting high voltage LED chip that can improve heat dissipation problem and preparation method thereof.
To achieve these goals, the present invention takes following technical solution：
Upside-down mounting high voltage LED chip, including substrate and M chip being mutually independent on the substrate surface, M
>=2, each chip includes n type gallium nitride layer, luminescent layer and the p-type gallium nitride being grown on successively on the substrate surface
Layer, the n type gallium nitride layer, luminescent layer and p-type gallium nitride layer constitute the epitaxial layer of chip, the p-type nitridation of each chip
Reflecting layer is formed with gallium layer；Cover the epitaxial layer of each chip and reflect the first insulating barrier of layer surface；With the first core
The P lead electrodes of the reflecting layer electrical connection of piece；The N lead electrodes electrically connected with the n type gallium nitride layer of M chips；Successively by i-th
The PN lead connection electrodes that the n type gallium nitride layer of chip and the reflecting layer of i+1 chip are electrically connected in series, i=1 ..., M-
1, the PN lead connection electrodes for the chip that each two is serially connected are mutually independent, in the P leads electrode and/or N leads
The annular radiating groove for being through to first surface of insulating layer is formed on electrode and/or PN lead connection electrodes；Second is exhausted
Edge layer, second insulating barrier is covered on the surface of P leads electrode, PN leads connection electrode and N lead electrodes and P leads electricity
On the first surface of insulating layer between pole, PN leads connection electrode and N lead electrodes, and the full radiating groove is filled, it is described
Formed on second insulating barrier and be through to dissipating for the P leads electrode and/or N leads electrode and/or PN lead connection electrodes surface
Hot hole, the projection of the heat emission hole in the horizontal plane is located in the radiating groove；Be deposited on second insulating barrier and with
The N pads of the N leads electrode connection；The P pads for being deposited on second insulating barrier and being connected with the P leads electrode；
The heating column of the full heat emission hole of filling, the heating column is connected with the P pads and N pads.
The thermal conductivity factor of the heating column of the upside-down mounting high voltage LED chip of the present invention is not less than 100W/ (mK).
The full heat emission hole formation heating column of N pads and P pad portions filling of the upside-down mounting high voltage LED chip of the present invention.
The upside-down mounting high voltage LED chip of the present invention also includes：Through the epitaxial layer, expose the groove of the substrate surface,
Each chip is isolated by the groove；P-type gallium nitride, luminescent layer through each chip is until the N of n type gallium nitride layer surface
Electrode hole；First insulating barrier fill be formed with the groove and N electrode hole, the first insulating barrier of each chip with it is described
The connected p-type contact hole of reflection layer surface and the N-type contact hole being connected with the n type gallium nitride layer surface；The P leads electrode
Be deposited on the insulating barrier of part first of the first chip surface and p-type contact hole in, by the p-type contact hole on the first chip with
The reflecting layer electrical connection of first chip；The N leads electrode deposition is on the insulating barrier of part first of M chip surfaces and N-type
Electrically connected in contact hole, by the N-type contact hole on M chips with the n type gallium nitride layer of M chips；The PN leads connection
Electrode deposition is on the insulating barrier of part first of adjacent chips and in N-type contact hole, p-type contact hole；On second insulating barrier
Be formed with the N lead electrode contact holes that are connected with the N lead electrode surfaces on M chips and with the P leads on the first chip
The P lead electrode contacts hole of electrode surface connection；The N pads are deposited on second insulating barrier and the N leads electrode
It is connected in contact hole with the N leads electrode；The P pads are deposited on second insulating barrier and the P leads electrode connects
It is connected in contact hole with the P leads electrode.
First insulating barrier of the upside-down mounting high voltage LED chip of the present invention is along chip perimeter side wall and substrate attaching.
Second insulating barrier of the upside-down mounting high voltage LED chip of the present invention is fitted along chip perimeter side wall with the first insulating barrier, often
Individual chip is fully wrapped around by first insulating barrier and the second insulating barrier successively.
Covered with tin paste layer on the N pads and P bond pad surfaces of the upside-down mounting high voltage LED chip of the present invention.
The thickness of the tin paste layer of the upside-down mounting high voltage LED chip of the present invention is 50~100um.
A kind of preparation method of upside-down mounting high voltage LED chip, comprises the following steps：
Step 1: providing substrate, n type gallium nitride layer is grown on the substrate surface, hair is grown on n type gallium nitride layer
Photosphere, the growing P-type gallium nitride layer on luminescent layer, the n type gallium nitride layer, luminescent layer and p-type gallium nitride layer constitute each core
The epitaxial layer of piece；
Step 2: covering reflecting layer on p-type gallium nitride layer；
Step 3: form groove on epitaxial layer, groove depth is to substrate surface and exposes substrate, make the epitaxial layer
The first chip being mutually independent is formed to M chips, M is the integer more than or equal to 2；Run through in the formation of each chip surface
P-type gallium nitride layer, luminescent layer are until the N electrode hole of n type gallium nitride layer surface；
Step 4: covering the first insulating barrier, the first insulating barrier filling groove and N electrode on the surface in epitaxial layer and reflecting layer
Hole；
Step 5: in the punching of the first surface of insulating layer, forming the p-type contact hole for being deep to reflection layer surface and being deep to N-type nitrogen
Change the N-type contact hole of gallium layer surface；
Connect Step 6: forming the P leads electrode with wiring pattern, N leads electrode and PN leads on the first insulating barrier
P lead electrodes are deposited on receiving electrode, the insulating barrier of part first on the first chip surface and in p-type contact hole, in M cores
N lead electrodes are deposited on the insulating barrier of part first on piece surface and in N-type contact hole, it is exhausted in the part first of adjacent chips
PN lead connection electrodes are deposited in edge layer and in N-type contact hole, p-type contact hole, PN leads connection electrode is successively by the i-th chip
N type gallium nitride layer and the reflecting layer of i+1 chip be electrically connected in series, i=1 ..., M, wherein each two are serially connected
The PN lead connection electrodes of chip are mutually independent；Connected in the P leads electrode and/or N leads electrode and/or PN leads
The annular radiating groove for being through to first surface of insulating layer is formed on electrode；
Step 7, forms the second insulating barrier, the second insulating barrier covering P leads electrode, N leads electrode and PN leads connection electricity
The surface of pole and the table of the first insulating barrier between P leads electrode, N leads electrode and PN lead connection electrodes
Face, and fill the groove that completely radiates；
Step 8: the N lead electrode contacts being connected in the formation of the second insulating barrier with the N lead electrode surfaces on M chips
Hole, the P lead electrode contact holes being connected with the P lead electrode surfaces on the first chip and it is through to P leads electrode and/or N
Lead electrode and/or the heat emission hole on PN lead connection electrodes surface, it is recessed that the projection of the heat emission hole in the horizontal plane is located at radiating
In groove；
Step 9: N pads are formed on the surface of insulating layer of part second and in N lead electrode contacts hole, in part second
P pads are formed on surface of insulating layer and in P lead electrode contacts hole, N pads pass through N lead electrode contact holes and and N leads electricity
Pole is in contact, and P pads are by P lead electrode contact holes and P lead contact electrodes, the interior filling heating column of the heat emission hole, institute
Heating column is stated with the P pads and N pads to be connected.
The preparation method of the upside-down mounting high voltage LED chip of the present invention, N pads and the full heat emission hole formation of P pad portions filling are led
Plume.
From above technical scheme, the present invention P pads and N pads and lead electrode and/or lead connection electrode it
Between heating column is set, heating column is in contact with lead electrode and/or lead connection electrode and P pads, N pads, and heating column can be with
Directly heat derives that luminescent layer is produced are to P pads and N pads, it is not necessary to again by the second insulating barrier so that high-voltage chip dissipates
Faster, more preferably, heating is few for radiating effect for thermal velocity；And P pads and N pad upside-down mountings contact area are big, and luminous leafing substrate
Closely, can be easily by heat derives.In addition, the second insulating barrier is preferred to use the material for possessing certain elasticity, it can absorb
The thermal stress for causing LED high-voltage chip internal to damage, so as to ensure the reliability of LED high-voltage chip operation.
Brief description of the drawings
Fig. 1 is the structural representation of the embodiment of the present invention；
Fig. 2 is the structural representation of high voltage LED chip of embodiment of the present invention formation epitaxial layer；
Fig. 3 is the structural representation in high voltage LED chip formation reflecting layer；
Fig. 4 a are high voltage LED chip formation groove and the structural representation in N electrode hole；
Fig. 4 b are the top view for the hole high voltage LED chip to form groove and N electrode；
Fig. 5 is the structural representation of high voltage LED chip the first insulating barrier of formation；
Fig. 6 a are the structural representation of high voltage LED chip formation p-type contact hole and N-type contact hole；
Fig. 6 b are the top view for the high voltage LED chip to form p-type contact hole and N-type contact hole；
Fig. 7 a are the structural representation of high voltage LED chip formation N leads electrode, PN leads connection electrode and P lead electrodes；
Fig. 7 b are the top view for the high voltage LED chip to form N leads electrode, PN leads connection electrode and P lead electrodes；
Fig. 8 is the structural representation of high voltage LED chip the second insulating barrier of formation；
Fig. 9 a are the structural representation in high voltage LED chip formation N lead electrode contact holes and P lead electrode contacts hole；
Fig. 9 b are the top view for the high voltage LED chip to form N lead electrode contact holes and P lead electrode contacts hole.
The embodiment of the present invention is described in more detail below in conjunction with accompanying drawing.
Embodiment
As shown in figure 1, the present invention upside-down mounting high voltage LED chip include substrate 1 and on the surface of substrate 1 each other
The independent M chip 10 of insulation, M is the integer more than or equal to 2, and each chip 10 includes the N being grown on successively on the surface of substrate 1
Reflecting layer 15, n type gallium nitride layer are covered on type gallium nitride layer 11, luminescent layer 12 and p-type gallium nitride layer 13, p-type gallium nitride layer 13
11st, luminescent layer 12 and p-type gallium nitride layer 13 constitute the epitaxial layer 2 of each chip.Each chip is kept apart by groove 3, groove 3
Depth is to the surface of substrate 1.The first insulating barrier 16 is covered in the epitaxial layer 2 of each chip and the surface of reflecting layer 15.First insulating barrier
The P leads electrode 31 electrically connected with the reflecting layer 15 of the first chip is formed on 16, is electrically connected with the n type gallium nitrides layers 11 of M chips
The N leads electrode 32 connect and the PN for being sequentially connected in series the reflecting layer of the n type gallium nitride layer of a chip and an adjacent chip
Lead connection electrode 33.Formed and be through on P leads electrode 31 and/or N leads electrode 32 and/or PN leads connection electrode 33
The annular radiating groove 65 on the surface of the first insulating barrier 16.In P leads electrode 31, PN leads connection electrode 33 and N lead electrodes
The surface of the first insulating barrier 16 on 32 surface and between P leads electrode, PN leads connection electrode and N lead electrodes
On covered with the second insulating barrier 22, the second insulating barrier 22 fills completely radiating groove 65, is formed to be through on the second insulating barrier 22 and drawn
Line electrode and/or the heat emission hole 45 on lead connection electrode surface, the heat emission hole 45 is in horizontal plane (perpendicular to the plane of its axis)
On projection be located at radiating groove 65 in.The outward flange of heat emission hole is located in radiating recess region, also including its outward flange just
On the inward flange of radiating groove.The N pads 26 being connected with N leads electrode 32 are formed on second insulating barrier 22 and are drawn with P
Heating column 55, the connecting lead wire electrode of heating column 55 and N pads 26 are filled with the P pads 27 that line electrode 31 is connected, heat emission hole 45
And P pads 27.
Below in conjunction with the accompanying drawings, the preparation method to the upside-down mounting high voltage LED chip of the embodiment of the present invention is illustrated, the preparation
Method comprises the following steps：
Step 1: as shown in Figure 2 there is provided substrate 1, the substrate 1 of the present embodiment is Sapphire Substrate, passes through MOCVD
(Metal-organic Chemical Vapor Deposition, metallo-organic compound chemical gaseous phase deposition) is in the table of substrate 1
Face growing epitaxial layers 2, the growth course of epitaxial layer 2 is followed successively by：In the superficial growth n type gallium nitride layer 11 of substrate 1, in N-type nitridation
Luminescent layer 12, the growing P-type gallium nitride layer 13 on luminescent layer 12 are grown on gallium layer 11；
Step 2: as shown in figure 3, covering reflecting layer 15 on p-type gallium nitride layer 13 using evaporation and photoetching process, this is anti-
The material for penetrating layer 15 can be aluminium, nickel, both silver-colored or above-mentioned any alloys；
Step 3: as shown in figures 4 a and 4b, by using ICP etch process to epitaxial layer, forming ditch on epitaxial layer
Groove 3, the depth of groove 3 to the surface of substrate 1, expose substrate 1, groove is set on epitaxial layer, makes the epitaxial layer formation each other
The first separate chip is to M chips, and M is the integer more than or equal to 2；Each chip 10 is performed etching, with each
The surface of chip 10 is formed through p-type gallium nitride layer 13, luminescent layer 12 until the N electrode hole 4 on 11 surface of n type gallium nitride layer, N electrode
The quantity in hole 4 can be multiple and is uniformly distributed in chip surface；
Step 4: as shown in figure 5, the surface covering first by sputtering or spraying coating process in epitaxial layer and reflecting layer is insulated
Layer 16, and the first insulating barrier 16 fills groove and N electrode hole simultaneously, the first insulating barrier 16 makes each chip mutually insulated；The
One thickness of insulating layer is 1um~2um, and its material can be aluminium nitride or silica or silicon nitride or alundum (Al2O3) or Prague
Reflecting layer DBR or silica gel or resin or acrylic acid, Bragg reflecting layer are silica SiO2With titanium dioxide TiO2Multilayer hand over
For structure；In addition, the first insulating layer material is also preferably organic silica gel, organic silica gel possesses high filling micron order in itself
Empty ability, can effectively fill groove and the cavity left by N electrode hole, reduce transmitting of such cavity to light formation, improve
Chip light emitting efficiency and prevent chip chamber from leaking electricity；First insulating barrier is along chip perimeter side wall and substrate attaching, by each core
Piece is fully wrapped around；
Step 5: as shown in figures 6 a and 6b, being punched using photoetching and etching technique on the surface of the first insulating barrier 16, each
P-type contact hole 5 and N-type contact hole 6 are etched on chip respectively, wherein, p-type contact hole 5 is deep to the surface of reflecting layer 15, and p-type connects
Reflecting layer 15 is exposed in the bottom of contact hole 5, and N-type contact hole 6 is deep to 11 surface of n type gallium nitride layer, and N-type nitrogen is exposed in the bottom of N-type contact hole 6
Change gallium layer 11；
Step 6: as shown in figs. 7 a and 7b, being formed by sputtering or evaporation process on the first insulating barrier 16 with cloth
P leads electrode 31, N leads electrode 32 and the PN leads connection electrode 33 of line pattern, wherein, the part on the first chip surface
P leads electrode 31 is deposited on first insulating barrier 16 and in p-type contact hole, i.e. P leads electrode 31 passes through the p-type on the first chip
Contact hole is electrically connected with the reflecting layer 15 of the first chip, on the first insulating barrier of part 16 on M chip surfaces and N-type connects
Deposition N leads electrode 32, i.e. N leads electrode 32 are nitrogenized by the N-type of the N-type contact hole on M chips and M chips in contact hole
Gallium layer 11 is electrically connected, and PN is deposited on the first insulating barrier of part 16 of adjacent chips and in N-type contact hole, p-type contact hole and is drawn
Line connection electrode 33, PN leads connection electrode 33 successively enters the reflecting layer of the n type gallium nitride layer of the i-th chip and i+1 chip
Row is electrically connected in series, i=1 ..., M, and the PN leads connection electrode 33 for the chip that each two is serially connected is to be mutually independent
's；
Form that to be through to first exhausted on P leads electrode 31 and/or N leads electrode 32 and/or PN leads connection electrode 33
The annular radiating groove 65 on the surface of edge layer 16；The closed loop shape of radiating groove can be triangle, circle, quadrangle etc., dissipate
Hot groove can be formed in P leads electrode, N leads electrode and PN lead connection electrodes simultaneously, or be formed in three
On one or two, the radiating groove 65 of the present embodiment is formed in PN leads connection electrode 33；
Step 7, as shown in figure 8, passing through spraying and photoetching process the second insulating barrier 22 of formation, the second insulating barrier 22 covering P
Lead electrode 31, the surface of N leads electrode 32 and PN leads connection electrode 33 and positioned at P leads electrode 31, N leads electrode 32
The surface of the first insulating barrier 16 between PN leads connection electrode 33, and fill the groove 65 that completely radiates；
When first insulating barrier is along chip perimeter side wall and substrate attaching, the second insulating barrier is exhausted along chip perimeter side wall and first
Edge layer is fitted；The thickness of second insulating barrier is 6~10um, and material can use organic silica gel, and organic silica gel is not absorb visible ray
The material of certain elasticity is composed and possessed, the thermal stress for causing inside of high-voltage chip to be damaged can be absorbed, so as to ensure high-voltage LED
The reliability of chip operation；Using with low solidification temperature (<200 DEG C) organic silica gel, it is adaptable to thermal Finite device；
Second insulating barrier 22 is fitted along chip perimeter side wall with insulating barrier, and each chip is fully wrapped around, not only helps tin cream Reflow Soldering
Technique, and prevent that tin cream climbs tin to cause electric leakage or short circuit during welding；
Step 8: as shown in figures 9 a and 9b, P lead electrode contacts hole 28 and N are etched on the surface of the second insulating barrier 22
Lead electrode contact hole 29 and the heat emission hole 45 for being through to the surface of PN leads connection electrode 33, the heat emission hole 45 is in horizontal plane
On projection be located at radiating the inner peripheral surface of groove 65 (using the plane parallel to substrate surface as horizontal plane), the position of heat emission hole with dissipate
The position of hot groove is corresponding, and the groove 65 that radiated in the present embodiment is formed in PN leads connection electrode 33, therefore heat emission hole pair
PN lead connection electrodes surface should be through to, when radiating groove is formed at P leads electrode, N leads electrode and PN leads connection electricity
On extremely, or in one or two being formed in three, heat emission hole also corresponds to and is through to P leads electrode, N leads electrode and PN
Lead connection electrode surface, or one or two being through in three surface；Wherein, P leads electrode contact hole 28 with
The table of N leads electrode 32 on the surface of P leads electrode 31 electrical connection on first chip, N lead electrode contacts hole 29 and M chips
Face is electrically connected；P lead electrode contacts hole 28 and N lead electrode contacts hole 29 can be multiple；
Step 9: manufacturing the N pads 26 and P pads 27 of mutually insulated using photoetching and evaporation coating technique, N pads 26 and P is welded
Disk 27 is symmetrical, and N pads 26 are covered on the surface of the second insulating barrier of part 22 and be filled in N lead electrodes with P pads 27
In contact hole and P lead electrode contacts hole, N pads 26 by N lead electrode contact holes with and M chips N leads electrode 32
It is in contact, P pads 27 are in contact by the P leads electrode 31 of P lead electrode contact holes and the first chip, meanwhile, the He of N pads 26
P pads 27 are partially filling up heat emission hole formation heating column 55 (Fig. 1).
In the present embodiment, heating column is formed by P pads and/or N pads filling heat emission hole, heating column and P pads and/or N
Pad is integrated, and heating column is identical with the material of P pads and/or N pads, but heating column can also be using other thermal conductivity factors not
Material less than 100W/ (mK) is made, and heating column is filled in heat emission hole, with PN leads connection electrode and P pads and/or N
Pad is in contact, and the heat that P pads and N pads are produced luminescent layer 12 by heating column 55 is directly exported by the first insulating barrier
To P pads and N pads, it is not necessary to again by the second insulating barrier so that high-voltage chip radiating rate faster, more preferably, send out by radiating effect
Heat is few.Simultaneously because the second insulating barrier is using the material for possessing certain elasticity, it, which can absorb, causes LED high-voltage chip internal to damage
Harmful thermal stress, so as to ensure the reliability of LED high-voltage chip operation.
Preferably, in evaporation N pads with before P pads, first roughening operation being carried out in the second surface of insulating layer, beneficial to raising
Second insulating barrier and N pads and P pad bonding strengths；P pads and N pad thickness can be 1um~2um, P pads and N pads it
Between interval be more than or equal to 150um, P pads and N pads be laminated using evaporation process and formed by Ti, Pt, Au or Ti, Pt, AuSn,
SnAgCu can be printed on Au.
As another embodiment of the present invention, plating or typography covering can be passed through on N pads and P bond pad surfaces
Tin paste layer, the thickness of tin paste layer is 50~100um, and tin paste layer is made up of Sn, Ag, Cu, and wherein Sn mass percent is 96.5,
Ag mass percent is 3.0, and surplus is Cu.Because the tin cream material has less voidage, heat dissipation channel can be effectively reduced
Thermal resistance, and possess extremely strong adhesion strength and conductive capability.Moreover, the material that tin paste layer category is directly welded, is conducive to letter
Change encapsulation step, and form between high-voltage chip and PCB substrate stress buffer.
The above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, although with reference to above-described embodiment pair
The present invention is described in detail, it should be understood by a person of ordinary skill in the art that still can be to the specific of the present invention
Embodiment is modified or equivalent substitution, and any modification or equivalent substitution without departing from spirit and scope of the invention,
It all should cover among scope of the presently claimed invention.
Claims (10)
1. upside-down mounting high voltage LED chip, including substrate and M chip being mutually independent on the substrate surface, M >=
2, each chip includes n type gallium nitride layer, luminescent layer and the p-type gallium nitride layer being grown on successively on the substrate surface, the N
Type gallium nitride layer, luminescent layer and p-type gallium nitride layer are constituted to be formed with the epitaxial layer of chip, the p-type gallium nitride layer of each chip
Reflecting layer；
Characterized in that, also including：
Cover the epitaxial layer of each chip and reflect the first insulating barrier of layer surface；
The P lead electrodes electrically connected with the reflecting layer of the first chip；
The N lead electrodes electrically connected with the n type gallium nitride layer of M chips；
The PN leads that the reflecting layer of the n type gallium nitride layer of the i-th chip and i+1 chip is electrically connected in series successively connect electricity
Pole, i=1 ..., M-1, the PN lead connection electrodes for the chip that each two is serially connected are mutually independent, in P leads electricity
The annular radiating for being through to first surface of insulating layer is formed on pole and/or N leads electrode and/or PN lead connection electrodes
Groove；
Second insulating barrier, second insulating barrier is covered in the surface of P leads electrode, PN leads connection electrode and N lead electrodes
On upper and the first surface of insulating layer between P leads electrode, PN leads connection electrode and N lead electrodes, and fill full described scattered
Formed on hot groove, second insulating barrier and be through to the P leads electrode and/or N leads electrode and/or PN leads connection electricity
The heat emission hole on pole surface, the projection of the heat emission hole in the horizontal plane is located in the radiating groove；
The N pads for being deposited on second insulating barrier and being connected with the N leads electrode；
The P pads for being deposited on second insulating barrier and being connected with the P leads electrode；
The heating column of the full heat emission hole of filling, the heating column is connected with the P pads and N pads.
2. upside-down mounting high voltage LED chip as claimed in claim 1, it is characterised in that：The thermal conductivity factor of the heating column is not less than
100W/(m·K)。
3. upside-down mounting high voltage LED chip as claimed in claim 1 or 2, it is characterised in that：The N pads and the filling of P pad portions
The full heat emission hole formation heating column.
4. upside-down mounting high voltage LED chip as claimed in claim 1, it is characterised in that：Also include
Through the epitaxial layer, expose the groove of the substrate surface, each chip is isolated by the groove；
P-type gallium nitride layer, luminescent layer through each chip is until the N electrode hole of n type gallium nitride layer surface；
First insulating barrier fill be formed with the groove and N electrode hole, the first insulating barrier of each chip with it is described anti-
Penetrate the connected p-type contact hole of layer surface and the N-type contact hole being connected with the n type gallium nitride layer surface；
The P leads electrode deposition on the insulating barrier of part first of the first chip surface and in p-type contact hole, pass through the first core
P-type contact hole on piece is electrically connected with the reflecting layer of the first chip；
The N leads electrode deposition on the insulating barrier of part first of M chip surfaces and in N-type contact hole, pass through M chips
On the n type gallium nitride layer of N-type contact hole and M chips electrically connect；
The PN leads connection electrode is deposited on the insulating barrier of part first of adjacent chips and N-type contact hole, p-type contact hole
It is interior；
Be formed with second insulating barrier N lead electrode contact holes that are connected with the N lead electrode surfaces on M chips and
The P lead electrode contacts hole being connected with the P lead electrode surfaces on the first chip；
The N pads be deposited on second insulating barrier and the N leads electrode contact hole in the N leads electrode connect
Connect；The P pads be deposited on second insulating barrier and the P leads electrode contact hole in be connected with the P leads electrode.
5. upside-down mounting high voltage LED chip as claimed in claim 1, it is characterised in that：First insulating barrier is along chip perimeter side
Wall and substrate attaching.
6. upside-down mounting high voltage LED chip as claimed in claim 5, it is characterised in that：Second insulating barrier is along chip perimeter side
Wall is fitted with the first insulating barrier, and each chip is fully wrapped around by first insulating barrier and the second insulating barrier successively.
7. upside-down mounting high voltage LED chip as claimed in claim 1, it is characterised in that：The N pads in P bond pad surfaces with covering
There is tin paste layer.
8. upside-down mounting high voltage LED chip as claimed in claim 7, it is characterised in that：The thickness of the tin paste layer be 50~
100um。
9. the preparation method of upside-down mounting high voltage LED chip, it is characterised in that comprise the following steps：
Step 1: providing substrate, n type gallium nitride layer is grown on the substrate surface, growth is luminous on n type gallium nitride layer
Layer, the growing P-type gallium nitride layer on luminescent layer, the n type gallium nitride layer, luminescent layer and p-type gallium nitride layer constitute each chip
Epitaxial layer；
Step 2: covering reflecting layer on p-type gallium nitride layer；
Step 3: form groove on epitaxial layer, groove depth is to substrate surface and exposes substrate, form the epitaxial layer
The first chip being mutually independent is to M chips, and M is the integer more than or equal to 2；Run through p-type in the formation of each chip surface
Gallium nitride layer, luminescent layer are until the N electrode hole of n type gallium nitride layer surface；
Step 4: covering the first insulating barrier, the first insulating barrier filling groove and N electrode hole on the surface in epitaxial layer and reflecting layer；
Step 5: in the punching of the first surface of insulating layer, forming the p-type contact hole for being deep to reflection layer surface and being deep to n type gallium nitride
The N-type contact hole of layer surface；
Step 6: forming the P leads electrode with wiring pattern, N leads electrode and PN leads connection electricity on the first insulating barrier
P lead electrodes are deposited on pole, the insulating barrier of part first on the first chip surface and in p-type contact hole, in M chip lists
N lead electrodes are deposited on the insulating barrier of part first on face and in N-type contact hole, in the insulating barrier of part first of adjacent chips
Deposition PN lead connection electrodes in upper and N-type contact hole, p-type contact hole, PN leads connection electrode is successively by the N of the i-th chip
The reflecting layer of type gallium nitride layer and i+1 chip is electrically connected in series, i=1 ..., M, the core that wherein each two is serially connected
The PN lead connection electrodes of piece are mutually independent；In the P leads electrode and/or N leads electrode and/or PN leads connection electricity
It is extremely upper to form the annular radiating groove for being through to first surface of insulating layer；
Step 7, forms the second insulating barrier, and the second insulating barrier covers P leads electrode, N leads electrode and PN lead connection electrodes
Surface and the surface of the first insulating barrier between P leads electrode, N leads electrode and PN lead connection electrodes, and
Fill the groove that completely radiates；
Step 8: the second insulating barrier formation be connected with the N lead electrode surfaces on M chips N lead electrode contacts hole, and
P lead electrode contact holes and be through to P leads electrode and/or N leads that P leads electrode surface on first chip is connected
Electrode and/or the heat emission hole on PN lead connection electrodes surface, the projection of the heat emission hole in the horizontal plane are located in radiating groove；
Step 9: forming N pads on the surface of insulating layer of part second and in N lead electrode contacts hole, insulated in part second
Form P pads in layer surface and in P lead electrode contacts hole, N pads by N lead electrode contact holes with and N lead electrode phases
Contact, P pads are by P lead electrode contact holes and P lead contact electrodes, and the interior filling heating column of the heat emission hole is described to lead
Plume is connected with the P pads and N pads.
10. the preparation method of upside-down mounting high voltage LED chip as claimed in claim 9, it is characterised in that：N pads and P pad portions
The full heat emission hole formation heating column of filling.
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| DE112017006432T5 (en) * | 2016-12-21 | 2019-09-05 | Seoul Viosys Co., Ltd | HIGHLY RELIABLE LUMINESCENT DIODE |
| CN112840468A (en) * | 2019-12-10 | 2021-05-25 | 厦门三安光电有限公司 | Light emitting device |
| CN111416027B (en) * | 2020-04-27 | 2022-08-12 | 厦门三安光电有限公司 | Flip-chip high-voltage light-emitting diode and light-emitting device |
| CN112467016A (en) * | 2020-11-16 | 2021-03-09 | 福建华佳彩有限公司 | Flexible packaging heat dissipation structure of Mini LED and manufacturing method thereof |
| CN112802953B (en) * | 2020-12-28 | 2022-10-28 | 厦门三安光电有限公司 | Light-emitting diode and preparation method thereof |
| CN113241393A (en) * | 2021-05-07 | 2021-08-10 | 临海市楚越微电子科技有限公司 | LED chip processing method based on space optimization and chip thereof |
| CN113644177B (en) * | 2021-08-10 | 2022-12-09 | 厦门三安光电有限公司 | Light emitting diode and light emitting device |
| CN118038766A (en) * | 2024-04-12 | 2024-05-14 | 常州明耀半导体科技有限公司 | LED display and manufacturing method thereof |
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