CN111416027B - Flip-chip high-voltage light-emitting diode and light-emitting device - Google Patents
Flip-chip high-voltage light-emitting diode and light-emitting device Download PDFInfo
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- CN111416027B CN111416027B CN202010343028.0A CN202010343028A CN111416027B CN 111416027 B CN111416027 B CN 111416027B CN 202010343028 A CN202010343028 A CN 202010343028A CN 111416027 B CN111416027 B CN 111416027B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
The invention relates to a flip high-voltage light-emitting diode and a light-emitting device, wherein the flip high-voltage light-emitting diode comprises a substrate and n sub-chips, wherein n is more than or equal to 3, the n sub-chips are positioned on the substrate and are mutually independent through a groove, each sub-chip comprises a semiconductor light-emitting stacked layer, and the semiconductor light-emitting stacked layer of each sub-chip and the groove are covered with a reflecting layer; the reflecting layer is provided with at least one first other opening and/or at least one second other opening which are positioned on at least one other sub-chip, the first bonding pad extends to the surface of the reflecting layer covered on at least one other sub-chip and is filled with the first other opening of the reflecting layer, and/or the second bonding pad extends to the surface of the reflecting layer covered on at least one other sub-chip and is filled with the second other opening, so that the integral wafer fixing capacity of the flip high-voltage light-emitting diode is improved.
Description
Technical Field
The invention relates to the technical field of light emitting diodes, in particular to an inverted high-voltage light emitting diode and a light emitting device.
Background
The flip chip has the advantages of low thermal resistance and no wire bonding, and the high-voltage chip has the advantages of high voltage and simplified driving power supply, so some research institutions hope to develop the flip chip to combine the advantages of the two chips for playing. The high-voltage flip chip can be applied to high-power fields such as illumination, backlight, RGB display screens, flexible filaments and the like by virtue of good heat dissipation performance, but the high-voltage flip chip focuses more on the die bonding capability of a bonding pad on a substrate, particularly the die bonding capability on the flexible substrate.
The flip-chip high voltage light emitting diode comprises at least three sub-chips 10, the structure of which is shown in fig. 1-2, each sub-chip 10 comprises a semiconductor light emitting stack layer, a groove is arranged between each sub-chip 10, a transparent insulating layer 105 covers the semiconductor light emitting stack layer and the groove of each sub-chip, a first electrode 106 and a second electrode 107 are respectively arranged on the semiconductor light emitting stack layers of the head and the tail of the two sub-chips, an interconnection electrode 108 is arranged on the groove, and connecting two adjacent sub-chips across the trench, the reflective layer 109 covering the first electrode, the second electrode, the trench, the interconnection electrode and the semiconductor light emitting sequence of each sub-chip, the reflective layer 109 being a bragg reflective layer, and the first pad 110 and the second pad 111, which are electrically opposite to each other, respectively covering the reflective layer 109 on the head-to-tail sub-chip and covering the surface of the middle sub-chip.
However, the flip-chip high voltage light emitting diode of the prior art has a technical problem that, taking a structure including three sub-chips as an example, a first bonding pad and a second bonding pad (P, N bonding pads) for die bonding are respectively covered on the reflective layer on each of the front and rear sub-chips and respectively covered on a partial region on the reflective layer on an intermediate sub-chip when the flip-chip high voltage light emitting diode is subsequently fixed on a package substrate. Through holes are respectively formed in the reflecting layers 109 covered on the head and tail sub-chips, and the first bonding pad and the second bonding pad (P, N bonding pad) are correspondingly filled with the through holes so as to be respectively connected with the first electrode and the second electrode (P, N electrode). Because the through holes are formed in the reflecting layers 109 of the first sub-chip and the last sub-chip respectively, the thickness of the reflecting layers is at least 2 micrometers, the depth of the through holes is at least 2 micrometers, the first bonding pad and the second bonding pad are filled in the through holes of the reflecting layers, the surface areas of the first bonding pad and the second bonding pad on the first sub-chip and the last sub-chip can be obviously increased, and the first bonding pad and the second bonding pad only cover the surface of the reflecting layers 109 of the middle sub-chip respectively. Therefore, the local die bonding capability of the bonding pad on the middle sub-chip can be further improved, and the overall die bonding capability is improved.
Disclosure of Invention
The invention aims to provide a flip high-voltage light emitting diode to improve the integral die bonding capability of the flip high-voltage light emitting diode, which comprises the following steps:
a substrate;
n sub-chips, wherein n is more than or equal to 3 and respectively refers to a 1 st sub-chip, an nth sub-chip and at least one other sub-chip, the n sub-chips are positioned on the substrate and are isolated from each other through grooves, and each sub-chip comprises a semiconductor light-emitting stacked layer at least composed of a first conductivity type semiconductor layer, a light-emitting layer and a second conductivity type semiconductor layer;
the reflecting layer is made of an insulating material and covers on each sub-chip and in the groove, the reflecting layer is provided with a first bonding pad through hole and a second bonding pad through hole, and the first bonding pad through hole and the second bonding pad through hole are respectively positioned above the 1 st sub-chip and the n-th sub-chip;
a first pad and a second pad, which are electrically opposite to each other, are respectively located on the surfaces of the reflective layers covered on the 1 st sub-chip and the n-th sub-chip, and respectively fill the first pad through hole and the second pad through hole, and the first pad and the second pad are respectively electrically connected to the second conductive type semiconductor layer of the 1 st sub-chip and the first conductive type semiconductor layer of the n-th sub-chip through the parts respectively filled in the first pad through hole and the second pad through hole;
the reflecting layer is provided with at least one first other opening and/or at least one second other opening, and the first other opening and/or the at least one second other opening are/is arranged above the at least one other sub chip; the first bonding pad extends to the surface of the reflecting layer covered on at least one other sub-chip and fills the first other opening of the reflecting layer, and/or the second bonding pad extends to the surface of the reflecting layer covered on at least one other sub-chip and fills the second other opening.
Preferably, the display device further comprises a transparent insulating layer, a first electrode and a second electrode; the transparent insulating layer covers on each sub chip and in the groove and is provided with a through hole; a first electrode and a second electrode electrically opposite to each other, filling the via hole of the transparent insulating layer to be connected to the second conductive type semiconductor layer and the first conductive type semiconductor layer of the 1 st and nth sub-chips, respectively; the reflecting layer covers the transparent insulating layer, the first electrode and the second electrode; first and second pads, which are electrically opposite to each other, fill the first and second pad vias, respectively, to be electrically connected to the first and second electrodes, respectively.
Preferably, the first further opening and/or the second further opening are each a through hole penetrating the reflective layer.
Preferably, the transparent insulating layer is located between the bottom of the first and/or second further opening and the semiconductor light emitting stack layer of the other sub-chip.
Preferably, each of the other sub-chips has a first further opening and/or a second further opening, the first pad simultaneously extending over at least one other sub-chip and filling the first further opening of the reflective layer, and/or the second pad simultaneously extending over at least one other sub-chip and filling the second further opening.
Preferably, each of the other sub-chips has a plurality of first other openings and/or a plurality of second other openings with uniform spacing between the plurality of first other openings and/or between the plurality of second other openings.
Preferably, the number of the other sub-chips is even, the reflective layer has only a first other opening over half of the other sub-chips, and the reflective layer has only a second other opening over the remaining half of the other sub-chips.
Preferably, the number of the other sub-chips is odd, and the first other opening and the second other opening are simultaneously arranged above one other sub-chip of the reflecting layer.
Preferably, the semiconductor light emitting sequence stacked layer of each sub-chip comprises a top surface and a side wall, and a transparent conducting layer is arranged between the top surface and the transparent insulating layer.
Preferably, the reflective layer is a bragg reflective layer.
Preferably, the thickness of the reflecting layer is 2-6 microns.
Preferably, the chip further includes an interconnection electrode, which is located on the transparent insulating layer on the trench and has two ends, the two ends respectively extend to the two adjacent sub-chips and fill the through holes of the transparent insulating layer to electrically connect the two adjacent sub-chips, and the interconnection electrode is located between the transparent insulating layer and the reflective layer.
Preferably, the chip further comprises another metal layer located between the transparent insulating layer and the reflective layer covered on the other sub-chip, and the other metal layer is located at a position corresponding to the first opening and the second opening and is spaced from the interconnection electrode by a certain distance.
More preferably, the other metal layer has a reflective function.
Preferably, the first pad and the second pad have a bottom layer which is a light reflecting layer.
Preferably, the first additional opening and/or the second additional opening are/is a blind hole which does not penetrate through the reflection layer.
Preferably, the first other opening and/or the second other opening are columnar or frustum-shaped holes, and the horizontal hole diameter of the first other opening and/or the second other opening is 2-40 micrometers.
Preferably, the horizontal aperture of the first other opening and/or the second other opening is 10-30 microns.
Preferably, the total number of the first other openings and the second other openings of each other sub-chip is 2-40.
Preferably, the total area of the first other opening and the second other opening of each other sub-chip occupies no more than 20% of the horizontal projection area of the semiconductor light emitting stack layer of the other sub-chip.
Preferably, the total area of the first other opening and the second other opening on the other sub-chip accounts for 5-15% of the horizontal projection area of the semiconductor light emitting stack layer of the other sub-chip.
Compared with the prior art, the flip-chip high-voltage light-emitting diode provided by the invention at least has the following advantages: the flip-chip high-voltage light-emitting diode provided by the invention forms at least one first other opening and at least one second other opening on the reflecting layer of the sub-chip which is not arranged in the middle of the head and the tail, and the second bonding pad and the first bonding pad are respectively filled in the corresponding first other opening and second other opening, so that the area of the bonding pad of the sub-chip at the middle position is increased, the local die bonding capability of the bonding pad on the middle sub-chip is increased, and the thrust value of the whole chip is increased finally.
Drawings
Fig. 1 shows a schematic top view of a flip-chip high voltage led in the prior art.
Fig. 2 shows a schematic cross-sectional structure of a flip-chip high voltage led in the prior art.
Fig. 3 shows a schematic top view of the flip-chip high voltage led of the present invention.
Fig. 4 shows a schematic cross-sectional structure along the line a in fig. 3, wherein the cross-sectional structure from left to right in fig. 4 is the cross-sectional structure along the arrow direction of the line a in fig. 3.
Fig. 5 shows a schematic cross-sectional structure along the line B in fig. 3, wherein the cross-sectional structure from left to right in fig. 5 is the cross-sectional structure along the arrow direction of the line a in fig. 3.
Fig. 6 shows a graph comparing the thrust values of a flip-chip high voltage light emitting diode of the prior art and of the present invention.
Description of reference numerals:
100: a substrate; 101: a first conductivity type semiconductor layer; 102: light-emitting layer, 103: a second conductive type semiconductor layer; 104: a transparent conductive layer; 105: a transparent insulating layer; 106: a first electrode; 107: a second electrode; 108: an interconnection electrode; 109: a reflective layer; 110: a first pad; 111: a second pad; 112: other metal layers.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. With these references, one of ordinary skill in the art will appreciate other possible embodiments and advantages of the present invention. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The structure of the flip-chip high voltage led of this embodiment will now be described in detail with reference to fig. 3 to 5.
First, an epitaxial structure is obtained on a substrate 100.
The substrate 100 may be one of a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon substrate, and the like. In this embodiment, the substrate 100 is a sapphire substrate, and the epitaxial structure is formed on a c-plane of the sapphire substrate, and the c-plane of the sapphire substrate is defined as a front surface and an opposite other surface is defined as a back surface. The at least three sub-chips 10 isolated from each other are located on a front surface of a substrate, the substrate is a transparent substrate, and the back surface is used for providing a main light output surface.
The semiconductor light emitting stack layer is a plurality of layers, and this embodiment may be referred to as an epitaxial structure, and the epitaxial structure includes at least a first conductive type semiconductor layer 101, an active layer 102, and a second conductive type semiconductor layer 103 sequentially stacked on the front surface of the substrate 100. For example, the first conductive type semiconductor layer 101 in this embodiment is an N-type GaN layer, the active layer 102 is a GaN-based mqw layer, and the second conductive type semiconductor layer 103 is a P-type GaN layer. The N-type GaN layer, the multiple quantum well layer and the P-type GaN layer are basic constituent units of an epitaxial structure of the LED chip, and on the basis, the epitaxial structure can further comprise other functional structure layers with an optimization effect on the performance of the light emitting diode.
The epitaxial structure may be formed on the substrate by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), epitaxial Growth (epitaxial Growth Technology), Atomic beam Deposition (ALD), and the like.
And then, an etching process is carried out on the epitaxial structure to form a hole or a step on the epitaxial structure, and the bottom of the hole or the step exposes part of the N-type layer. And then, manufacturing a groove by adopting an etching process, wherein the depth of the groove reaches the surface of the substrate to expose the substrate, and the epitaxial structures are isolated from each other by the groove, so that a plurality of sub-chips are formed. Each sub-chip thus has an epitaxial structure, each epitaxial structure providing a light emitting area. As in this embodiment, for convenience of description, the three epitaxial structures in fig. 4 are sequentially defined from left to right as a 1 st sub-chip, a 2 nd sub-chip, and a 3 rd sub-chip.
A transparent conductive layer 104 is formed on the second conductive type semiconductor layer 103 of each sub-chip, and the material of the transparent conductive layer 104 can be ITO, ZnO, AZO, FTO, IMO, etc., which can be formed on the second conductive type semiconductor layer 103 by using techniques such as e-beam evaporation or ion-beam sputtering. The transparent conductive layer 104 has an ohmic contact effect and a lateral current spreading effect.
A transparent insulating layer (CBL)105 covers the transparent conductive layer 104, the side surfaces of the epitaxial structure and the bottom of the trench, and the transparent insulating layer 105 can insulate and protect the epitaxial structures of the three sub-chips and the non-electrode-disposed region of the trench structure between the three sub-chips. The material of the transparent insulating layer 105 may be silicon dioxide SiO 2 、Si 3 N 4 And the like, which can be formed using a method such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The transparent insulating layer preferably has a thickness of 100 to 1000 nm.
And partially etching the part of the transparent insulating layer 105 covering the 1 st and 3 rd sub-chips, and etching a first electrode through hole and a second electrode through hole, wherein the first electrode through hole and the second electrode through hole correspond to the positions of a first electrode and a second electrode of the 1 st and 3 rd sub-chips, the bottom of the first electrode through hole is the surface of the 1 st sub-chip transparent conductive layer 104, and the bottom of the second electrode through hole is the surface of the 3 rd sub-chip first conductive semiconductor layer 101. The transparent insulating layer 105 covering the sub-chips 1, 2 and 3 is simultaneously etched to form a plurality of interconnection electrode vias. The bottom of the plurality of interconnection electrode vias of the transparent insulating layer 105 is on the first conductive type semiconductor layer surface of the 1 st and 2 nd sub-chips, and the transparent conductive layer surface of the 2 nd and 3 rd sub-chips.
The transparent insulating layer 105 covered on the 1 st sub-chip is filled with a conductive metal in a first electrode via hole to form a first electrode 106, and the insulating layer covered on the 3 rd sub-chip is filled with a conductive metal in a second electrode via hole to form a second electrode 107. The first electrode 106 is in contact with the transparent conductive layer, and the second electrode 107 is in contact with the first conductivity type semiconductor layer. The first electrode is formed while forming the interconnection electrode 108 for electrically connecting the two adjacent sub-chips, the interconnection electrode 108 is formed on the insulating layer in the trench and has two ends, the two ends extend to the two adjacent sub-chips, and one end of the interconnection electrode is in contact with the first conductive type semiconductor layer of one of the sub-chips and the other end of the interconnection electrode is in contact with the surface of the transparent conductive layer of the other sub-chip by filling the interconnection electrode through holes of the two adjacent sub-chips.
As shown in fig. 4, one of the interconnection electrodes connects the first conductive type semiconductor layer 101 of the 1 st sub-chip and the transparent conductive layer of the 2 nd sub-chip, and the other interconnection electrode connects the first conductive type semiconductor layer 101 of the 2 nd sub-chip and the transparent conductive layer of the 3 rd sub-chip. And preferably, the first electrode 106, the second electrode 107 and the interconnection electrode 108 extend from within the via to a local insulating layer upper surface vicinity around the transparent insulating layer via.
The conductive metal material of the first electrode 106, the second electrode 107, and the interconnection electrode 108 may be one material such as Al, Ni, Ti, Pt, Au, or an alloy composed of at least two of these materials, and may be formed using a technique such as electron beam evaporation or ion beam sputtering.
And forming a reflecting layer after the first electrode, the second electrode and the interconnection electrode are prepared. The reflective layer covers the transparent insulating layer, the first electrode and the second electrode, including covering the upper part of each sub-chip, the periphery of the side wall and the groove. Under the condition that the substrate is a transparent substrate, the reflecting layer reflects light radiated by the semiconductor light emitting stacked layer of each sub-chip, the reflected light reaches the back of the substrate, and backlight light emitting of the substrate is improved. The reflective layer 109 is made of a multi-layer insulating material, and the reflective layer 109 may be made of, for example, SiO 2 、TiO 2 、HfO 2 ,ZnO 2 ,ZrO 2 ,Cu 2 O 3 And the bragg reflective layer may be made of at least two different materials, for example, by alternately laminating the two materials into a plurality of layers using a technique such as electron beam evaporation or ion beam sputtering. Preferably, the thickness of the Bragg reflection layer is 2 to 6 microns.
The first pad 110 and the second pad 111 are formed by respectively having at least one first pad via hole and at least one second pad via hole by an etching process at a position where the reflective layer 109 covers over the corresponding first electrode and a position over the second electrode, and filling the first pad via hole and the second pad via hole with a conductive metal. In the present embodiment, the first pad 110 is electrically connected to the first electrode 106 of the 1 st sub-chip, i.e. the bottom of the first pad via contacts the first electrode 106; and the second pad 111 is electrically connected to the second electrode 107 of the nth sub-chip, i.e. the bottom of the second pad via contacts the second electrode 107. The conductive metal material of the first and second pads 110 and 111 may be a material such as Al, Cr, Ni, Ti, Pt, Au, or an alloy of at least two of these materials, and may be formed using a technique such as electron beam evaporation or ion beam sputtering. Since the first pad via and the second pad via may cause a loss of a reflective area of the reflective layer, an area of the first pad via or the second pad via may generally occupy no more than 20% of an area of the 1 st sub-chip or the n-th sub-chip.
Meanwhile, the first pad 110 and the second pad 111 extend to above at least one other sub-chip region except the 1 st and nth sub-chips. And at least one first pad through hole and at least one second pad through hole are formed on the insulating layer at the position above the first electrode and the position above the second electrode through an etching process, and at least one first other opening and/or at least one second other opening are formed on the reflecting layer 109 covered above the other sub-chips. The second pad 111 and the first pad 110 are filled in the corresponding first and second other openings, respectively. The first and second additional openings are used to fill the first and second pads, increasing the geometric area of the two pads.
Preferably, the first further opening and the second further opening are through holes penetrating through the reflective layer, and wherein the bottom of the first further opening and the bottom of the second further opening are both located on a transparent insulating layer 105 covering the other sub-chips, the transparent insulating layer insulates and isolates the first pad filled in the first further opening from the semiconductor light emitting stack, and at the same time insulates and isolates the second pad filled in the second further opening from the semiconductor light emitting stack. Therefore, the sub-chips are connected only through the interconnection electrodes, and the transparent insulating layer can prevent current from flowing into the semiconductor light-emitting laminated layer from the pad parts filled in the first other opening and the second other opening, so that the short-circuit problem is avoided.
In this embodiment, since there are three sub-chips, the reflective layer covering the 2 nd sub-chip is simultaneously provided with a first additional opening and a second additional opening.
The flip-chip high-voltage light-emitting diode provided by the invention forms at least one first other opening and at least one second other opening on the reflecting layer 109 of other sub-chips which are not arranged from head to tail, and the first bonding pad 110 and the second bonding pad 111 are respectively filled in the corresponding first other opening and second other opening, so that the area of the bonding pad of the sub-chip at the middle position is increased, the crystal fixing capacity of the middle sub-chip is increased, and the thrust value of the whole chip is increased; the phenomenon that local bonding pads on other sub-chips are not too hard to bond the chip and local peeling occurs, so that the overall reliability of the inverted high-voltage light-emitting diode is reduced.
In this embodiment, the number of the first other openings or the second other openings on each of the sub-chips that are not head-to-tail is multiple, and the first other openings and the second other openings on each of the other sub-chips are distributed at uniform intervals, and the openings are multiple, so that the bonding electrodes filled in the openings can also diffract or reflect light to a certain extent, which can reduce light loss, and the diffraction or reflection effect is better than that of the bonding electrodes filled in one opening with the same horizontal area, and the surfaces of the other sub-chips are subjected to uniform distribution after die bonding. Preferably, the number and/or total area of the first and second additional openings on one of the additional chiplets is the same as the number and/or total area of the first bonding electrode vias.
Preferably, the number of the other sub-chips is an even number, the reflective layer has only first other openings over half of the other sub-chips, and the number of the first other sub-chip openings over each of the other sub-chips of the half is equal, the reflective layer has only second other openings over the other sub-chips of the remaining half, and the number of the second other sub-chip openings over each of the other sub-chips of the remaining half is equal.
Preferably, the number of the other sub-chips is odd, the reflective layer has a first other opening and a second other opening above one of the other sub-chips, the number of the other sub-chips is even, the reflective layer has only a first other opening above half of the other sub-chips, and the number of the first other sub-chip openings above each sub-chip is equal; the reflective layer has only second further openings over another half of the other sub-chips of the remaining other sub-chips, and the second further sub-chip openings over each sub-chip are equal in number.
Since the filling of the first further opening or the second further opening with the pad electrode causes a reduction in the area of the reflective layer, a reduction in the overall reflectivity of the chip, and a certain loss of light. Therefore, the area of the first other opening or the second other opening of each sub-chip occupies no more than 20% of the horizontal projection area of the semiconductor light emitting stack layer of the other sub-chip, so that the sub-chip has a better overall thrust value and a smaller light loss.
Preferably, the ratio of the area of the first other opening or the second other opening of each sub-chip to the horizontal projection area of the semiconductor light emitting stack layer of the other sub-chip is 5-15%, and in this ratio, the flip-chip high voltage light emitting diode has a relatively excellent overall thrust value and smaller light loss.
Each of the first and second other openings has a shape of a pillar-shaped or a cone-shaped hole having a circular or polygonal horizontal cross section, and a horizontal aperture of preferably 2 to 40 micrometers, more preferably 10 to 30 micrometers.
The number of the first other openings and the second other openings on each sub-chip which is not head-to-tail is preferably 2-40.
In addition, as an embodiment, another metal layer 112 may be further included, the another metal layer being located between the transparent insulating layer and the reflective layer covering the other sub-chip, the another metal layer corresponding to the first another opening and the second another opening, the first pad extending to above the at least one other sub-chip, filling the first another opening of the transparent insulating layer and contacting the another metal layer, and/or the second pad extending to above the at least one other sub-chip, filling the second another opening of the transparent insulating layer and contacting the another metal layer. The other metal layer may be formed through the same step as the first electrode, the second electrode, and the interconnection electrode.
Fig. 6 reflects thrust relative value data of a chip in the background art and a chip in this embodiment, where the chip in the background art and the chip in this embodiment are named as chip No. 1 and chip No. 2, respectively, where chip No. 1 is a flip high-voltage light emitting diode manufactured by using a prior art scheme, chip No. 2 is a flip high-voltage light emitting diode manufactured by using a scheme in this embodiment, and includes 3 sub-chips, and 3 sub-chips are respectively a 1 st sub-chip, a 2 nd sub-chip, and a 3 rd sub-chip, where the 1 st sub-chip and the 2 nd sub-chip are covered with a first pad, and the 2 nd sub-chip and the 3 rd sub-chip are covered with a second pad. The only difference from chip No. 1 is that there are 2 first further openings and 2 second further openings in the insulating layer covering the 2 nd sub-chip of chip No. 2. The two flip high-voltage light emitting diodes are welded on the substrate by the same material and process, the thrust value of each flip high-voltage light emitting diode is tested, the measured thrust relative value data refers to a figure 5, as can be seen from the figure 5, the thrust value of the No. 1 chip is taken as a reference, and the thrust value of the No. 2 chip is about 1.16 times of the thrust value of the No. 1 chip. It can be seen that after the first additional opening and the second additional opening are added on the middle sub-chip, and the first pad 110 and the second pad 111 fill the corresponding first additional opening and second additional opening, the thrust value of the whole chip can be significantly increased.
In addition, the reflection area of the reflection layer is reduced to a certain extent due to the second other opening and the second other opening, so as to solve the above problem to a certain extent and improve the light efficiency. Or as another alternative, the bottom layers of the first bonding pad and the second bonding pad have light reflectivity, and the bottom layers form a metal reflecting layer with reflecting capacity for the light emitted by the flip-chip high-voltage light-emitting diode, wherein the metal reflecting layer comprises a mirror aluminum layer, a lens silver layer and the like.
As an alternative embodiment, the first other opening and the second other opening of the reflective layer may also be non-through holes, and the bottom of the opening is located in the reflective layer, so that the geometric area of the bonding pad can be increased, and the die bonding capability can be improved.
According to the invention, the plurality of other openings are arranged on the reflecting layers on the other sub-chips which are not head-to-tail and are used for filling the bonding pad, so that the geometric area of the bonding pad on the other sub-chips is increased, and the die bonding capability of the bonding pad on the other sub-chips is improved, thereby improving the overall die bonding capability of the bonding pad; the poor die bonding capability of the bonding pad on other sub-chips is avoided, the bonding pad is not locally stripped during die bonding, and the reliability of the chip is reduced; in addition, when the light emitting areas provided by the semiconductor light emitting laminated layers of each sub-chip are close to or equal to each other, the bonding pad through holes are formed in the parts, on the head chip and the tail chip, of the reflecting layers, the reflecting areas of the head chip and the tail chip are reduced to some extent, and a plurality of other openings are formed in the parts, on the other sub-chips, of the reflecting layers, so that the difference of the reflecting areas of each sub-chip is reduced, and uniform light emitting of each sub-chip is achieved as much as possible.
The high-voltage flip chip can be applied to the high-power fields of illumination, backlight, RGB display screens, flexible filaments and the like.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (21)
1. A flip-chip high voltage light emitting diode comprising:
a substrate;
n sub-chips, wherein n is more than or equal to 3 and respectively refers to a 1 st sub-chip, an nth sub-chip and at least one other sub-chip, the n sub-chips are positioned on the substrate and are isolated from each other through a groove, and each sub-chip comprises a semiconductor light-emitting stacked layer at least composed of a first conductivity type semiconductor layer, a light-emitting layer and a second conductivity type semiconductor layer;
the reflecting layer is made of an insulating material and covers each sub-chip and the groove, the reflecting layer is provided with a first bonding pad through hole and a second bonding pad through hole, and the first bonding pad through hole and the second bonding pad through hole are respectively positioned above the 1 st sub-chip and the n-th sub-chip;
a first pad and a second pad, which are electrically opposite to each other, are respectively located on the surfaces of the reflective layers covered on the 1 st sub-chip and the n-th sub-chip, and respectively fill the first pad through hole and the second pad through hole, and the first pad and the second pad are respectively electrically connected to the second conductive type semiconductor layer of the 1 st sub-chip and the first conductive type semiconductor layer of the n-th sub-chip through the parts respectively filled in the first pad through hole and the second pad through hole;
the reflecting layer is provided with at least one first other opening and/or at least one second other opening, and the first other opening and/or the at least one second other opening are/is arranged above the at least one other sub chip; the first bonding pad extends to the upper part of at least one other sub chip and fills the first other opening of the reflecting layer, and/or the second bonding pad extends to the upper part of at least one other sub chip and fills the second other opening of the reflecting layer; the total area of the first other opening and the second other opening of each other sub-chip accounts for no more than 20% of the horizontal projection area of the semiconductor light emitting stack layer of the other sub-chip;
the transparent insulating layer covers each sub-chip and the groove, the interconnection electrode is positioned on the transparent insulating layer on the groove and provided with two ends, the two ends respectively extend to the two adjacent sub-chips to be respectively and electrically connected with the two adjacent sub-chips, and the interconnection electrode is positioned between the transparent insulating layer and the reflecting layer.
2. The flip-chip high voltage light emitting diode of claim 1, wherein: the transparent conductive layer is provided with a through hole; a first electrode and a second electrode electrically opposite to each other, filling the through hole of the transparent insulating layer to be connected to the second conductive type semiconductor layer of the 1 st sub-chip and the first conductive type semiconductor layer of the nth sub-chip, respectively; the reflecting layer covers the transparent insulating layer, the first electrode and the second electrode; first and second pads, which are electrically opposite to each other, fill the first and second pad vias, respectively, to be electrically connected to the first and second electrodes, respectively.
3. The flip-chip high voltage light emitting diode of claim 1 or 2, wherein: the first other opening and/or the second other opening are through holes penetrating through the reflecting layer.
4. The flip-chip high voltage light emitting diode of claim 2, wherein: the transparent insulating layer is positioned between the bottom of the first other opening and/or the second other opening and the semiconductor light emitting stack layers of other sub-chips.
5. The flip-chip high voltage light emitting diode of claim 1, wherein: each of the other sub-chips has a first further opening and/or a second further opening, the first pad extending simultaneously over at least one other sub-chip and filling the first further opening of the reflective layer, and/or the second pad extending simultaneously over at least one other sub-chip and filling the second further opening of the reflective layer.
6. The flip-chip high voltage light emitting diode of claim 1, wherein: each of the other sub-chips has a plurality of first other openings and/or a plurality of second other openings with uniform spacing between the plurality of first other openings and/or between the plurality of second other openings.
7. The flip-chip high voltage light emitting diode of claim 1, wherein: the number of the other sub-chips is even, the reflecting layer only has a first other opening above half of the other sub-chips, and the reflecting layer only has a second other opening above the other half of the other sub-chips.
8. The flip-chip high voltage light emitting diode of claim 1, wherein: the number of the other sub-chips is odd, and the reflecting layer is provided with a first other opening and a second other opening above one of the other sub-chips.
9. The flip-chip high voltage light emitting diode of claim 1, wherein: the reflecting layer is a Bragg reflecting layer.
10. The flip-chip high voltage light emitting diode of claim 1, wherein: the thickness of the reflecting layer is 2-6 microns.
11. The flip-chip high voltage light emitting diode of claim 2, wherein: the semiconductor light emitting sequence stacking layer of each sub-chip comprises a top surface and a side wall, and a transparent conducting layer is arranged between the top surface and the transparent insulating layer.
12. The flip-chip high voltage light emitting diode of claim 2, wherein: the interconnection electrode is positioned on the transparent insulating layer on the groove and provided with two ends, the two ends respectively extend to the two adjacent sub-chips and fill the through holes of the transparent insulating layer so as to be respectively and electrically connected with the two adjacent sub-chips, and the interconnection electrode is positioned between the transparent insulating layer and the reflecting layer.
13. The flip-chip high voltage light emitting diode of claim 12, wherein: and the other metal layer is positioned between the transparent insulating layer and the reflecting layer which are covered on the other sub-chips, corresponds to the first opening and the second opening, and is spaced from the interconnection electrode by a certain distance.
14. The flip-chip high voltage light emitting diode of claim 13, wherein: the other metal layers have a reflection function.
15. The flip-chip high voltage light emitting diode of claim 1, wherein: the first bonding pad and the second bonding pad are provided with bottom layers which are light reflecting layers.
16. The flip-chip high voltage light emitting diode of claim 1, wherein: the first other opening and/or the second other opening are/is a blind hole which does not penetrate through the reflecting layer.
17. The flip-chip high voltage light emitting diode of claim 1, wherein: the first other opening and/or the second other opening are columnar or frustum-shaped holes, and the pore diameter of the first other opening and/or the second other opening is 2-40 micrometers.
18. The flip-chip high voltage light emitting diode of claim 17, wherein: the first other opening and/or the second other opening have a pore size of 10-30 micrometers.
19. The flip-chip high voltage light emitting diode of claim 1, wherein: the total number of the first other openings and the second other openings of each other sub-chip is 2-40.
20. The flip-chip high voltage light emitting diode of claim 1, wherein: and the total area of the first other opening and the second other opening on the other sub-chip accounts for 5-15% of the horizontal projection area of the semiconductor light emitting stacked layer of the other sub-chip.
21. A light emitting device comprising the flip-chip high voltage light emitting diode of any one of claims 1 to 20.
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| CN113363359A (en) * | 2021-06-09 | 2021-09-07 | 泉州三安半导体科技有限公司 | Flip-chip light emitting diode |
| CN116053381A (en) * | 2021-08-24 | 2023-05-02 | 厦门三安光电有限公司 | Flip-chip light emitting diode and preparation method thereof |
| CN113903843B (en) * | 2021-09-27 | 2023-01-17 | 厦门三安光电有限公司 | Light emitting diode and light emitting device |
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