CN112802953B - Light-emitting diode and preparation method thereof - Google Patents
Light-emitting diode and preparation method thereof Download PDFInfo
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- CN112802953B CN112802953B CN202011579718.2A CN202011579718A CN112802953B CN 112802953 B CN112802953 B CN 112802953B CN 202011579718 A CN202011579718 A CN 202011579718A CN 112802953 B CN112802953 B CN 112802953B
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/644—Heat extraction or cooling elements in intimate contact or integrated with parts of the device other than the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
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Abstract
The invention discloses a light-emitting diode and a preparation method thereof, wherein the preparation method comprises the following steps: a plurality of sub-chips, first pads, second pads and other pads electrically connected to each other; the adjacent sub-chips are spaced by the grooves, at least one sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip except the first sub-chip and the second sub-chip; the first bonding pad is electrically connected with the second semiconductor layer of the first sub-chip; the second bonding pad is electrically connected with the first semiconductor layer of the second sub-chip; at least one other sub-chip has one other bonding pad thereon, and the other bonding pad is electrically connected with at most one of the first bonding pad or the second bonding pad. The invention can avoid the phenomenon of uneven heat dissipation of the chip, solve the problem of chip burn caused by poor heat dissipation of the light-emitting diode and improve the reliability of the chip.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode and a preparation method thereof.
Background
With the development of LED technology, LEDs directly driven by high voltage have been realized. The efficiency of high voltage LEDs is superior to that of conventional low voltage LEDs, mainly due to the small current, the multi-unit design can spread the current evenly, and the high voltage LEDs can be directly driven at high voltage, thereby saving the cost of LED driving.
The existing high-voltage LED chip has the problems of power increase, difficult heat dissipation and reliability reduction. Generally, in order to ensure the uniformity of light emission of a high-voltage chip, the chip is divided into (at least three) sub-chips with equal areas by an isolation groove, and each sub-chip is connected in series to realize high-voltage light emission; in the process, the head and the tail of the two sub-chips are connected with the bonding pads for electrical interconnection, the bonding pads on the head and the tail of the two sub-chips can conduct heat to enable the chip to effectively dissipate heat, and the middle sub-chip cannot effectively dissipate heat due to the fact that no heat dissipation channel exists, so that heat accumulation is easily caused, and electrode burning and chip failure are caused.
Disclosure of Invention
In order to solve at least one technical problem in the background art, the invention provides the light-emitting diode and the preparation method thereof, which can avoid the phenomenon of uneven heat dissipation of a chip in the working process, solve the problem of chip burn caused by poor heat dissipation of the light-emitting diode and improve the reliability of the chip.
The technical scheme adopted by the invention is as follows:
according to an aspect of the present invention, there is provided a light emitting diode including:
the plurality of sub-chips are electrically connected, and adjacent sub-chips are spaced by a groove, wherein at least one sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip arranged between the first sub-chip and the second sub-chip;
the first bonding pad is electrically connected with the second semiconductor layer of the first sub-chip;
the second bonding pad is electrically connected with the first semiconductor layer of the second sub-chip; and
and at least one other sub-chip is provided with one other bonding pad, and the other bonding pad is electrically connected with at most one of the first bonding pad or the second bonding pad.
Optionally, at least one other pad overlies at least one other sub-chip.
Optionally, the chip further comprises a reflection layer, the reflection layer covers on each sub-chip and in the groove, the reflection layer is provided with a first pad through hole, a second pad through hole and at least one other pad through hole, and the first pad through hole, the second pad through hole and the at least one other pad through hole are respectively located above the first sub-chip, the second sub-chip and the at least one other sub-chip;
the first bonding pad, the second bonding pad and at least one other bonding pad are respectively positioned on the surface of the reflecting layer covered by the first sub-chip, the second sub-chip and at least one other sub-chip, wherein the first bonding pad and the second bonding pad are respectively filled in the first bonding pad through hole, the second bonding pad through hole and other first bonding pad and second bonding pad are respectively electrically connected to the second semiconductor layer of the first sub-chip and the first semiconductor layer of the second sub-chip through the parts respectively filled in the first bonding pad through hole and the second bonding pad through hole.
Optionally, the reflective layer is an insulating reflective layer.
Optionally, the first insulating layer is positioned below at least one other pad through hole and has a thickness of 50nm to 1000nm.
Optionally, the chip further includes a transparent conductive layer, the transparent conductive layer is located above the second semiconductor layer of the sub-chip, electrically connected to the second semiconductor layer, and an opening is formed at a position corresponding to at least one other pad via, and the at least one other pad via is located in the opening.
Optionally, a heat conduction portion is disposed in at least one other pad through hole corresponding to at least one other pad, and the at least one other pad is connected to at least one other sub-chip disposed correspondingly thereto through the heat conduction portion.
Optionally, a heat dissipation layer is further included, and the heat dissipation layer is located between the reflective layer and the first insulating layer.
Optionally, a cross-sectional area of the heat dissipation layer is greater than a cross-sectional area of the thermal conductive pillar and less than or equal to a cross-sectional area of the first insulating layer.
Optionally, the chip further comprises an interconnection electrode, and two ends of the interconnection electrode are connected with two adjacent sub-chips to electrically connect the several sub-chips.
Optionally, in the first sub-chip and the second sub-chip, a second insulating layer is further disposed between the transparent conductive layer and the second semiconductor layer, and the thickness of the second insulating layer is 50nm to 1000nm.
Optionally, the second insulating layer is a current blocking layer.
Optionally, the other pads are connected to the epitaxial layers of the other chiplets.
According to an aspect of the present invention, there is also provided a method of manufacturing a light emitting diode, including:
obtaining a plurality of sub-chips which are electrically connected with each other, wherein the adjacent sub-chips are spaced by a groove, at least one sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip except the first sub-chip and the second sub-chip;
preparing a first bonding pad and a second bonding pad, so that the first bonding pad is connected with the second semiconductor layer of the first sub-chip, and the second bonding pad is connected with the second semiconductor layer of the second sub-chip;
the other pads are prepared such that there is one other pad on at least one other chiplet and the other pads are electrically connected to at most one of the first or second pads.
Optionally, preparing other pads includes: at least one other bond pad is overlaid on at least one other chiplet.
Optionally, preparing the first pad and the second pad includes:
and preparing a reflecting layer in the sub-chips and the grooves, and preparing a first pad through hole, a second pad through hole and at least one other pad through hole on the reflecting layer above the first sub-chip, the second sub-chip and the other sub-chips, so that the first pad and the second pad respectively fill the first pad through hole and the second pad through hole, and are respectively electrically connected to the second semiconductor layer of the first sub-chip and the first semiconductor layer of the second sub-chip through parts respectively filled in the first pad through hole and the second pad through hole.
Optionally, a first insulating layer is prepared below at least one other pad via, the first insulating layer having a thickness of 50nm to 1000nm.
Optionally, preparing a transparent conductive layer over the second semiconductor layer of the sub-chip such that the transparent conductive layer is electrically connected with the second semiconductor layer; and forming an opening at a position corresponding to the at least one other pad through hole, so that the at least one other pad through hole is positioned in the opening.
Optionally, a heat conduction portion is formed in at least one other pad through hole corresponding to at least one other pad, so that at least one other pad is connected with at least one other sub-chip arranged correspondingly thereto through the heat conduction portion.
Optionally, a heat dissipation layer is formed between the reflective layer and the first insulating layer.
Compared with the prior art, the light-emitting diode and the preparation method have the following beneficial effects that:
the light emitting diode comprises a plurality of sub-chips which are electrically connected with each other, wherein the adjacent sub-chips are spaced by a groove, at least one sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip arranged between the first sub-chip and the second sub-chip; a first bonding pad connected with the second semiconductor layer of the first sub-chip; the second bonding pad is connected with the first semiconductor layer of the second sub-chip; and the other bonding pads are arranged on at least one other sub-chip and are electrically connected with at most one of the first bonding pads or the second bonding pads. Therefore, other bonding pads are arranged on other sub-chips between the first sub-chip and the second sub-chip, and the bonding pads covering the other sub-chips can assist the other sub-chips to dissipate heat, so that the phenomenon that the first sub-chip and the second sub-chip can dissipate heat and the other sub-chips cannot dissipate heat to cause uneven heat dissipation is avoided. Furthermore, at least one other bonding pad through hole is formed in the reflecting layer covering each sub-chip and the groove, and the other bonding pads conduct heat through the other bonding pad through holes, so that the problem of chip burn caused by poor heat dissipation of the light-emitting diode is solved, and the reliability of the chip is improved.
Drawings
FIGS. 1a-1b are schematic structural diagrams of a high voltage LED chip in the prior art;
FIGS. 2a-2b are schematic views of the structure of the LED without bonding pads on other sub-chips according to the present invention;
FIGS. 3a-3b are photographs of chip failures caused by burning of the electrodes of the light emitting diode according to the present invention;
FIGS. 4a-4b are schematic diagrams of an LED structure in embodiment 1 of the present invention;
fig. 5a to 5h are schematic diagrams of the led structure in embodiment 1 of the present invention;
FIG. 6 is a schematic diagram illustrating a positional relationship between the sub-chips of the LED in the embodiment of the present invention;
fig. 7 is a schematic structural diagram of a light emitting diode according to embodiment 2 of the present invention;
fig. 8 is a flowchart of a method for manufacturing a light emitting diode according to embodiment 3 of the present invention.
List of reference numerals:
100. substrate 503 interconnect electrode
200. First sub-chip 600 reflective layer
201. Epitaxial layer 601 first pad via
2011. First semiconductor layer 602 second pad via
2012. Active layer 603 other pad vias
2013. Second semiconductor layer 701 first pad
210. Second sub-chip 702 second bonding pad
220. Other pads of other chiplets 703
301. First insulating layer 800 thermal conductor
302. Second insulating layer 900 heat sink layer
303. Third insulating layer 1 sub-chip
400. Transparent conductive layer 2 pad
501. First electrode layer 3 burn zone
502. A second electrode layer
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the existing high-voltage LED chip, referring to FIGS. 1a-1b, the chip is divided into at least 3 sub-chips 1 with equal areas by an isolation groove, and each sub-chip 1 is connected in series to realize high-voltage light emission; the head and tail sub-chips 1 are electrically interconnected through the bonding pads 2 on the surfaces of the head and tail sub-chips, and the heat dissipation of the head and tail sub-chips can be realized through the bonding pads; and other sub-chips have no heat dissipation channel, so that the generated heat cannot be conducted out in time, and electrode burning and electrode failure are easily caused by heat accumulation. Specifically, referring to fig. 2a-2b, the light emitting diode includes a substrate 100, a first sub-chip 200, a second sub-chip 210, another sub-chip 220 disposed between the first sub-chip and the second sub-chip, and a pad, wherein the first sub-chip 200, the second sub-chip 210, and the another sub-chip 220 are connected in series; the bonding pads comprise a first bonding pad 701 and a second bonding pad 702, the first bonding pad 701 is connected with the second semiconductor layer of the first sub-chip 200, and the second bonding pad 702 is connected with the first semiconductor layer of the second sub-chip 210; in use, both the first chiplet 200 and the second chiplet 210 can dissipate heat through the first bonding pad 701 and the second bonding pad 702, and the other chiplets 220 do not have heat dissipation channels, resulting in heat build-up causing electrode burn-out, see fig. 3a-3b for burn-out area 3.
In order to solve the above technical problems, the present invention provides a light emitting diode and a method for manufacturing the same.
Example 1
The light emitting diode provided by the embodiment comprises a plurality of sub-chips, a first bonding pad, a second bonding pad and other bonding pads, wherein the plurality of sub-chips are electrically connected, adjacent sub-chips are spaced by a groove, at least one sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip except the first sub-chip and the second sub-chip; the first bonding pad is electrically connected with the second semiconductor layer of the first sub-chip, the second bonding pad is electrically connected with the first semiconductor layer of the second sub-chip, at least one other sub-chip is provided with one other bonding pad, and the other bonding pads are electrically connected with at most one of the first bonding pad or the second bonding pad. Therefore, the light-emitting diode provided by the invention has the advantages that other bonding pads are arranged on other sub-chips between the first sub-chip and the second sub-chip, and the other sub-chips are assisted by the other bonding pads to radiate heat, so that the phenomenon of uneven heat radiation caused by the fact that the first sub-chip and the second sub-chip can radiate heat and the other sub-chips cannot radiate heat is avoided.
In an embodiment, referring to fig. 4a and 4b, the substrate 100 may be one of a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon substrate, and the like. In this embodiment, the substrate 100 is a sapphire substrate, and the epitaxial structure is formed on a c-plane of the sapphire substrate, and the c-plane of the sapphire substrate is defined as a first surface and the opposite surface is defined as a second surface. A plurality of sub-chips are arranged at intervals between each other on the first surface of the substrate 100 through the grooves; at least one sub-chip comprises an epitaxial layer 201 composed of a first semiconductor layer 2011, an active layer 2012 and a second semiconductor layer 2013 with the conductivity type opposite to that of the first semiconductor layer; the epitaxial layer 201 may be an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer. The plurality of sub-chips include a first sub-chip 200, a second sub-chip 210, and at least one other sub-chip 220 except the first sub-chip 200 and the second sub-chip 210, and the sub-chips are electrically connected to each other.
The reflective layer 600 is disposed above each sub-chip epitaxial layer and covers each sub-chip and in the trench. Optionally, the reflective layer 600 is an insulating reflective layer, for example, a bragg reflective layer made of multiple layers of insulating materials, optionally, the reflective layer 600 has a thickness of 3 μm or more, preferably, 3 μm to 5 μm, for exampleFor example, it may be 4 μm. The material of the reflective layer 600 may be, for example, siO 2 、TiO 2 、HfO 2 ，ZnO 2 ，ZrO 2 ，Cu 2 O 3 And the bragg reflective layer may be made by alternately laminating two materials into a multilayer by using a technique such as electron beam evaporation or ion beam sputtering, for example.
The first pad 701 and the second pad 702 pass through a first pad via 601 and a second pad via 602 disposed on the reflective layer 600 to be electrically connected to the first chiplet 200 and the second chiplet 210, respectively; alternatively, the first pad 701 and the second pad 702 are filled in the first pad via hole 601 and the second pad via hole 602, respectively, and a heat conduction portion is formed in the first pad via hole 601 and the second pad via hole 602. In an alternative embodiment, a transparent conductive layer 400 is further disposed between the first sub-chip 200 and the second sub-chip 210 and the first pad through hole 601 and the second pad through hole 602, and the first sub-chip 200 and the second sub-chip 210 are electrically connected to the first pad 701 and the second pad 702 through the transparent conductive layer 400. Further, a first electrode layer 501 is further disposed between the transparent conductive layer 400 and the first pad through hole 601, a second electrode layer 502 is further disposed between the transparent conductive layer 400 and the second pad through hole 602, and the first sub-chip 200 and the second sub-chip 210 are electrically connected to the first pad 701 and the second pad 702 through the transparent conductive layer 400, the first electrode layer 501, and the second electrode layer 502.
At least one other pad 703 overlies at least one other chiplet 220, and the other pad 703 is connected to the epitaxial layers of the other chiplet 220. Wherein, the covering of the at least one other pad 703 on the at least one other sub-chip 220 may include the following cases: as shown in fig. 4a and 4b, one other pad 703 may be provided with one other sub-chip 220; may also correspond to a plurality of other chiplets 220, as shown in fig. 5a, 5b, and 5 c; meanwhile, there may be a case where one or more other sub-chips do not have other pad coverage, as shown in fig. 5 d; in alternative embodiments, multiple pads may be present on the same chiplet. For example, the first sub-chip 200 may be covered with the first pad 701 and a part of the other pads 703 at the same time, the other sub-chip 220 is covered with the other pads 703, and the second sub-chip 210 is covered with the second pads 702, as shown in fig. 5 f; the first chiplet 200 can be covered with both the first pads 701 and part of the other pads 703 while the second chiplet 210 is covered with the second pads 702 and part of the other pads 703 as shown in fig. 5 e. Other pads 703, a part of the first pads 701 and a part of the second pads 702 can be covered on other sub-chips 220 at the same time, as shown in fig. 5 g; it is also possible to cover only the other pads 703, part of the first pads 701 or part of the second pads 702, see fig. 5h. When one other bonding pad 703 covers a plurality of other sub-chips 220, the positions of the other bonding pad through holes 603 correspond to the positions of the other sub-chips 220, so that each other sub-chip can be connected to the other bonding pads and dissipate heat. Optionally, the number of the pad through holes corresponding to each sub-chip may be one or more; further, the number of the pad through holes on the first sub-chip 200, the second sub-chip 210 and the other sub-chips 220 is the same, and this arrangement can make the number of the heat dissipation channels of each sub-chip the same, so that the heat dissipation of each sub-chip is uniform, and the service life of the chip is increased. Further, the pad area covering each sub-chip can be set to be the same, so that the heat dissipation area of each sub-chip is the same, and the uniformity of heat dissipation of each sub-chip is improved.
In addition, the flip chip needs to use a thimble to push the middle position of the front surface of the chip (namely the geometric center of the chip) during packaging; in the process, the thimble cracks the insulating layer of the chip and even causes certain damage to the epitaxial layer of the chip, and the quality of the light-emitting diode is influenced. Therefore, when other bonding pads on the chip are positioned in the geometric center of the chip in the embodiment, the damage of the ejector pin to the chip can be prevented, and heat generated by the chip can be dissipated through the through holes of the other bonding pads; specifically, as shown in fig. 4a, the other bonding pad 703 is located at the geometric center of the whole chip, and the other bonding pad 703 has the functions of heat dissipation and thimble prevention.
In one embodiment, referring to FIG. 4a, the other pads 703 are insulated from each other chiplet by thermal conductors 800 disposed in other pad through-holes 603 on the reflective layer 600And (4) connecting. Optionally, the thermal conduction portion 800 in the other pad via 603 is an insulating material, such as SiO 2 、Si 3 N 4 、TiO 2 、Ti 2 O 3 、Ti 3 O 5 、Ta 2 O 5 、ZrO 2 And the like. Alternatively, the heat conduction portion 800 may be disposed in the pad through hole in the form of a heat conduction pillar or a heat conduction layer. In an alternative embodiment, the heat conducting portions 800 in the other pad through holes may also be made of a conductive material, in this case, the first insulating layer 301 is further disposed below the other pad through holes 703 and above the epitaxial layers of the other sub-chips, and the other pads 703 are connected to the epitaxial layers of the other sub-chips through the heat conducting portions 800 in the other pad through holes 603; alternatively, the material of the first insulating layer 301 may be SiO 2 、Si 3 N 4 、TiO 2 、Ti 2 O 3 、Ti 3 O 5 、Ta 2 O 5 、ZrO 2 And the like. Alternatively, the thickness of the first insulating layer 301 may be 50nm to 1000nm. Alternatively, the material of the first pad 701 and the second pad 702 may be a material such as A1, cr, ni, ti, pt, au, or an alloy composed of at least two of these materials; the material of the other bonding pads 703 is a non-conductive material with good heat dissipation, such as: a ceramic material; and the conductive material can also be one or a combination of A1, cr, ni, ti, pt and Au. It should be noted that when the material of the other bonding pad 703 is a conductive material, the area of the other bonding pad 703 can maximally contact with the first bonding pad 701 or the second bonding pad 702, but can be connected with only any one of the first bonding pad 701 and the second bonding pad 792, so as to prevent the first chiplet 200 and the second chiplet 210 from forming a via and affecting the performance of the chip. Optionally, a heat dissipation layer 900 is further disposed between the first insulating layer 301 and the other pad through holes 603, and the material of the heat dissipation layer 900 may be a common heat conductive metal, or a non-metal material, such as a diamond-like film. Optionally, the cross-sectional area of the heat dissipation layer 900 is larger than the cross-sectional area of the thermal conductive pillar 800 and smaller than or equal to the cross-sectional area of the first insulating layer 301, so that the heat dissipation layer 900 can effectively conduct heat on the epitaxial layers of other sub-chipsAnd the heat dissipation of other sub-chips is facilitated.
Optionally, the area of the other bonding pad 703 is larger than the area of the other bonding pad via 603 or slightly larger than the sum of the covered areas of the other sub-chips 220, so as to increase the heat dissipation area as much as possible and increase the heat dissipation performance of the chip.
Optionally, the transparent conductive layer 400 is located above the second semiconductor layer of the sub-chip, electrically connected to the second semiconductor layer, and an opening is formed at a position corresponding to at least one other pad via 603, where the at least one other pad via is located in the opening; the transparent conductive layer has an ohmic contact effect and a lateral current spreading effect. Optionally, in the first sub-chip 200 and the second sub-chip 210, a second insulating layer 302 is further disposed between the transparent conductive layer 400 and the second semiconductor layer; the second insulating layer 302 may serve as a current blocking layer for optimizing current spreading capability and improving heat dissipation capability and reliability of the chip. Optionally, the current barrier material can be SiO 2 、Si 3 N 4 、TiO 2 、Ti 2 O 3 、Ti 3 O 5 、Ta 2 O 5 、ZrO 2 One or a combination of materials.
Optionally, the light emitting diode further includes a third insulating layer 303, and the third insulating layer 303 covers the trenches between the sub-chips to insulate the chips. Optionally, the insulating layers in this embodiment are all transparent insulating layers, so as to avoid affecting the light emitting efficiency of the chip.
Alternatively, the first electrode layer 501 is disposed on the second semiconductor layer of the first sub-chip 220, and the second electrode layer 502 is disposed on the first semiconductor layer of the second sub-chip 210, wherein the first pad 701 and the second pad 702 are connected to the first electrode layer 501 and the second electrode layer 502 through the first pad through hole 601 and the second pad through hole 602, respectively.
Optionally, the light emitting diode further includes an interconnection electrode 503, two ends of the interconnection electrode 503 are connected to two adjacent sub-chips to connect several sub-chips in series, for example, one end of the interconnection electrode 503 is connected to the second semiconductor layer of the first sub-chip 200, and the other end is connected to the first semiconductor layer of the other sub-chip 220.
It should be noted that the other sub-chip 220 described in this embodiment refers to a sub-chip electrically connected between the first sub-chip 200 and the second sub-chip 210, and does not limit specific positions of other sub-chips. For example, as shown in fig. 6, although the actual positions of the other sub-chips 220 are not located between the first sub-chip 200 and the second sub-chip 210, from the perspective of the connecting circuit, the first sub-chip 200 is located at the head end of the connecting circuit, the second sub-chip 210 is located at the tail end of the connecting circuit, and the other sub-chips 220 are located between the first sub-chip 200 and the second sub-chip 210 at the head and tail ends of the connecting circuit. Thus, the sub-chips connected between the first sub-chip 200 and the second sub-chip 210 are all other sub-chips according to the present invention.
The light emitting diode described in this embodiment is provided with other bonding pads on other sub-chips between the first sub-chip and the second sub-chip, and the bonding pads can cover other sub-chips and assist the other sub-chips to dissipate heat, thereby avoiding the phenomenon of uneven heat dissipation caused by the fact that the first sub-chip and the second sub-chip can dissipate heat and the other sub-chips cannot dissipate heat. In addition, other pad through holes are further formed in the reflecting layer covering each sub-chip and the groove, and the other pads conduct heat through the other pad through holes, so that the problem of chip burn caused by poor heat dissipation of the light emitting diode is solved, and the reliability of the chip is improved.
Example 2
The present embodiment provides a light emitting diode, which has the same points as those in embodiment 1, and is not repeated herein, except that:
referring to fig. 7, the other pads 703 are electrically connected to the respective other chiplets through the thermal conductors 800 disposed in the other pad through-holes 603 on the reflective layer 600. Specifically, one end of the heat conducting portion 800 is connected to the other bonding pad 703 through the other heat dissipating through hole 603, and the other end is connected to the epitaxial layer of the other sub-chip 220; in this case, the other pads 703 and the heat conduction portion 800 are made of a conductive material. Optionally, a heat dissipation layer 900 is further disposed between the thermal conductive portion 800 and the epitaxial layers of the other sub-chips 220, and the material of the heat dissipation layer 900 is also a thermal conductive metal. Optionally, the cross-sectional area of the heat dissipation layer 900 is larger than the cross-sectional area of the thermal conductive pillar 800 and smaller than or equal to the cross-sectional area of the first insulating layer 301, so that the heat dissipation layer 900 can effectively conduct heat away from the epitaxial layers of other sub-chips, which is beneficial for heat dissipation of other sub-chips.
In the embodiment, the heat dissipation of other sub-chips can be assisted by covering other bonding pads of other sub-chips, so that the phenomenon that the first sub-chip and the second sub-chip can dissipate heat and the other sub-chips cannot dissipate heat to cause uneven heat dissipation is avoided. The other bonding pad through holes arranged on the reflecting layer covering each sub-chip and the groove can conduct heat, so that the problem of chip burn caused by poor heat dissipation of the light-emitting diode is solved, and the reliability of the chip is improved.
Example 3
The embodiment also provides a method for manufacturing the light emitting diode, which is shown in fig. 8, 4a-4b and 5a-5h; the method comprises the following steps:
s101: obtaining a plurality of sub-chips which are electrically connected with each other, wherein adjacent sub-chips are spaced by a groove; wherein, at least one sub-chip comprises an epitaxial layer at least composed of a first semiconductor layer, an active layer and a second semiconductor layer with a conductivity type opposite to that of the first semiconductor layer, and the plurality of sub-chips comprise a first sub-chip 200, a second sub-chip 210 and at least one other sub-chip 220 except the first sub-chip 200 and the second sub-chip 210;
specifically, a substrate 100 is provided, the substrate 100 may be one of a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a silicon substrate, and the like, an epitaxial layer including a first semiconductor layer, an active layer, and a first semiconductor layer is sequentially formed on the substrate 100, and for example, the epitaxial layer may be grown on the substrate by using Metal Organic Chemical Vapor Deposition (MOCVD); the epitaxial layer 201 is etched to form a plurality of sub-epitaxial layers.
A transparent conductive layer 400 is formed on the second semiconductor layer of each epitaxial layer 201 such that the transparent conductive layer 400 is electrically connected to the second semiconductor layer, and an opening is formed at a position corresponding to at least one other pad via 603. Optionally, in the first chiplet 200 and the second chiplet 210, the second insulating layer 302 is formed between the transparent conductive layer 400 and the second semiconductor layer such that part of the transparent conductive layer 400 is electrically connected to the second semiconductor layer, part of the transparent conductive layer 400 is isolated from the second semiconductor layer by the second insulating layer 302, and the second insulating layer 302 is a current blocking layer for optimizing current spreading capability. Optionally, the thickness of the second insulating layer 302 is 50nm to 1000nm.
Forming an interconnection electrode 503 between two adjacent epitaxial layers, specifically, the interconnection electrode 503 is formed above the transparent conductive layer 400 and is electrically connected with the transparent conductive layer 400; one end of the interconnection electrode 503 is connected to the first semiconductor layer of one of the two adjacent epitaxial layers, and the other end is connected to the second semiconductor layer of the other of the two adjacent epitaxial layers, so that the two adjacent epitaxial layers are electrically connected.
S102: the first pad 701 and the second pad 702 are prepared such that the first pad 702 is connected to the second semiconductor layer of the first chiplet 200 and the second pad 702 is connected to the second semiconductor layer of the second chiplet 210.
Specifically, a reflective layer 600 is prepared on each sub-chip and in the trench, and the reflective layer 600 can be prepared by using a technique such as electron beam evaporation or ion beam sputtering; and a first pad through hole 601 and a second pad through hole 602 are prepared on the reflective layer 600 above the first sub-chip 200, the second sub-chip 210 and the other sub-chips 220, and the reflective layer 600 may be etched by dry etching or wet etching to obtain the pad through holes. The first pad 701 and the second pad 702 are respectively filled with materials such as electron beam evaporation or ion beam sputtering in the first pad through hole 601 and the second pad through hole 602, and the first pad 701 and the second pad 702 are formed above the reflective layer 600 corresponding to the first sub-chip 200 and the second sub-chip 210, and the first pad 701 and the second pad 702 are respectively electrically connected to the second semiconductor layer 2013 of the first sub-chip 200 and the first semiconductor layer of the second sub-chip 210 through the portions respectively filled in the first pad through hole 601 and the second pad through hole 602.
S103: the other pads 703 are prepared such that at least one other chiplet 603 has one other pad 703 thereon, and the other pad 703 is electrically connected to at most one of the first pads 701 or the second pads 702.
Specifically, another pad via 603 is formed over the opening position of the transparent conductive layer 400 on another chiplet 603, and a thermal conduction portion 800 is formed within the other pad via 603. Alternatively, the heat conduction part 800 may be formed by electron beam evaporation, ion beam sputtering, or chemical deposition, and the material of the heat conduction part 800 may be SiO 2 、Si 3 N 4 、TiO 2 、Ti 2 O 3 、Ti 3 O 5 、Ta 2 O 5 、ZrO 2 One or more of these materials, and may also be the same material as the other pads. Other pads are sputtered or evaporated over the thermal conductor 800 such that at least one of the other pads 603 is connected to at least one other chiplet 220 disposed corresponding thereto through the thermal conductor 800, see fig. 4a or 7.
Alternatively, a first insulating layer 301 is formed between the thermal conduction portion 800 and the second semiconductor layer so that the other pads 703 are connected to the other chiplets 220 in an insulating manner; optionally, a heat dissipation layer 900 is further formed between the thermal conductor 800 and the first insulating layer 301, the cross-sectional area of the heat dissipation layer 900 being larger than the cross-sectional area of the thermal conductor 800, see fig. 4a.
By the method for manufacturing a light emitting diode described in this example, the light emitting diode of example 1 or example 2 can be obtained, and the technical effects of example 1 or example 2 can be similarly achieved.
In summary, the light emitting diode and the manufacturing method of the invention at least have the following beneficial effects:
the light emitting diode comprises a plurality of sub-chips which are electrically connected with each other, wherein the adjacent sub-chips are spaced by a groove, at least one sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip arranged between the first sub-chip and the second sub-chip; the first bonding pad is connected with the second semiconductor layer of the first sub-chip; the second bonding pad is connected with the first semiconductor layer of the second sub-chip; and the other bonding pads are arranged on at least one other sub-chip and are electrically connected with at most one of the first bonding pads or the second bonding pads. Therefore, other bonding pads are arranged on other sub-chips between the first sub-chip and the second sub-chip, and the bonding pads covering the other sub-chips can assist the other sub-chips to dissipate heat, so that the phenomenon that the first sub-chip and the second sub-chip can dissipate heat and the other sub-chips cannot dissipate heat to cause uneven heat dissipation is avoided. Furthermore, at least one other bonding pad through hole is formed in the reflecting layer covering each sub-chip and the groove, and the other bonding pads conduct heat through the other bonding pad through holes, so that the problem of chip burning caused by poor heat dissipation of the light-emitting diode is solved, and the reliability of the chip is improved.
The specific embodiments are only for explaining the invention, not for limiting the invention, and the skilled in the art can modify the embodiments as required after reading the description, but only by the protection of the patent law within the scope of the claims of the present invention.
Claims (16)
1. A light emitting diode, comprising:
the plurality of sub-chips are electrically connected, and adjacent sub-chips are spaced by a groove, wherein each sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip except the first sub-chip and the second sub-chip;
the insulating layer is formed on the surfaces of the other sub-chips;
a first bonding pad electrically connected to the second semiconductor layer of the first sub-chip;
a second bonding pad electrically connected to the first semiconductor layer of the second sub-chip; and
each other sub-chip is covered with other bonding pads which are not electrically connected with the first bonding pads or the second bonding pads;
the insulating reflecting layer covers on each sub chip and in the groove;
the pad through-hole, set up in the insulating reflecting layer, the pad through-hole includes first pad through-hole, second pad through-hole and at least one other pad through-hole, first pad through-hole the second pad through-hole and at least one other pad through-hole is located respectively first sub-chip the second sub-chip and the top of other sub-chips, other pads pass through other pad through-holes are connected to the insulating layer on each other sub-chip surface, in order to with other sub-chips form insulating connection.
2. The light-emitting diode according to claim 1, wherein the first pad, the second pad and the other pad are respectively located on a surface covering the insulating reflective layer on the first chiplet, the second chiplet and the other chiplet, wherein the first pad and the second pad respectively fill the first pad via and the second pad via and are electrically connected to the second semiconductor layer of the first chiplet and the first semiconductor layer of the second chiplet through portions respectively filled in the first pad via and the second pad via.
3. The led of claim 1, wherein the insulating layer further comprises a first insulating layer, wherein the first insulating layer is located below the other pad via, and wherein the first insulating layer has a thickness of 50nm to 1000nm.
4. The led of claim 1, further comprising a transparent conductive layer, wherein the transparent conductive layer is disposed above the second semiconductor layer of the sub-chip, electrically connected to the second semiconductor layer, and has an opening formed at a position corresponding to the at least one other pad via, and the at least one other pad via is disposed in the opening.
5. The LED of claim 3, wherein a thermal conductor is formed in at least one other pad via corresponding to the other pad, and the other pad is connected to the at least one other sub-chip disposed corresponding to the other pad via the thermal conductor.
6. The led of claim 5, further comprising a heat spreading layer, said heat spreading layer being positioned between said insulating reflective layer and said first insulating layer.
7. The LED of claim 6, wherein the cross-sectional area of the heat spreading layer is greater than the cross-sectional area of the thermal conductor and less than or equal to the cross-sectional area of the first insulating layer.
8. The light-emitting diode according to claim 1, further comprising an interconnection electrode, wherein two ends of the interconnection electrode are connected to two adjacent sub-chips to electrically connect the sub-chips.
9. The light-emitting diode according to claim 4, wherein a second insulating layer is further provided between the transparent conductive layer and the second semiconductor layer in the first sub-chip and the second sub-chip, and the thickness of the second insulating layer is 50nm to 1000nm.
10. The led of claim 9, wherein said second insulating layer is a current blocking layer.
11. A method for preparing a Light Emitting Diode (LED), comprising:
obtaining a plurality of sub-chips which are electrically connected with each other, wherein adjacent sub-chips are spaced by a groove; each sub-chip comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the plurality of sub-chips comprise a first sub-chip, a second sub-chip and at least one other sub-chip except the first sub-chip and the second sub-chip;
preparing an insulating layer, and forming the insulating layer on the surfaces of the other sub-chips;
preparing a first bonding pad and a second bonding pad, so that the first bonding pad is connected with the second semiconductor layer of the first sub-chip, and the second bonding pad is connected with the first semiconductor layer of the second sub-chip;
preparing other bonding pads, so that each other sub-chip is covered with other bonding pads, and the other bonding pads are not electrically connected with the first bonding pads or the second bonding pads;
preparing an insulating reflecting layer, so that the insulating reflecting layer covers each sub chip and the groove;
preparing pad through holes formed in the insulating reflecting layer, wherein the pad through holes comprise a first pad through hole, a second pad through hole and at least one other pad through hole, the first pad through hole, the second pad through hole and the at least one other pad through hole are respectively positioned above the first sub-chip, the second sub-chip and the other sub-chips,
and the other bonding pads are connected to the insulating layer on the surface of each other sub-chip through the other bonding pad through holes so as to form insulating connection with the other sub-chips.
12. The method of manufacturing a light emitting diode according to claim 11, wherein the manufacturing of the first pad and the second pad includes:
preparing an insulating reflective layer in the sub-chip and the trench, and preparing a first pad via, a second pad via, and at least one other pad via on the insulating reflective layer located above the first sub-chip, the second sub-chip, and the other sub-chip, such that the first pad and the second pad fill the first pad via and the second pad via, respectively, and are electrically connected to the second semiconductor layer of the first sub-chip and the first semiconductor layer of the second sub-chip, respectively, through portions filled in the first pad via and the second pad via, respectively.
13. The method of claim 12, wherein the step of forming the insulating layer comprises: and preparing a first insulating layer below the other pad through holes, wherein the thickness of the first insulating layer is 50 nm-1000 nm.
14. The method of manufacturing a light-emitting diode according to claim 12, wherein a transparent conductive layer is manufactured over the second semiconductor layer of the sub-chip so that the transparent conductive layer is electrically connected to the second semiconductor layer; and forming an opening at a position corresponding to the at least one other pad through hole, so that the at least one other pad through hole is positioned in the opening.
15. The method of claim 12, wherein a thermal conductive portion is formed in at least one other pad via corresponding to the other pad, such that the other pad is connected to the at least one other sub-chip disposed corresponding to the other pad via the thermal conductive portion.
16. The method of claim 13, wherein a heat sink layer is formed between the insulating reflective layer and the first insulating layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681704A (en) * | 2015-01-30 | 2015-06-03 | 大连德豪光电科技有限公司 | Flip LED (Light Emitting Diode) chip and production method thereof |
| CN104779339A (en) * | 2015-01-15 | 2015-07-15 | 大连德豪光电科技有限公司 | Inverted high-voltage LED chip and preparation method thereof |
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| CN104241508A (en) * | 2014-09-22 | 2014-12-24 | 山东浪潮华光光电子股份有限公司 | White LED chip and manufacturing method |
| CN204516759U (en) * | 2015-01-30 | 2015-07-29 | 大连德豪光电科技有限公司 | Flip LED chips |
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| CN106206883A (en) * | 2016-09-18 | 2016-12-07 | 佛山市国星半导体技术有限公司 | A kind of upside-down mounting high voltage LED chip |
| CN107331679A (en) * | 2017-07-05 | 2017-11-07 | 广东工业大学 | A kind of the high voltage LED chip structure and preparation method of CSP encapsulation |
| CN107516701B (en) * | 2017-07-14 | 2019-06-11 | 华灿光电(苏州）有限公司 | A kind of high pressure light-emitting diode chip and preparation method thereof |
| CN109216515B (en) * | 2018-07-26 | 2020-07-07 | 华灿光电股份有限公司 | Flip LED chip and manufacturing method thereof |
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| CN111416027B (en) * | 2020-04-27 | 2022-08-12 | 厦门三安光电有限公司 | Flip-chip high-voltage light-emitting diode and light-emitting device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779339A (en) * | 2015-01-15 | 2015-07-15 | 大连德豪光电科技有限公司 | Inverted high-voltage LED chip and preparation method thereof |
| CN104681704A (en) * | 2015-01-30 | 2015-06-03 | 大连德豪光电科技有限公司 | Flip LED (Light Emitting Diode) chip and production method thereof |
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