WO2022140898A1

WO2022140898A1 - High-voltage flip-chip light-emitting diode chip and preparation method therefor

Info

Publication number: WO2022140898A1
Application number: PCT/CN2020/140041
Authority: WO
Inventors: 刘士伟; 徐瑾; 王水杰; 刘可; 阙珍妮; 张中英
Original assignee: 厦门三安光电有限公司
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2022-07-07
Also published as: CN113302758A

Abstract

Disclosed in the present application are a high-voltage flip-chip light-emitting diode (LED) chip and a preparation method therefor. The high-voltage flip-chip LED chip comprises a plurality of sub-chips and a protection layer; adjacent sub-chips are separated by an isolation groove, and adjacent sub-chips are electrically connected to one another; each sub-chip comprises a semiconductor stack layer, and the semiconductor stack layers each comprise a first-type semiconductor layer, an active layer, and a second-type semiconductor layer; the protection layer covers the sub-chips and the isolation groove between adjacent sub-chips; and a recessed area is formed in the protection layer located in the isolation groove, and a third bonding pad is formed at least in the recessed area of the central region of the high-voltage flip-chip LED chip. According to the present application, a third bonding pad is formed in the central region of the high-voltage flip-chip LED chip, and when an ejector pin acts on the central region of the chip, the third bonding pad can prevent the ejector pin from puncturing the protection layer, thereby improving the reliability of the chip.

Description

High voltage flip-chip light emitting diode chip and preparation method thereof

technical field

The present application relates to the technical field of semiconductors, and in particular, to a high-voltage flip-chip light-emitting diode chip and a preparation method thereof.

Background technique

The light-emitting diode chip is a semiconductor solid-state light-emitting device, which has the characteristics of high reliability, long life and low power consumption, and has a wide range of applications. As the power and brightness requirements of LED chips are gradually increasing, the current solution is to prepare high-voltage flip-chip LED chips. Each sub-chip is connected in series with each other to obtain a high-voltage flip-chip light-emitting diode chip. In the high-voltage flip-chip light-emitting diode chip, it is necessary to use a thimble to act on the chip, and the thimble is prone to crack or puncture the protective layer at the isolation groove, which makes the high-voltage flip-chip light-emitting diode chip leakage failure and poor reliability.

technical solutions

The purpose of the present application is to provide a high-voltage flip-chip light-emitting diode chip, which can solve the problem of poor chip reliability caused by easy topping or puncturing the protective layer at the isolation groove when a thimble acts on the high-voltage flip-chip light-emitting diode chip.

Another object is to provide a preparation method of a high voltage flip-chip light emitting diode chip.

In a first aspect, an embodiment of the present application provides a high-voltage flip-chip light-emitting diode chip, including:

A plurality of sub-chips, the adjacent sub-chips are separated by isolation grooves, and the adjacent sub-chips are electrically connected; each sub-chip includes a semiconductor stack layer, and the semiconductor stack layer includes a first-type semiconductor layer, an active layer and a first-type semiconductor layer. Two types of semiconductor layers; wherein, the sub-chips are defined as the first sub-chip, the second sub-chip, and the n-th sub-chip in sequence;

The protective layer covers the sub-chips and the isolation grooves between adjacent sub-chips; the protective layer located at the isolation grooves is formed with a concave area;

a first pad, electrically connected to the first type semiconductor layer of the first sub-chip;

the second pad is electrically connected to the second type semiconductor layer of the nth sub-chip;

The third pad is located at least on the recessed area in the central area of the high-voltage flip-chip light emitting diode chip.

In a possible implementation, the third pad covers at least the bottom and sidewalls of the corresponding recessed area.

In a possible implementation, the third pad covers the bottom and sidewalls of the corresponding recessed area and the upper surface of the protective layer in the vicinity of the corresponding recessed area.

In a possible implementation, the third pad and the protective layer at the corresponding recessed area form a total reflection structure.

In one possible embodiment, the third pad area is greater than 300 μm ² .

In a possible embodiment, the thickness of the third pad is between 0.5 μm and 10 μm.

In a possible implementation, the ratio of the thickness of the protective layer directly above the sub-chip to the thickness of the protective layer located on the sidewall of the recessed region is between 1 and 2.

In a possible implementation, the third pad is spaced apart from the first pad and the second pad.

In a possible implementation, the sides of the first pad and the second pad close to the third pad are both arc-shaped, and the arc-shaped opening faces the third pad.

In a possible embodiment, the third pad is formed by an extension of the first pad or the second pad.

In a possible embodiment, at least one recessed area is formed with a third pad.

In one possible embodiment, the protective layer comprises a distributed Bragg reflector (DBR);

Alternatively, the protective layer includes one or more of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer or a silicon oxynitride layer;

Alternatively, the protective layer includes an aluminum oxide layer.

In a possible implementation, the high voltage flip-chip light emitting diode chip includes:

a first electrode, connected to the first type semiconductor layer in the first sub-chip;

a second electrode, connected to the second type semiconductor layer in the nth sub-chip;

Interconnect electrodes to connect adjacent sub-chips.

In one possible embodiment, each chiplet includes a first current blocking layer and a transparent conductive layer formed on the second type semiconductor layer.

In a second aspect, an embodiment of the present application provides a method for preparing the above-mentioned high-voltage flip-chip light-emitting diode chip, including:

A plurality of sub-chips are formed on the substrate, and adjacent sub-chips are separated by isolation grooves; the sub-chips are defined as a first sub-chip, a second sub-chip, and an n-th sub-chip in sequence;

A protective layer is formed on the sub-chips and the isolation trenches between adjacent sub-chips; the protective layer at the isolation trench is formed with a concave area; the protective layer is etched to form a first opening for mounting the first pad and a second opening for mounting the second pad;

A third pad, a first pad and a second pad are respectively formed at least at the recessed area, the first opening and the second opening in the central region of the high voltage flip-chip light emitting diode chip.

In a possible implementation, a plurality of sub-chips are formed on the substrate, and the spacing between adjacent sub-chips by isolation trenches includes:

Forming intermittently arranged semiconductor stack layers on the substrate; the semiconductor stack layers include a first type semiconductor layer, an active layer and a second type semiconductor layer;

A first electrode connected to the first-type semiconductor layer in the first sub-chip, a second electrode connected to the second-type semiconductor layer in the n-th sub-chip, and an interconnect electrode connected to an adjacent sub-chip are formed.

In one possible implementation, a first electrode connected to the semiconductor layer of the first type in the first sub-chip, a second electrode connected to the second type of semiconductor layer in the n-th sub-chip, and an adjacent sub-chip are formed. Before the interconnection electrodes, an intermittently arranged semiconductor stack layer is formed on the substrate, and after the semiconductor stack layer includes the first type semiconductor layer, the active layer and the second type semiconductor layer, it also includes:

A first current blocking layer is formed on the surface of the second type semiconductor layer, and the area covered by the first current blocking layer includes part of the surface of the second type semiconductor layer, sidewalls of the semiconductor stack layer and part of the surface of the first type semiconductor layer;

A transparent conductive layer is formed on the first current blocking layer on the surface of the second type semiconductor.

beneficial effect

Compared with the prior art, the present application at least has the following beneficial effects:

1) In this application, a third pad is formed at least in the central area of the high-voltage flip-chip light-emitting diode chip. When the ejector pin acts on the central area of the chip, the third pad can prevent the ejector pin from piercing the protective layer and improve the performance of the chip. reliability;

2) The third pad and the protective layer at the corresponding recessed area form a total reflection structure, which enhances the reflectivity of the protective layer at the corresponding recessed area and improves the luminous efficiency of the chip.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following drawings will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

1 to 7 are schematic cross-sectional views of a high-voltage flip-chip light-emitting diode chip in different fabrication processes according to embodiments of the present application;

8 is a schematic cross-sectional view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

9 is a schematic cross-sectional view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

10 is a schematic cross-sectional view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

11 is a schematic cross-sectional view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

12 is a schematic cross-sectional view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

13 is a schematic cross-sectional view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

14 is a schematic cross-sectional view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

FIG. 15 is a top view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

FIG. 16 is a top view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

FIG. 17 is a top view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

FIG. 18 is a top view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

FIG. 19 is a top view of a high-voltage flip-chip light emitting diode chip according to an embodiment of the present application

FIG. 20 is a top view of a high-voltage flip-chip light-emitting diode chip according to an embodiment of the present application;

FIG. 21 is a top view of a high-voltage flip-chip light emitting diode chip according to an embodiment of the present application.

Illustration description:

100 substrate; 200 sub-chip; 210 semiconductor stack layer; 211 first type semiconductor layer; 212 active layer; 213 second type semiconductor layer; 220 first current blocking layer; 230 transparent conductive layer; 241 first electrode; 242 Interconnection electrode; 243 second electrode; 250 second current blocking layer; 260 isolation trench; 300 protective layer; 310 recessed area; 320 first opening; 330 second opening; 410 first pad; 420 second pad; 430 third pad.

Embodiments of the present invention

The embodiments of the present application are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or operated through other different specific embodiments, and various details in the present application can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

In the description of this application, it should be noted that the orientations or positional relationships indicated by the terms "left" and "right" are based on the orientations or positional relationships shown in the accompanying drawings, or are usually placed when the product of the application is used. The orientation or positional relationship is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present application. Furthermore, the terms "first" and "second" etc. are only used to differentiate the description and should not be construed to indicate or imply relative importance.

According to one aspect of the present application, a high voltage flip-chip light emitting diode chip is provided. Referring to FIG. 7 to FIG. 14 , the high voltage flip-chip light emitting diode chip includes a plurality of sub-chips 200 and a protective layer 300 . The adjacent sub-chips 200 are separated by isolation trenches 260 , and the adjacent sub-chips 200 are electrically connected. Each chiplet 200 includes a semiconductor stack layer 210 including a first type semiconductor layer 211 , an active layer 212 and a second type semiconductor layer 213 . The sub-chip 200 is defined as a first sub-chip, a second sub-chip, and an n-th sub-chip in sequence, where n is the number of sub-chips. The protective layer 300 covers the sub-chips 200 and the isolation trenches 260 between adjacent sub-chips 200 , and a recessed area 310 is formed on the protective layer 300 located at the isolation trenches 260 . A third pad 430 is formed at least in the concave region 310 in the central region of the high voltage flip-chip light emitting diode chip. The first type semiconductor layer 211 of the first sub-chip is connected to the first pad 410 ; the second type semiconductor layer 213 of the nth sub-chip is connected to the second pad 420 . Here, the central area of the high voltage flip-chip light emitting diode chip refers to the central area of the top view thereof.

The sub-chips 200 are sequentially defined as a first sub-chip, a second sub-chip, and an n-th sub-chip from right to left, where n is the number of sub-chips. The definition sequence of the sub-chips 200 can be adaptively adjusted according to the arrangement of the sub-chips 200 in the high voltage flip-chip LED chip.

The working process and working principle of this application are as follows:

In the present application, a third pad 430 is formed at least on the recessed area 310 corresponding to the central region of the high-voltage flip-chip LED chip. When the ejector pin acts on the central region of the chip, the third pad 430 can prevent the ejector pin from being punctured. The protective layer 300 improves the reliability of the chip.

The following is a description of the specific implementation structure of the high-voltage flip-chip light-emitting diode chip:

实施例Example 11

Referring to FIGS. 7 to 13 , the high-voltage flip-chip light emitting diode chip includes a substrate 100 , a plurality of sub-chips 200 and a protective layer 300 from bottom to top, and adjacent sub-chips 200 are separated by isolation grooves 260 , and adjacent sub-chips 200 Electrical connection between 200. Each chiplet 200 includes a semiconductor stack layer 210 including a first type semiconductor layer 211 , an active layer 212 and a second type semiconductor layer 213 from bottom to top.

The first-type semiconductor layer 211 is an N-type semiconductor layer, the second-type semiconductor layer 213 is a P-type semiconductor layer, and the active layer 212 is a multi-layer quantum well layer. The N-type semiconductor layer, the multi-layer quantum well layer, and the P-type semiconductor layer are only the basic constituent units of the semiconductor stack layer 210. On this basis, the semiconductor stack layer 210 may also include other components optimized for the performance of the high-voltage flip-chip light-emitting diode chip. The functional structural layer of action.

The protective layer 300 covers the isolation trenches 260 between the chiplets 200 and adjacent chiplets 200 . The protective layer 300 located at the isolation trench 260 is formed with a concave region 310 , the protective layer 300 corresponding to the first sub-chip is respectively provided with first openings 320 , and the protective layer 300 corresponding to the n-th sub-chip is provided with a second opening 330 . At least a third pad 430 is formed on the concave area 310 corresponding to the central area of the high-voltage flip-chip LED chip, and the third pad 430 can prevent the thimble from piercing the protective layer 300 or the sub-chip when the thimble acts on the central area 200, which improves the reliability of the chip. In addition, the third pad 430 and the protective layer 300 corresponding to the recessed area 310 form a total reflection structure, which further improves the luminous efficiency of the chip.

The first pad 410 is formed at the first opening 320 and is electrically connected to the first type semiconductor layer 211 in the first sub-chip through the first opening 320 . The second pad 420 is formed at the second opening 330 and is electrically connected to the second type semiconductor layer 213 in the nth sub-chip through the second opening 330 .

In one embodiment, referring to FIG. 7 , the thickness D ₁ of the protective layer directly above the sub-chip 200 refers to the thickness of the upper surface of the protective layer directly above the sub-chip from the second type semiconductor layer 213 , which is different from the thickness D 1 of the protective layer directly above the sub-chip. The ratio of the thickness D ₂ of the protective layer on the sidewall of 310 is between 1 and 2. Preferably, the thickness D ₁ of the protective layer directly above the sub-chip 200 is between 1 μm and 6 μm; the thickness D ₂ of the protective layer at the sidewall of the recessed region 310 is between 0.50 μm and 5 μm. In this embodiment, the thickness D ₁ of the protective layer directly above the sub-chip 200 is 1 μm, and the thickness D ₂ of the protective layer at the sidewall of the recessed region 310 is 0.50 μm. Alternatively, the thickness D ₁ of the protective layer directly above the sub-chip 200 is 2 μm, and the thickness D ₂ of the protective layer at the sidewall of the recessed region 310 is 2 μm.

The maximum thickness D ₃ of the protective layer corresponding to the bottom of the recessed region 310 is the same as the thickness D ₁ of the protective layer located directly above the sub-chip 200 , that is, the maximum thickness D ₃ of the protective layer corresponding to the bottom of the recessed region 310 is between 1 μm and 6 μm. The ratio of the thickness D ₂ of the protective layer on the sidewall of the recessed region 310 is between 1 and 2.

In one embodiment, referring to FIG. 7 , there is one third pad 430 , and the third pad 430 is spaced apart from the first pad 410 and the second pad 420 . The third pads 430 cover the bottom and sidewalls of the corresponding recessed region 310 ; alternatively, the third bonding pads 430 cover the bottom and sidewalls of the corresponding recessed region 310 and the upper surface of the protective layer 300 near the recessed region 310 .

The thicknesses of the third pads 430 , the first pads 410 and the second pads 420 are the same or different, and the thicknesses are all between 0.5 μm and 10 μm. The thickness of the two bonding pads 420 is between 2 μm and 3 μm. In this embodiment, the thickness of the third bonding pad 430 , the first bonding pad 410 and the second bonding pad 420 is 2.5 μm. The third pad 430 , the first pad 410 and the second pad 420 are made of the same material, which is a metal material, specifically any combination of Au, Ti, Al, Cr, Pt, TiW alloy or Ni.

Preferably, the third pad 430 is a polygonal structure or a circular structure. The area of the third pad 430 is greater than 300 μm ² . Preferably, its area is between 300 μm ² and 1000 μm ² . For example, when the third pad 430 has a square structure, its side length is greater than 20 μm, and preferably, its side length is between 20 μm and 35 μm. When the third pad 430 has a circular structure, its diameter is greater than 20 μm, and preferably, its diameter is between 20 μm and 35 μm.

As an alternative embodiment, there are multiple third pads 430 . The third pads 430 are spaced apart from the first pads 410 and the second pads 420 ; or, referring to FIGS. 8 and 9 , a part of the third pads 430 is formed by extending the first pads 410 or the second pads 420 Alternatively, all the third pads 430 are formed by extending from the first pad 410 or the second pad 420 .

As an alternative embodiment, referring to FIGS. 10 to 13 , each recessed area 310 corresponds to a third pad 430 . The third pads 430 are spaced apart from the first pads 410 and the second pads 420; or, part of the third pads 430 is formed by extending the first pad 410 or the second pad 420; or, all the third pads 430 The pad 430 is formed by extending the first pad 410 or the second pad 420 .

In the above embodiment, the reflectivity of the protective layer 300 to the chip can be adjusted by adjusting the number of the third pads 430 , so as to improve the luminous efficiency of the chip. As the number of the third pads 430 increases, the luminous efficiency of the chip also increases.

It should be noted that the present application describes the structure of a high-voltage flip-chip light emitting diode chip including four or two sub-chips 200 with reference to FIGS. 7 to 10 and FIGS. 11 to 13 respectively, and the number of the sub-chips 200 is other When the number is used, it also applies to the protection scope of this application.

In one embodiment, referring to FIG. 15 , the plurality of sub-chips 200 are arranged in a row along the length direction of the substrate 100 , and the first pads 410 and the second pads 420 are respectively located at two positions of the substrate 100 along the length direction of the substrate 100 . end. The number of sub-chips 200 is an even number. In this embodiment, the number of the sub-chips 200 is 4, and the sub-chips 200 are defined in order from right to left as: a first sub-chip, a second sub-chip, a third sub-chip and a fourth sub-chip. The first pad 410 is located on the first sub-chip, and the second pad 420 is located on the fourth sub-chip. The third pad 430 is located on the recessed area 310 between the second sub-chip and the third sub-chip.

As an alternative embodiment, referring to FIGS. 16 to 17 , the plurality of sub-chips 200 are arranged in even rows, and the even-numbered rows of sub-chips 200 are spaced apart by a predetermined distance in the width direction of the substrate 100 . For example, the arrangement of the sub-chips 200 is 2 rows×4 columns. Referring to FIG. 16 , the sub-chips 200 are arranged in a U shape, the sub-chips 200 are defined according to their arrangement directions, and the first pads 410 and the second pads 420 are respectively located at two ends of the substrate 100 along its width direction. Referring to FIG. 17 , the sub-chips 200 are arranged in a serpentine shape, the sub-chips 200 are defined according to their arrangement directions, and the first pads 410 and the second pads 420 are respectively located at two ends of the substrate 100 along the length direction thereof. In the above two arrangement directions, the third pads 430 are both located on the recessed area 310 corresponding to the central area of the high voltage flip-chip LED chip.

As an alternative embodiment, referring to FIGS. 18 to 19 , the plurality of chiplets 200 are arranged in even columns, and the even columns of chiplets 200 are spaced apart by a predetermined distance in the length direction of the substrate 100 . For example, the arrangement of the sub-chips 200 is 3 rows×4 columns. Referring to FIG. 18 , the sub-chips 200 are arranged in an S-shape, and the sub-chips 200 are defined according to their arrangement directions; referring to FIG. 19 , the sub-chips 200 are arranged in a serpentine shape, and the sub-chips 200 are defined according to their arrangement directions; , the first pad 410 and the second pad 420 are located at two ends of the substrate 100 along the length direction thereof, respectively, and the third pad 430 is located in the depression corresponding to the central region of the high-voltage flip-chip LED chip. District 310.

In this application, the length of the substrate 100 extends in the direction indicated by arrow 1 ; the width of the substrate 100 extends in the direction indicated by arrow 2 . It should be noted that, the direction of arrow 1 and the direction of arrow 2 are defined only for the convenience of description, and are not used to define the orientation of the substrate 100 .

In one embodiment, the protective layer 300 includes a distributed Bragg reflector (DBR); alternatively, the protective layer 300 includes one or more of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, or a silicon oxynitride layer; Alternatively, the protective layer 300 includes an aluminum oxide layer.

In one embodiment, referring to FIG. 7 , the high voltage flip-chip LED chip further includes a first electrode 241 , a second electrode 243 and an interconnection electrode 242 , the first electrode 241 and the first type semiconductor in the first sub-chip The layer 211 is electrically connected; the second electrode 243 is electrically connected to the second type semiconductor layer 213 in the nth sub-chip; the interconnection electrode 242 extends from the surface of the second type semiconductor layer 213 in one sub-chip 200 to the adjacent sub-chip 200 on the surface of the first type semiconductor layer 211 to electrically connect two adjacent sub-chips 200 .

Each of the chiplets 200 includes a first current blocking layer 220 and a transparent conductive layer 230 formed on the second type semiconductor layer 213 . The area covered by the first current blocking layer 220 includes: part of the surface of the second type semiconductor layer 213 of one sub-chip 200 and sidewalls of the semiconductor stack layer 210 , the isolation trench 260 and part of the first type of sub-chip adjacent to the sub-chip The surface of the semiconductor layer 211 , that is, the first current blocking layer 220 extends from the surface of the second type semiconductor layer 213 in one sub-chip 200 to the surface of the first type semiconductor layer 211 in the adjacent sub-chip 200 through the isolation trench 260 .

The transparent conductive layer 230 covers part of the surface of the first current blocking layer 220 located on the surface of the second type semiconductor layer 213 .

The preparation material of the first current blocking layer 220 is selected from one or more of silicon oxide, silicon nitride, silicon carbide or silicon oxynitride. The preparation material of the transparent conductive layer 230 is a conductive material with transparent properties, which specifically includes thin metals such as gold and nickel or oxides selected from metals such as zinc, indium, and tin. In this embodiment, the preparation material of the transparent conductive layer 230 It is indium tin oxide.

实施例Example 22

This embodiment has many of the same features as Embodiment 1. The difference between this embodiment and Embodiment 1 is that the high-voltage flip-chip light emitting diode chip further includes a second current blocking layer 250 . Here, the same features will not be described one by one, and only the differences will be described.

14 , the area covered by the first current blocking layer 220 includes: a part of the surface of the second type semiconductor layer 213 , that is, the first current blocking layer 220 is located on the surface of the second type semiconductor layer 213 . The transparent conductive layer 230 covers the surface of the first current blocking layer 220 . A second current blocking layer 250 is also formed between the transparent conductive layer 230 and the interconnection electrode 242 , and the area covered by the second current blocking layer 250 includes: part of the surface of the transparent conductive layer 230 of a sub-chip 200 , part of the second type semiconductor layer 213 surface and sidewalls of the semiconductor stack layer 210 , the isolation trench 260 , and part of the surface of the first type semiconductor layer 211 of the chiplet adjacent to the chiplet.

Preferably, the preparation material of the second current blocking layer 250 is selected from one or more of silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.

In this embodiment, the first current blocking layer 220 and the second current blocking layer 250 are respectively formed before and after the transparent conductive layer 230 , and the first current blocking layer 220 only covers part of the surface of the second type semiconductor layer 213 . When the layer 230 is annealed at a high temperature, the first current blocking layer 220 can be prevented from damaging the active region 212, thereby improving the reliability of the chip.

实施例Example 33

This embodiment has many of the same features as Embodiment 1 or Embodiment 2. The difference between this embodiment and Embodiment 1 or Embodiment 2 is that the first pad 410 and the second pad 420 are close to the third pad 430 The sides of the s are arc-shaped, and the arc-shaped opening faces the third pad 430 . Here, the same features will not be described one by one, and only the differences will be described.

Referring to FIG. 20 , a high voltage flip-chip light emitting diode chip including two sub-chips 20 is exemplified. The third pads 430 are spaced apart from the first pads 410 and the second pads 420 . The sides of the first pad 410 and the second pad 420 close to the third pad 430 are arc-shaped, and the arc-shaped opening faces the third pad 430 , which can increase the size of the first pad 410 and the second pad 420 The distance between the high-voltage flip-chip light-emitting diode chips can avoid the short-circuit problem when the high-voltage flip-chip light-emitting diode chip is flip-chip welded.

As an alternative embodiment, referring to FIG. 21 , the third pad 430 is formed by extending from the first pad 410 or the second pad 420 . Then, the sides of the first pad 410 and the second pad 420 close to each other are arc-shaped, and the arc-shaped openings are opposite to each other, which can avoid the problem of short circuit easily occurring when the high-voltage flip-chip LED chip is flip-chip welded.

According to another aspect of the present application, a method for fabricating the high-voltage flip-chip light emitting diode chip in the above embodiment is provided.

The preparation method of the high-voltage flip-chip light-emitting diode chip includes the following steps:

S1. A plurality of sub-chips 200 are formed on the substrate 100, and adjacent sub-chips 200 are separated by isolation grooves 260; the number of sub-chips.

In one embodiment, forming a plurality of sub-chips 200 on the substrate 100, and separating adjacent sub-chips 200 by isolation trenches 260 includes the following steps:

S11 . Referring to FIGS. 1 to 2 , intermittently arranged semiconductor stack layers 210 are formed on the substrate 100 .

Referring to FIG. 1 , a semiconductor stack layer 210 is formed on the upper surface of the substrate 100 , and the semiconductor stack layer 210 is formed on the substrate by means of physical vapor deposition (PVD), chemical vapor deposition (CVD), epitaxial growth or atomic layer deposition (ALD). Bottom 100. The semiconductor stack layer 210 includes a first type semiconductor layer 211 , an active region 212 and a second type semiconductor layer 213 . In this embodiment, the substrate 100 is a sapphire patterned substrate or a sapphire flat bottom substrate. The first type semiconductor layer 211 is an N type semiconductor layer, the second type semiconductor layer 213 is a P type semiconductor layer, and the active region 212 is a multilayer quantum well layer.

Referring to FIG. 2 , isolation trenches 260 are etched on the semiconductor stack layer 210 to form discontinuously arranged semiconductor stack layers 210 .

Preferably, the semiconductor stack layer 210 is etched and the inside of the first type semiconductor layer 211 is exposed.

S12. Referring to FIG. 3, the first current blocking layer 220 is formed on the surface, sidewalls and the isolation trench 260 of the semiconductor stack layer 210, and the first current blocking layer 220 is etched, so that the etched first current blocking layer 220 The covered area includes a part of the surface of the second type semiconductor layer 213 , the sidewall of the semiconductor stack layer 210 , the isolation trench 260 and a part of the exposed surface of the first type semiconductor layer 211 . The first current blocking layer 220 is an oxide of silicon, and specifically includes one or more of silicon oxide, silicon nitride, silicon carbide or silicon oxynitride, which may adopt a plasma-enhanced chemical vapor deposition method (PECVD), etc. method is formed.

S13 . Referring to FIG. 4 , a transparent conductive layer 230 is formed on the first current blocking layer 220 located on the surface of the second type semiconductor layer 213 . The material of the transparent conductive layer 230 is generally selected from conductive materials with transparent properties, including thin metals such as gold and nickel or oxides selected from metals such as zinc, indium, and tin. In this embodiment, the material of the transparent conductive layer 230 is oxide Indium Tin. The transparent conductive layer 230 can be formed on the first current blocking layer 220 by techniques such as electron beam evaporation or ion beam sputtering, which mainly plays the role of ohmic contact and lateral current spreading.

S14. Referring to FIG. 5, form a first electrode 241 connected to the first type semiconductor layer 211 in the first sub-chip, a second electrode 243 connected to the second type semiconductor layer 213 in the n-th sub-chip, and connecting adjacent sub-chips Interconnect electrode 242 of 200 . The materials of the first electrode 241, the second electrode 243 and the interconnection electrode 242 include one material such as Al, Ni, Ti, Pt, Au, etc. or an alloy composed of at least two of these materials, and can be deposited by electron beam evaporation. Or formed by techniques such as ion beam sputtering.

As an alternative embodiment, the steps of its changes are as follows:

In step S12 , a first current blocking layer 220 is formed on the surface of the semiconductor stack layer 210 , and the area covered by the first current blocking layer 220 includes part of the surface of the second type semiconductor layer 213 .

In step S13 , a transparent conductive layer 230 is formed on the surface of the first current blocking layer 220 .

Before step S14 and after step S13, the method further includes: forming a second current blocking layer 250 on the transparent conductive layer 230, and the area covered by the second current blocking layer 250 includes part of the transparent conductive layer 230 and part of the surface of the second type semiconductor layer 213 , the sidewall of the semiconductor stack layer 210 , the isolation trench 260 and the partially exposed surface of the first type semiconductor layer 211 .

S2. A protective layer 300 is formed on the sub-chips 200 and on the isolation trenches 260 between adjacent sub-chips 200; The protective layer 300 is etched to form a first opening 320 for mounting the first pad 410 and a second opening 330 for mounting the second pad 420 .

In one embodiment, referring to FIG. 6 , a protective layer 300 is formed on the plurality of sub-chips 200 and the isolation trenches 260 , and a recessed region 310 is formed on the protective layer 300 at the isolation trench 260 . The protective layer 300 includes a distributed Bragg reflector (DBR); alternatively, the protective layer 300 includes one or more of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer or a silicon oxynitride layer; alternatively, the protective layer 300 includes an oxide layer aluminum layer.

S3 , forming a third pad 430 , a first pad 410 and a second pad 420 at least at the recessed area 310 , the first opening 320 and the second opening 330 in the central region of the high voltage flip-chip light emitting diode chip, respectively.

In one embodiment, referring to FIG. 7 , a third pad 430 , a first pad 410 and a The second pad 420 . The third pads 430 are formed in the recessed area 310 in the central region of the chip, the first pads 410 are formed at the first openings 320 , and the second pads 420 are formed at the second openings 330 . The preparation material of the first pad 410 , the second pad 420 and the third pad 430 is a metal material, specifically any combination of Au, Ti, Al, Cr, Pt, TiW alloy or Ni. It should be noted that, the third pad 430 , the first pad 410 and the second pad 420 may be formed at the same time, or may be formed sequentially.

Preferably, the third pads 430 at least cover the bottom and sidewalls of the corresponding recessed regions 310 .

Preferably, the third pad 430 covers the bottom and sidewalls of the corresponding recessed area 310 and the upper surface of the protective layer 300 near the recessed area 310 .

Preferably, the third pad 430 and the protective layer 300 at the corresponding recessed area 310 form a total reflection structure.

Preferably, the third pad 430 is spaced apart from the first pad 410 and the second pad 420 .

Preferably, the third pad 430 is formed by extending from the first pad 410 or the second pad 420 .

Preferably, at least one recessed area 310 is formed with a third pad 430 .

Preferably, the area of the third pad 430 is greater than 300 μm ² . The thicknesses of the third pads 430 , the first pads 410 and the second pads 420 are all between 0.5 μm and 10 μm. Preferably, the thicknesses of the third pads 430 , the first pads 410 and the second pads 420 are 2.5μm.

As can be seen from the above technical solutions, the present application forms a third pad 430 at least on the recessed area 310 corresponding to the central area of the high-voltage flip-chip LED chip. When the ejector pin acts on the central area of the chip, the third pad is formed. The disk 430 can prevent the ejector pin from piercing the protective layer 300, thereby improving the reliability of the chip.

Further, the third pad 430 and the protective layer 300 corresponding to the recessed area 310 form a total reflection structure, which enhances the reflectivity of the protective layer 300 corresponding to the recessed area 310 and improves the luminous efficiency of the chip. By adjusting the number of the third pads 430 , the reflectivity of the protective layer 300 to the chip can be adjusted, so as to improve the luminous efficiency of the chip.

The above are only the preferred embodiments of the present application. It should be pointed out that for those skilled in the art, without departing from the technical principles of the present application, several improvements and replacements can be made. These improvements and replacements It should also be regarded as the protection scope of this application.

Claims

A high-voltage flip-chip light-emitting diode chip, characterized by comprising:

A plurality of sub-chips, the adjacent sub-chips are separated by isolation grooves, and the adjacent sub-chips are electrically connected; each of the sub-chips includes a semiconductor stack layer, and the semiconductor stack layer includes a first type semiconductor layer, active layer and second type semiconductor layer; wherein, the sub-chips are defined as a first sub-chip, a second sub-chip, and an n-th sub-chip in sequence;

a protective layer covering the sub-chips and the isolation grooves between the adjacent sub-chips; the protective layer located at the isolation grooves is formed with a concave area;

a first pad, electrically connected to the first type semiconductor layer of the first sub-chip;

a second pad, electrically connected to the second type semiconductor layer of the nth sub-chip;

The third pad is located at least on the recessed area in the central area of the high-voltage flip-chip light emitting diode chip.
The high-voltage flip-chip light emitting diode chip according to claim 1, wherein the third pad covers at least the bottom and sidewalls of the corresponding recessed area.
The high voltage flip-chip light emitting diode chip according to claim 1, wherein the third pad covers the bottom and sidewalls of the corresponding recessed area and the upper surface of the protective layer near the corresponding recessed area.
The high-voltage flip-chip light-emitting diode chip according to claim 1, wherein the third pad and the protective layer at the corresponding recessed area form a total reflection structure.
The high-voltage flip-chip light emitting diode chip according to claim 1, wherein the area of the third pad is greater than 300 μm 2 .
The high-voltage flip-chip light emitting diode chip according to claim 1, wherein the thickness of the third pad is between 0.5 μm and 10 μm.
The high-voltage flip-chip light emitting diode chip of claim 1, wherein a ratio of the thickness of the protective layer directly above the sub-chip to the thickness of the protective layer located on the sidewall of the recessed region is between 1 ~2.
The high-voltage flip-chip light emitting diode chip according to any one of claims 1 to 7, wherein the third pad is arranged at intervals from the first pad and the second pad.
The high-voltage flip-chip light emitting diode chip according to claim 8, wherein the sides of the first pad and the second pad close to the third pad are arc-shaped, and the arc-shaped opening faces the third pad. pad.
The high-voltage flip-chip light emitting diode chip according to any one of claims 1 to 7, wherein the third pad is formed by extending from the first pad or the second pad.
The high-voltage flip-chip light emitting diode chip according to any one of claims 1 to 7, wherein the third pad is formed in at least one of the recessed regions.
The high-voltage flip-chip light emitting diode chip according to claim 1, wherein the protective layer comprises a distributed Bragg reflector (DBR);

Alternatively, the protective layer includes one or more of a silicon oxide layer, a silicon nitride layer, a silicon carbide layer or a silicon oxynitride layer;

Alternatively, the protective layer includes an aluminum oxide layer.
The high-voltage flip-chip light-emitting diode chip according to claim 1, characterized in that, comprising:

a first electrode, connected to the first type semiconductor layer in the first sub-chip;

a second electrode, connected to the second type semiconductor layer in the nth sub-chip;

The interconnection electrodes connect the adjacent sub-chips.
14. The high voltage flip-chip light emitting diode chip of claim 13, wherein each of the sub-chips includes a first current blocking layer and a transparent conductive layer formed on the second type semiconductor layer.
A method for preparing a high-voltage flip-chip light-emitting diode chip according to any one of claims 1 to 14, characterized in that, comprising:

A plurality of the sub-chips are formed on the substrate, and the adjacent sub-chips are separated by isolation grooves; the sub-chips are sequentially defined as a first sub-chip, a second sub-chip, and an n-th sub-chip;

The protective layer is formed on the sub-chips and the isolation trenches between the adjacent sub-chips; the concave region is formed on the protective layer located at the isolation trench; the protective layer is etched to form a first opening for mounting the first pad and a second opening for mounting the second pad;

The third pad, the first pad and the second pad are respectively formed at least at the recessed area, the first opening and the second opening in the central region of the high voltage flip-chip light emitting diode chip.
The method for manufacturing a high-voltage flip-chip light-emitting diode chip according to claim 15, wherein forming a plurality of the sub-chips on a substrate, and spacing between adjacent sub-chips by an isolation trench comprises:

Forming intermittently arranged semiconductor stack layers on the substrate; the semiconductor stack layers including a first type semiconductor layer, an active layer and a second type semiconductor layer;

forming a first electrode connected to the semiconductor layer of the first type in the first sub-chip, a second electrode connected to the semiconductor layer of the second type in the n-th sub-chip, and an interconnect electrode connected to the adjacent sub-chips .
The method for fabricating a high-voltage flip-chip light emitting diode chip according to claim 16, characterized in that in forming a first electrode connected to the first type semiconductor layer in the first sub-chip, and in the n-th sub-chip Before the second electrode connected to the second type semiconductor layer and the interconnection electrode connected to the adjacent sub-chips, an intermittently arranged semiconductor stack layer is formed on the substrate, and the semiconductor stack layer includes the first type semiconductor layer, the After the source layer and the second type semiconductor layer, it also includes:

A first current blocking layer is formed on the surface of the second type semiconductor layer, and the area covered by the first current blocking layer includes part of the surface of the second type semiconductor layer, the sidewall of the semiconductor stack layer and part of the first current blocking layer type of semiconductor layer surface;

A transparent conductive layer is formed on the first current blocking layer on the surface of the second type semiconductor.