CN111987208B

CN111987208B - Light-emitting element

Info

Publication number: CN111987208B
Application number: CN202010788076.0A
Authority: CN
Inventors: 陈昭兴; 王佳琨; 曾咨耀; 胡柏均; 蒋宗勋; 庄文宏; 李冠亿; 林昱伶; 沈建赋; 柯淙凯
Original assignee: Epistar Corp
Current assignee: Epistar Corp
Priority date: 2015-11-18
Filing date: 2015-11-18
Publication date: 2023-07-04
Anticipated expiration: 2035-11-18
Also published as: CN111987210A; CN111987209A; CN111987208A; CN111987211B; CN106711316A; CN111987211A; CN106711316B

Abstract

The invention discloses a light-emitting element, which comprises a semiconductor lamination layer, a first semiconductor layer, a second semiconductor layer and an active layer, wherein the active layer is positioned between the first semiconductor layer and the second semiconductor layer; one or more holes through the active layer to expose the first semiconductor layer; a first contact layer covering one or more hole portions; a third insulating layer including one or more third insulating layer openings exposing the first contact layer; a first bonding pad, which is positioned on the semiconductor lamination and covers one or more third insulating layer openings; and a second bonding pad on the semiconductor layer stack at a distance from the first bonding pad, defining a region on the semiconductor layer stack between the first bonding pad and the second bonding pad, wherein the second bonding pad is formed in a region other than the one or more hole portions in a top view of the light emitting device.

Description

Light-emitting element

The present application is a divisional application of Chinese patent application (application number: 201510794248.4, application date: 2015, 11, 18, title of the invention: light emitting element).

Technical Field

The present invention relates to a light emitting device, and more particularly, to a light emitting device including a semiconductor stack and a bonding pad on the semiconductor stack.

Background

A Light-Emitting Diode (LED) is a solid-state semiconductor Light-Emitting element, and has advantages of low power consumption, low generated heat energy, long service life, vibration resistance, small volume, high reaction speed, and good photoelectric characteristics, such as stable Light emission wavelength. Therefore, the light emitting diode is widely used in household appliances, equipment indication lamps, photoelectric products and the like.

Disclosure of Invention

The light-emitting element comprises a semiconductor lamination layer, a first semiconductor layer, a second semiconductor layer and an active layer, wherein the active layer is positioned between the first semiconductor layer and the second semiconductor layer; one or more holes through the active layer to expose the first semiconductor layer; a first contact layer covering one or more hole portions; a third insulating layer including one or more third insulating layer openings exposing the first contact layer; a first bonding pad, which is positioned on the semiconductor lamination and covers one or more third insulating layer openings; and a second bonding pad on the semiconductor layer stack at a distance from the first bonding pad, defining a region on the semiconductor layer stack between the first bonding pad and the second bonding pad, wherein the second bonding pad is formed in a region other than the one or more hole portions in a top view of the light emitting device.

Drawings

Fig. 1A to 7C are schematic views illustrating a method for manufacturing a light emitting device 1 or a light emitting device 2 according to an embodiment of the invention;

fig. 8 is a top view of a light emitting device 1 according to an embodiment of the present invention;

fig. 9A is a cross-sectional view of a light-emitting element 1 according to an embodiment of the present invention;

fig. 9B is a cross-sectional view of the light-emitting element 1 disclosed in an embodiment of the present invention;

fig. 10 is a top view of a light emitting device 2 according to an embodiment of the present invention;

fig. 11A is a cross-sectional view of a light-emitting element 2 according to an embodiment of the present invention;

fig. 11B is a cross-sectional view of a light-emitting element 2 according to an embodiment of the present invention;

fig. 12A to 18B are schematic views illustrating a method for manufacturing the light emitting element 3 or the light emitting element 4 according to an embodiment of the present invention;

fig. 19 is a top view of a light emitting element 3 according to an embodiment of the present invention;

fig. 20 is a cross-sectional view of a light-emitting element 3 disclosed in an embodiment of the present invention;

fig. 21 is a top view of a light emitting device 4 according to an embodiment of the present invention;

fig. 22 is a cross-sectional view of a light-emitting element 4 disclosed in an embodiment of the present invention;

fig. 23 is a cross-sectional view of a light-emitting element 5 disclosed in an embodiment of the present invention;

Fig. 24 is a cross-sectional view of a light-emitting element 6 disclosed in an embodiment of the present invention;

FIG. 25 is a schematic diagram of a light emitting device according to an embodiment of the invention;

fig. 26 is a schematic structural diagram of a light emitting device according to an embodiment of the invention.

Symbol description

1,2,3,4,5,6 light emitting element

11a,11b substrates

10a,10b semiconductor stacks

101a,101b first semiconductor layer

102a,102b second semiconductor layer

103a,103b active layer

100a,100b well

102s surface

First surfaces of 1011a,1011b

Second surfaces of 1012a,1012b

110a fourth insulating layer

111a,111b encircling portions

20a,20b first insulating layer

200a,200b first insulating layer surrounding region

201a,201b first insulating layer coverage area

202a,202b first insulating layer openings

203a,203b first insulating layer openings

30a,30b transparent conductive layer

300b transparent conductive layer opening

301a,301b transparent conductive layer outer edges

40a,40b reflective layer

400b reflective layer openings

Outer edges of 401a,401b reflective layers

41a,41b barrier layer

410b barrier layer opening

Outer edges of

barrier layers

411a,411b

50a,50b second insulating layer

501a,501b second insulating layer openings

502a,502b second insulating layer openings

5020b ring opening

5021b side wall

60a,60b contact layer

600a,600b thimble region

602a contact layer openings

601b first contact layer

6011b first contact layer sidewall

602b second contact layer

6021b second contact layer sidewall

70a,70b third insulating layer

Openings in the third insulating

layer

702a, 702a

702b, 702b third insulating layer openings

80a,80b first bonding pad

90a,90b second bonding pad

800a first bond pad opening

801b first protrusion

802a first side

802b first recess

803b first flat edge

804a first recess

805a first upper layer bonding pad

807a first lower layer bonding pad

810a first cushion pad

900a second bond pad opening

901b second convex part

902a second side

902b second recess

903b second flat edge

904a second recess

905a second upper layer pad

907a second lower layer bonding pad

910a,910b second bumper pad

1000a,1000b semiconductor structure

Side walls of

sides

100 a,1001b

Inner side walls of 1002a,1002b

1003a,1003b first outer side wall

51. Packaging substrate

511. First gasket

512. Second gasket

53. Insulation part

54. Reflection structure

600. Bulb lamp

602. Lampshade

604. Reflecting mirror

606. Bearing part

608. Light-emitting element

610. Light emitting module

612. Lamp holder

614. Heat sink

616. Connecting part

618. Electric connecting element

Detailed Description

For a more complete and thorough description of the present invention, reference is made to the following description of embodiments taken in conjunction with the accompanying drawings. However, the following examples are given by way of illustration of the light-emitting element of the present invention, and the present invention is not limited to the following examples. The dimensions, materials, shapes, relative arrangements, and the like of the constituent parts described in the embodiments are not limited to those described in the specification, and the scope of the present invention is not limited thereto but only by a simple description. And the sizes, positional relationships, etc. of the members shown in the drawings may be exaggerated for clarity of explanation. In the following description, the same or similar members are denoted by the same names and symbols, respectively, for the purpose of omitting detailed descriptions.

Fig. 1A to 11B illustrate a method for manufacturing a light emitting element 1 or a light emitting element 2 according to an embodiment of the present invention.

As shown in the top view of fig. 1A and the cross-sectional view of fig. 1B along line A-A' of fig. 1A, the method for manufacturing the

light emitting device

1 or 2 includes a mesa formation step including providing a substrate 11A; and forming a semiconductor stack 10a on the substrate 11a, wherein the semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a disposed between the first semiconductor layer 101a and the second semiconductor layer 102 a. The semiconductor stack 10a may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102a and the active layer 103a, thereby forming one or more semiconductor structures 1000a; and a surrounding portion 111a surrounds one or more of the semiconductor structures 1000a. The surrounding portion 111a exposes a first surface 1011a of the first semiconductor layer 101 a. The one or more semiconductor structures 1000a each include a plurality of first outer sidewalls 1003a, a second outer sidewall 1001a, and a plurality of inner sidewalls 1002a, wherein the first outer sidewall 1003a is a sidewall of the first semiconductor layer 101a, the second outer sidewall 1001a is a sidewall of the active layer 103a and/or the second semiconductor layer 102a, one end of the second outer sidewall 1001a is connected to a surface 102s of the second semiconductor layer 102a, and the other end of the second outer sidewall 1001a is connected to the first surface 1011a of the first semiconductor layer 101 a; one end of the inner sidewall 1002a is connected to the surface 102s of the second semiconductor layer 102a, and the other end of the inner sidewall 1002a is connected to the second surface 1012a of the first semiconductor layer 101 a; the plurality of semiconductor structures 1000a are connected to each other through the first semiconductor layer 101 a. As seen in fig. 1B, the inner sidewall 1002a of the semiconductor structure 1000a has an obtuse angle with the second surface 1012a of the first semiconductor layer 101a, the first outer sidewall 1003a of the semiconductor structure 1000a has an obtuse angle or a straight angle with the surface 11s of the substrate 11a, and the second outer sidewall 1001a of the semiconductor structure 1000a has an obtuse angle with the first surface 1011a of the first semiconductor layer 101 a. The surrounding portion 111a surrounds the semiconductor structure 1000a, and the surrounding portion 111a has a rectangular shape or a polygonal shape in a top view of the light emitting element 1 or the light emitting element 2.

In one embodiment of the present invention, the light emitting element 1 or the light emitting element 2 comprises a side length of less than 30mil. When an external current is injected into the light emitting element 1 or the light emitting element 2, the surrounding portion 111a surrounds the semiconductor structure 1000a, so that the light field distribution of the light emitting element 1 or the light emitting element 2 can be homogenized, and the forward voltage of the light emitting element can be reduced.

In one embodiment of the present invention, light emitting element 1 or light emitting element 2 comprises a side length greater than 30 mils. The semiconductor stack 10a may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102a and the active layer 103a, and one or more holes 100a are formed through the second semiconductor layer 102a and the active layer 103a, wherein the one or more holes 100a expose one or more second surfaces 1012a of the first semiconductor layer 101 a. When an external current is injected into the light emitting element 1 or the light emitting element 2, the light field distribution of the light emitting element 1 or the light emitting element 2 can be uniformized and the forward voltage of the light emitting element can be reduced by the distributed arrangement of the surrounding portion 111a and the plurality of hole portions 100a.

In an embodiment of the present invention, the light emitting element 1 or the light emitting element 2 includes a side length of less than 30mil, and the light emitting element 1 or the light emitting element 2 may not include one or more hole portions 100a.

In one embodiment of the present invention, the opening shape of the one or more hole portions 100a includes a circle, an ellipse, a rectangle, a polygon, or any shape. The plurality of hole portions 100a may be arranged in a plurality of rows, and the hole portions 100a in two adjacent rows may be aligned or offset from each other.

In one embodiment of the present invention, the substrate 11a may be a growth substrate including gallium arsenide (GaAs) wafer for growing AlGaInP (AlGaInP) or sapphire (Al) wafer for growing InGaN (InGaN) ₂ O ₃ ) Wafers, gallium nitride (GaN) wafers, or silicon carbide (SiC) wafers. The semiconductor stack 10a having photoelectric characteristics, such as a light-emitting (light-emitting) stack, may be formed on the substrate 11a by using Metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), hydride vapor deposition (HVPE), evaporation, or ion plating.

In an embodiment of the present invention, the first semiconductor layer 101a and the second semiconductor layer 102a are, for example, a cladding layer (cladding layer) or a confinement layer (confinement layer), both of which have different conductivity types, electrical properties, polarities, or may be doped with elements to provide electrons or holes, for example, the first semiconductor layer 101a is an n-type semiconductor, and the second semiconductor layer 102a is a p-type semiconductor. The active layer 103a is formed between the first semiconductor layer 101a and the second semiconductor layer 102a, and electrons and holes are recombined in the active layer 103a under a current drive to convert electric energy into light energy, so as to emit a light. The wavelength of light emitted by the light emitting element 1 or the light emitting element 2 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 10 a. The material of the semiconductor stack 10a comprises a III-V semiconductor material, such as Al _x In _y Ga _(1-x-y) N or Al _x In _y Ga _(1-x-y) P, wherein 0 is less than or equal to x and y is less than or equal to 1; (x+y) +.1. Depending on the material of the active layer 103a, red light with a wavelength between 610nm and 650nm and green light with a wavelength between 530nm and 570nm may be emitted when the semiconductor stack 10a is an AlInGaP-based material, blue light with a wavelength between 450nm and 490nm may be emitted when the semiconductor stack 10a is an InGaN-based material, or ultraviolet light with a wavelength between 400nm and 250nm may be emitted when the semiconductor stack 10a is an AlGaN-based material. The active layer 103a may be a single heterostructure (single heterostructure, SH), a double heterostructure (double heterostructure, DH), a double-sided double heterostructure (DDH), a multi-quantum well (MQW) structure. The material of the active layer 103a may be a semiconductor of neutral, p-type or n-type electrical properties.

As shown in the top view of fig. 2A and the cross-sectional view of fig. 2B along the line A-A' of fig. 2A, the method for manufacturing the light emitting device 1 or the light emitting device 2 includes a first insulating layer forming step. A first insulating layer 20a may be formed on the semiconductor structure 1000a by evaporation, deposition, or the like, and patterned by photolithography and etching to cover the first surface 1011a of the surrounding portion 111a and the second surface 1012a of the hole portion 100a, and to cover the second semiconductor layer 102a of the semiconductor structure 1000a, the second outer sidewall 1001a of the active layer 103a, and the inner sidewall 1002a, wherein the first insulating layer 20a includes a first insulating layer surrounding region 200a to cover the surrounding portion 111a, such that the first surface 1011a of the first semiconductor layer 101a located in the surrounding portion 111a is covered by the first insulating layer surrounding region 200 a; a first group of first insulating layer coverage areas 201a to cover the hole portion 100a, such that the second surface 1012a of the first semiconductor layer 101a located at the hole portion 100a is covered by the first group of first insulating layer coverage areas 201 a; and a second group of first insulating layer openings 202a exposing the surface 102s of the second semiconductor layer 102 a. The first insulating layer coverage areas 201a of the first group are separated from each other and correspond to the plurality of hole portions 100a, respectively. The first insulating layer 20a may be of a single-layer or multi-layer construction. When the first insulating layer 20a is a single-layer film, the first insulating layer 20a can protect the sidewalls of the semiconductor structure 1000a to prevent the active layer 103a from being damaged by the subsequent manufacturing process. When the first is When the insulating layer 20a is a multi-layered film, the first insulating layer 20a may include two or more materials having different refractive indices alternately stacked to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The first insulating layer 20a is made of a non-conductive material and includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy Resin (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), or an inorganic material such as silica gel (Silicone), glass (Glass), or a dielectric material such as alumina (Al) ₂ O ₃ ) Silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Titanium oxide (TiO) _x ) Or magnesium fluoride (MgF) _x )。

In one embodiment of the present invention, the first insulating layer forming step is continued, and as shown in the top view of fig. 3A and the cross-sectional view of fig. 3B along the line A-A' of fig. 3A, the manufacturing method of the light emitting device 1 or the light emitting device 2 includes a transparent conductive layer forming step. A transparent conductive layer 30a may be formed in the first insulating layer openings 202a of the second group by evaporation or deposition, wherein an outer edge 301a of the transparent conductive layer 30a is spaced apart from the first insulating layer 20a to expose a surface 102s of the second semiconductor layer 102 a. Since the transparent conductive layer 30a is formed on substantially the entire surface of the second semiconductor layer 102a and is in contact with the second semiconductor layer 102a, the transparent conductive layer 30a can uniformly spread a current over the entire second semiconductor layer 102 a. The material of the transparent conductive layer 30a includes a material transparent to light emitted from the active layer 103a, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In another embodiment of the present invention, after the mesa formation step, the transparent conductive layer formation step may be performed first, followed by the first insulating layer formation step.

In another embodiment of the present invention, after the mesa formation step, the first insulating layer formation step may be omitted, and the transparent conductive layer formation step may be directly performed.

In one embodiment of the present invention, the transparent conductive layer is formed by following the step of forming the transparent conductive layer, as shown in the top view of fig. 4A and the cross-sectional view of fig. 4B along the line A-A' of fig. 4A, and the method for manufacturing the light emitting device 1 or the light emitting device 2 includes a step of forming the reflective structure. The reflective structure includes a reflective layer 40a and/or a barrier layer 41a, which can be directly formed on the transparent conductive layer 30a by evaporation or deposition, wherein the reflective layer 40a is located between the transparent conductive layer 30a and the barrier layer 41 a. In a top view of the light emitting element 1 or the light emitting element 2, the outer edge 401a of the reflective layer 40a may be disposed inside, outside, or in overlapping alignment with the outer edge 301a of the transparent conductive layer 30a, and the outer edge 411a of the barrier layer 41a may be disposed inside, outside, or in overlapping alignment with the outer edge 401a of the reflective layer 40a, the outer edge 301a of the reflective layer 40 a.

In another embodiment of the present invention, the step of forming the transparent conductive layer may be omitted, and the step of forming the reflective structure is directly performed after the step of forming the mesa or the step of forming the first insulating layer, for example, the reflective layer 40a and/or the barrier layer 41a are directly formed on the second semiconductor layer 102a, and the reflective layer 40a is located between the second semiconductor layer 102a and the barrier layer 41 a.

The reflective layer 40a may be one or more layers of structure, such as a Bragg reflective structure. The material of the reflective layer 40a includes a metal material having a high reflectance, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy of the above materials. The term "high reflectance" as used herein means a reflectance of 80% or more with respect to the wavelength of light emitted from the light-emitting

element

1 or 2. In an embodiment of the present invention, the barrier layer 41a covers the reflective layer 40a to prevent the reflective layer 40a from being oxidized on the surface of the reflective layer 40a to deteriorate the reflectivity of the reflective layer 40 a. The material of the barrier layer 41a includes a metal material such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. The barrier layer 41a may be one or more layers, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In one embodiment of the present invention, the barrier layer 41a includes a titanium (Ti)/aluminum (Al) stack on a side away from the reflective layer 40a, and a titanium (Ti)/tungsten (W) stack on a side near the reflective layer 40 a. In an embodiment of the present invention, the material of the reflective layer 40a and the barrier layer 41a preferably comprises a metal material other than gold (Au) or copper (Cu).

In an embodiment of the invention, following the reflective structure forming step, as shown in the top view of fig. 5A, the cross-sectional view of fig. 5B along the line A-A 'of fig. 5A, and the cross-sectional view of fig. 5C along the line B-B' of fig. 5A, the method for manufacturing the light emitting device 1 or the light emitting device 2 includes a second insulating layer forming step. A second insulating layer 50a may be formed on the semiconductor structure 1000a by evaporation, deposition, or the like, and patterned by photolithography and etching to form a first group of second insulating layer openings 501a exposing the first semiconductor layer 101a, and a second group of second insulating layer openings 502a exposing the reflective layer 40a or the barrier layer 41a, wherein during the patterning of the second insulating layer 50a, the first insulating layer surrounding region 200a covering the surrounding portion 111a and the first insulating layer covering region 201a of the first group in the hole portion 100a are partially etched away to expose the first semiconductor layer 101a in the first insulating layer forming step; a first group of first insulating layer openings 203a are formed in the hole portion 100a to expose the first semiconductor layer 101a. In the present embodiment, in the cross-sectional view of the light emitting element 1 or the light emitting element 2, as shown in fig. 5B, the first group of second insulating layer openings 501a and the second group of second insulating layer openings 502a have different widths and numbers. The opening shapes of the first group of second insulating layer openings 501a and the second group of second insulating layer openings 502a include a circle, an ellipse, a rectangle, a polygon, or any shape. In this embodiment, as shown in fig. 5A, the second insulating layer openings 501a of the first group are separated from each other and arranged in a plurality of rows, and respectively correspond to the plurality of holes 100a and the first insulating layer openings 203a of the first group, the second insulating layer openings 502a of the second group are all close to one side of the substrate 11a, for example, the left side or the right side of the center line of the substrate 11a, and the second insulating layer openings 502a of the second group are separated from each other and are located between the second insulating layer openings 501a of the first group of two adjacent rows. The second insulating layer 50a may be of a single-layer or multi-layer construction. When the second insulating layer 50a is a single-layer film, the second insulating layer 50a may protect the sidewalls of the semiconductor structure 1000a from damage by subsequent fabrication processes. When the second insulating layer 50a is a multi-layered film, the second insulating layer 50a may include two or more materials having different refractive indices alternately stacked to form a bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The second insulating layer 50a is made of a non-conductive material and includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), or an inorganic material such as silica gel (Silicone), glass (Glass), or a dielectric material such as alumina (Al) ₂ O ₃ ) Silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Titanium oxide (TiO) _x ) Or magnesium fluoride (MgF) _x )。

Following the second insulating layer formation step, in an embodiment of the present invention, as shown in the top view of fig. 6A, the cross-sectional view of fig. 6B along line A-A 'of fig. 6A, and the cross-sectional view of fig. 6C along line B-B' of fig. 6A, the method for manufacturing the light emitting element 1 or the light emitting element 2 includes a contact layer formation step. A contact layer 60a may be formed on the first semiconductor layer 101a and the second semiconductor layer 102a by evaporation, deposition, or the like, and then patterned by photolithography and etching, and one or more contact layer openings 602a are formed on the second insulating layer openings 502a of the second group to expose the reflective layer 40a or the barrier layer 41a, and define an ejector pin region 600a at the geometric center of the light emitting device 1 or the light emitting device 2. In the cross-sectional view of the light emitting element 1 or the light emitting element 2, the contact layer opening 602a includes a width larger than the width of the second insulating layer opening 502a of any one of the second groups. In the upper view of the light emitting element 1 or the light emitting element 2, the plurality of contact layer openings 602a are all close to one side of the substrate 11a, for example, the left side or the right side of the center line of the substrate 11 a. The contact layer 60a may be one or more layers. In order to reduce the resistance of contact with the first semiconductor layer 101a, the material of the contact layer 60a includes a metal material such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. In an embodiment of the present invention, the material of the contact layer 60a preferably includes a metal material other than gold (Au) or copper (Cu). In an embodiment of the present invention, the material of the contact layer 60a preferably comprises a metal having high reflectivity, such as aluminum (Al), platinum (Pt). In an embodiment of the present invention, the side of the contact layer 60a in contact with the first semiconductor layer 101a preferably includes chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101 a.

In an embodiment of the present invention, the contact layer 60a covers all the hole portions 100a and extends to cover the second semiconductor layer 102a, wherein the contact layer 60a is insulated from the second semiconductor layer 102a by the second insulating layer 50a, and the contact layer 60a is in contact with the first semiconductor layer 101a through the hole portions 100 a. When an external current is injected into the light emitting element 1 or the light emitting element 2, the current is conducted to the first semiconductor layer 101a through the plurality of hole portions 100 a. In this embodiment, a first shortest distance is included between two adjacent holes 100a on the same row, and a second shortest distance is included between any hole 100a adjacent to the edge of the light emitting device and the first outer sidewall 1003a of the first semiconductor layer 101a, wherein the first shortest distance is greater than the second shortest distance.

In another embodiment of the present invention, the contact layer 60a covers the surrounding portion 111a and the hole portion 100a and extends to cover the second semiconductor layer 102a, wherein the contact layer 60a is insulated from the second semiconductor layer 102a by the second insulating layer 50a, and the contact layer 60a is contacted with the first semiconductor layer 101a by the surrounding portion 111a and the hole portion 100 a. When an external current is injected into the light emitting element 1 or the light emitting element 2, a part of the current is conducted to the first semiconductor layer 101a through the surrounding portion 111a, and another part of the current is conducted to the first semiconductor layer 101a through the plurality of hole portions 100 a. In this embodiment, a first shortest distance is included between two adjacent holes 100a on the same row, and a second shortest distance is included between any hole 100a adjacent to the edge of the light emitting device and the first outer sidewall 1003a of the first semiconductor layer 101a, wherein the first shortest distance is less than or equal to the second shortest distance.

In another embodiment of the present invention, the plurality of hole portions 100a may be arranged in a first row and a second row, wherein a first shortest distance is included between two adjacent hole portions 100a located in the same row, and a second shortest distance is included between the hole portions 100a located in the first row and the hole portions 100a located in the second row, wherein the first shortest distance is greater than or less than the second shortest distance.

In an embodiment of the present invention, the plurality of holes 100a may be arranged in a first row, a second row and a third row, a first shortest distance is included between the holes 100a located in the first row and the holes 100a located in the second row, and a second shortest distance is included between the holes 100a located in the second row and the holes 100a located in the third row, wherein the first shortest distance is smaller than the second shortest distance.

In an embodiment of the present invention, following the contact layer forming step shown in fig. 6A, 6B and 6C, the method for manufacturing the light emitting device 1 or the light emitting device 2 includes a third insulating layer forming step, as shown in the top view of fig. 7A, the cross-sectional view of fig. 7B along the line A-A 'of fig. 7A, and the cross-sectional view of fig. 7C along the line B-B' of fig. 7A, a third insulating layer 70a may be formed on the semiconductor structure 1000a by evaporation or deposition, and the like, and then patterned by photolithography and etching, wherein a first group of third insulating layer openings 701a is formed on the contact layer 60a to expose the contact layer 60a shown in fig. 6A, and a second group of third insulating layer openings 702a is formed on the one or more contact layer openings 602a to expose the reflective layer 40a or the barrier layer 41a shown in fig. 6A, wherein the contact layer 60a on the second semiconductor layer 102a is sandwiched between the second insulating layer 50a and the third insulating layer 70a, and the third group of third insulating layer openings 501a are not overlapped with the first group of openings 501 a. The thimble region 600a is surrounded and covered by the third insulating layer. In the present embodiment, as shown in fig. 7A, the third insulating layer openings 701a of the first group are separated from each other and are offset from the plurality of hole portions 100 a. The third insulating layer openings 702a of the second group are separated from each other and correspond to the plurality of contact layer openings 602a, respectively. In the top view of fig. 7A, a first group of third insulating layer openings 701a are adjacent to one side, e.g., the right side, of the substrate 11a, the first The third insulating layer openings 702a of the two groups are near the other side of the substrate 11a, for example, the left side of the center line of the substrate 11 a. In the cross-sectional view of the light emitting device 1 or the light emitting device 2, the third insulating layer opening 702a of any one of the second groups includes a width smaller than the width of any one of the contact layer openings 602a, and the third insulating layer 70a conforms to the contact layer opening 602a and fills the sidewalls of the cladding contact layer opening 602a to expose the reflective layer 40a or the barrier layer 41a, thereby forming the third insulating layer opening 702a of the second group. The third insulating layer 70a may be of a single-layer or multi-layer construction. When the third insulating layer 70a is a multi-layered film, the third insulating layer 70a may include two or more materials having different refractive indices alternately stacked to form a bragg reflector (DBR) structure to selectively reflect light of a specific wavelength. The third insulating layer 70a is made of a non-conductive material and contains an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy Resin (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), or an inorganic material such as silica gel (Silicone), glass (Glass), or a dielectric material such as alumina (Al) ₂ O ₃ ) Silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Titanium oxide (TiO) _x ) Or magnesium fluoride (MgF) _x )。

The manufacturing method of the light emitting device 1 or the light emitting device 2 includes a bonding pad forming step following the third insulating layer forming step. As shown in the top view of fig. 8, a first bonding pad 80a and a second bonding pad 90a may be formed on one or more semiconductor structures 1000a by electroplating, evaporation, deposition, or the like, and then patterned by photolithography and etching. In the top view of fig. 8, the first pads 80a are located near one side, e.g., the right side, of the centerline of the substrate 11a, and the second pads 90a are located near the other side, e.g., the left side, of the centerline of the substrate 11 a. The first pad 80a covers all of the third insulating layer openings 701a of the first group to be in contact with the contact layer 60a, and is electrically connected to the first semiconductor layer 101a through the contact layer 60a and the hole portion 100 a. The second bonding pad 90a covers all of the third insulating layer openings 702a of the second group, contacts the reflective layer 40a or the barrier layer 41a, and electrically connects to the second semiconductor layer 102a through the reflective layer 40a or the barrier layer 41 a. The first pad 80a has one or more first pad openings 800a; and a first side 802a and a plurality of first recesses 804a extend from the first side 802a in a direction away from the second bonding pad 90 a. The second bond pad 90a has one or more second bond pad openings 900a; and a second side 902a and a plurality of second recesses 904a extending from the second side 902a in a direction away from the first pads 80 a. The positions of the first pad opening 800a and the second pad opening 900a substantially correspond to the positions of the hole portion 100a, and the positions of the first recess 804a and the second recess 904a substantially correspond to the positions of the hole portion 100 a. In other words, the first and

second pads

80a and 90a do not cover any hole portion 100a, the first and

second pads

80a and 90a bypass the hole portion 100a and are formed around the hole portion 100a such that the first or

second pad openings

800a or 900a include a diameter larger than that of any hole portion 100a, and the first or

second recesses

804a or 904a include a width larger than that of any hole portion 100 a. In one embodiment of the present invention, the first plurality of recesses 804a are substantially aligned with the second plurality of recesses 904a in a top view. In another embodiment of the present invention, the plurality of first recesses 804a are offset from the plurality of second recesses 904a in a top view. In an embodiment of the present invention, the shape of the first pad 80a is the same as or different from the shape of the second pad 90a in the upper view of the light emitting element 1 or the light emitting element 2.

Fig. 9A is a cross-sectional view taken along line A-A 'of fig. 8, and fig. 9B is a cross-sectional view taken along line B-B' of fig. 8. The light emitting device 1 according to the present embodiment is a flip-chip light emitting diode device. The light emitting element 1 includes a substrate 11a; one or more semiconductor structures 1000a are located on the substrate 11a; the surrounding portion 111a surrounds one or more semiconductor structures 1000a; and the first pad 80a and the second pad 90a are located on the semiconductor stack 10 a. The one or more semiconductor structures 1000a each include a semiconductor stack 10a, the semiconductor stack 10a including a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a located between the first semiconductor layer 101a and the second semiconductor layer 102 a. The plurality of semiconductor structures 1000a are connected to each other through the first semiconductor layer 101 a. As shown in fig. 8, 9A and 9B, the second semiconductor layer 102a and the active layer 103a around the one or more semiconductor structures 1000a are removed to expose the first surface 1011a of the first semiconductor layer 101a, in other words, the surrounding portion 111a includes the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000 a.

The light emitting device 1 further includes one or more holes 100a penetrating the second semiconductor layer 102a and the active layer 103a to expose one or more second surfaces 1012a of the first semiconductor layer 101 a; and a contact layer 60a formed on the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a and contact the first semiconductor layer 101a to form an electrical connection, and formed on the one or more second surfaces 1012a of the first semiconductor layer 101a to cover the one or more holes 100a and contact the first semiconductor layer 101a to form an electrical connection. In the present embodiment, the contact layer 60a includes a total surface area larger than the total surface area of the active layer 103a, or the contact layer 60a includes a peripheral side longer than the peripheral side of the active layer 103a, in the upper view of the light emitting element 1.

In an embodiment of the present invention, the first pad 80a and/or the second pad 90a cover the plurality of semiconductor structures 1000a.

In one embodiment of the present invention, the first pad 80a has one or more first pad openings 800a and the second pad 90a has one or more second pad openings 900a. The formation positions of the first pad 80a and the second pad 90a are wound around the formation position of the hole portion 100a such that the formation positions of the first pad opening 800a and the second pad opening 900a overlap with the formation position of the hole portion 100 a.

In an embodiment of the invention, in a top view of the light emitting device 1, the shape of the first bonding pad 80a is the same as the shape of the second bonding pad 90a, for example, the shapes of the first bonding pad 80a and the second bonding pad 90a are comb-shaped, as shown in fig. 8, a radius of curvature of the first bonding pad opening 800a and a radius of curvature of the first concave portion 804a of the first bonding pad 80a are respectively larger than a radius of curvature of the hole portion 100a, so that the first bonding pad 80a is formed in a region other than the positions of the plurality of hole portions 100 a. A radius of curvature of the second pad opening 900a and a radius of curvature of the second recess 904a of the second pad 90a are respectively larger than a radius of curvature of the hole 100a, so that the second pad 90a is formed in an area other than the positions of the plurality of holes 100 a.

In an embodiment of the present invention, in a top view of the light emitting device 1, the shape of the first pad 80a is different from the shape of the second pad 90a, for example, when the shape of the first pad 80a is rectangular and the shape of the second pad 90a is comb-shaped, the first pad 80a includes the first pad opening 800a such that the first pad 80a is formed in a region other than the plurality of holes 100a, and the second pad 90a includes the second recess 904a or includes both the second recess 904a and the second pad opening 900a such that the second pad 90a is formed in a region other than the plurality of holes 100 a.

In an embodiment of the present invention, the size of the first bonding pad 80a is different from the size of the second bonding pad 90a, for example, the area of the first bonding pad 80a is larger than the area of the second bonding pad 90 a. The first pad 80a and the second pad 90a may be one or more layers of structures including metal materials. The material of the first pad 80a and the second pad 90a includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy thereof. When the first bonding pad 80a and the second bonding pad 90a are of a multi-layer structure, the first bonding pad 80a includes a first upper bonding pad 805a and a first lower bonding pad 807a, and the second bonding pad 90a includes a second upper bonding pad 905a and a second lower bonding pad 907a. The upper layer bonding pad and the lower layer bonding pad have different functions respectively. The function of the upper layer bonding pad is mainly used for welding and forming a lead. The light emitting element 1 can be mounted on the package substrate in a flip chip form by upper layer pads using a solder or AuSn eutectic bonding. Specific metal materials of the upper layer pad include high ductility materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os). The upper layer bonding pad can be a single layer, an alloy or a multi-layer film of the materials. In one embodiment of the present invention, the material of the upper layer pad preferably comprises nickel (Ni) and/or gold (Au), and the upper layer pad is a single layer or multiple layers. The function of the lower bonding pad is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, to increase the interface bonding strength of the first lower bonding pad 807a with the contact layer 60a or to increase the interface bonding strength of the second lower bonding pad 907a with the reflective layer 40a or the barrier layer 41 a. Another function of the underlying bond pad is to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure, destroying the reflectivity of the reflective structure. Accordingly, the lower layer pad preferably contains a metal material other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), and the lower layer pad may be a single layer, an alloy, or a multilayer film of the above materials. In one embodiment of the present invention, the lower bonding pad preferably comprises a multilayer film of titanium (Ti), aluminum (Al), or a multilayer film of chromium (Cr), aluminum (Al).

In an embodiment of the present invention, a portion of the contact layer 60a connected to the first semiconductor layer 101a is located under the second pad 90a in a cross-sectional view of the light emitting element 1.

In an embodiment of the present invention, in the cross-sectional view of the light emitting device 1, a portion of the contact layer 60a connected to the first semiconductor layer 101a is located above the reflective layer 40a and/or the barrier layer 41 a.

In an embodiment of the present invention, in a top view of the light emitting element 1, the hole portion 100a includes a maximum width smaller than a maximum width of the first bonding pad opening 800 a; and/or the hole portion 100a includes a maximum width smaller than a maximum width of the second pad opening 900 a.

In an embodiment of the invention, the hole portions 100a are respectively located in the first concave portions 804a of the first pad 80a and the second concave portions 904a of the second pad 90a in the top view of the light emitting element 1.

Fig. 10 is a cross-sectional view of a light-emitting element 2 disclosed in an embodiment of the present invention. The light emitting element 2 is similar to the light emitting element 1 in the above embodiment, and the light emitting element 2 further includes a first buffer pad 810a and a second buffer pad 910a respectively located under the first bonding pad 80a and the second bonding pad 90a, and the light emitting element 2 and the light emitting element 1 have substantially the same structure, so the light emitting element 2 in fig. 10 and the light emitting element 1 in fig. 9A to 9B have the same name and the same number, are represented by the same structure, have the same material, or have the same function, and will not be described herein again. In this embodiment, the light emitting device 2 includes a first buffer pad 810a located between the first pad 80a and the semiconductor stack 10a, and a second buffer pad 910a located between the second pad 90a and the semiconductor stack 10a, wherein the first buffer pad 810a and the second buffer pad 910a cover part or all of the hole portion 100a; in this embodiment, since the

bonding pads

80a, 90a and the semiconductor stack 10a include multiple insulating layers therebetween, the

bonding pads

80a, 90a of the light emitting device 2 are cracked by the stress generated when the

bonding pads

80a, 90a are bonded with a solder or AuSn eutectic, so that the

pads

810a, 910a are respectively located between the

bonding pads

80a, 90a and the third insulating layer 70a, the first and

second pads

810a, 910a cover all the holes 100a, the forming positions of the first and

second bonding pads

80a, 90a are the forming positions around the holes 100a, and the stress generated between the bonding pads and the insulating layers is reduced by selecting the material of the pads and reducing the thickness. In other words, the first pad 80a and the second pad 90a do not cover the hole portion 100a.

In an embodiment of the present invention, as shown in fig. 10, in the top view of the light emitting element 2, the shapes of the

buffer pads

810a,910a are the same as the shapes of the

bonding pads

80a,90a, respectively, for example, the shapes of the first buffer pad 810a and the first bonding pad 80a are comb-shaped.

In an embodiment of the present invention, the shape of the

pads

810a,910a is different from the shape of the

pads

80a,90a, respectively, in a top view (not shown) of the light emitting element 2, for example, the shape of the first pad 810a is rectangular, and the shape of the first pad 80a is comb-shaped.

In another embodiment of the present invention, the size of the

cushioning pads

810a,910a is different from the size of the

bonding pads

80a,90a, respectively, e.g., the area of the first cushioning pad 810a is larger than the area of the first bonding pad 80a and the area of the second cushioning pad 910a is larger than the area of the second bonding pad 90 a.

In another embodiment of the present invention, a distance between the first pad 80a and the second pad 90a is greater than a distance between the first buffer pad 810a and the second buffer pad 910 a.

In another embodiment of the present invention, the

buffer pads

810a,910a have a larger area than the

bonding pads

80a,90a to release the pressure of the

bonding pads

80a,90a during die bonding. In the cross-sectional view of the light emitting element 2, the first buffer pad 810a includes a width 1.5 to 2.5 times, preferably 2 times, the width of the first pad 80 a.

In another embodiment of the present invention, the

buffer pads

810a,910a have a larger area than the

bonding pads

80a,90a to release the pressure of the

bonding pads

80a,90a during die bonding. In the cross-sectional view of the light emitting element 2, the first cushion 810a spreads over a distance of 1 or more times its thickness, preferably 2 or more times its thickness.

In another embodiment of the present invention, the

pads

80a,90a have a thickness of between 1 and 100 μm, preferably between 2 and 6 μm, and the

pads

810a,910a have a thickness of greater than 0.5 μm to release the pressure of the

pads

80a,90a during die bonding.

In another embodiment of the present invention, the first cushion 810a and the second cushion 910a may be one or more layers of structures comprising metal materials. The function of the first and

second cushions

810a and 910a forms a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, e.g., the first cushion 810a contacts the contact layer 60a and the second cushion 910a contacts the reflective layer 40a or the barrier layer 41 a. The

buffer pads

810a,910a preferably contain a metallic material other than gold (Au), copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os) to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the light emitting element.

In another embodiment of the present invention, the first buffer pad 810a and/or the second buffer pad 910a are/is a multi-layer structure comprising a metal material, wherein the multi-layer structure comprises a high ductility layer and a low ductility layer to prevent the stress generated when the

bonding pads

80a, 90a are bonded with the holder solder or AuSn eutectic from cracking the insulating layer between the

bonding pads

80a, 90a and the semiconductor stack 10 a. The high-ductility layer and the low-ductility layer comprise metals having different Young's modulus.

In another embodiment of the present invention, the high ductility layer of the first and

second cushioning pads

810a and 910a comprises a thickness greater than or equal to a thickness of the low ductility layer.

In another embodiment of the present invention, the first buffer pad 810a and the second buffer pad 910a are of a multi-layered structure comprising metal materials, and when the first pad 80a and the second pad 90a are of a multi-layered structure comprising metal materials, the surface of the first buffer pad 810a contacting the first pad 80a comprises the same metal material, and the surface of the second buffer pad 910a contacting the second pad 90a comprises the same metal material, such as chromium (Cr), nickel (Ni), titanium (Ti), platinum (Pt), to improve the interface bonding strength between the pads.

As shown in fig. 11A and 11B, a fourth insulating layer 110a may be formed on the first buffer pad 810a and the second buffer pad 910a by evaporation, deposition, or the like, and then patterned by photolithography and etching, and the first pad 80a and the second pad 90a are formed on the first buffer pad 810a and the second buffer pad 910a, respectively, wherein the fourth insulating layer 110a surrounds the sidewalls of the first buffer pad 810a and the second buffer pad 910 a. The fourth insulating layer 110a may have a single-layer or multi-layer structure. When the fourth insulating layer 110a is a multi-layered film, the fourth insulating layer 110a may include two or more materials having different refractive indices alternately stacked to form a bragg reflector (DBR) structure to selectively reflect light of a specific wavelength. The material of the fourth insulating layer 110a is made of a non-conductive material, and includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (polyimide), fluorocarbon polymer (Fluorocarbon Polymer), or an inorganic material such as silica gel (Silicone), glass (Glass), or a dielectric material such as alumina (Al) ₂ O ₃ ) Silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Titanium oxide (TiO) _x ) Or magnesium fluoride (MgF) _x )。

In an embodiment of the present invention, the manufacturing process of the first pad 80a and the second pad 90a may be directly subsequent to the manufacturing process of the first cushion 810a and the second cushion 910 a. In another embodiment of the present invention, after the manufacturing process of the first buffer pad 810a and the second buffer pad 910a, the forming step of the fourth insulating layer 110a is performed, and then the manufacturing process of the first pad 80a and the second pad 90a is continued.

Fig. 12A to 22 illustrate a method for manufacturing a light emitting element 3 or a light emitting element 4 according to an embodiment of the present invention.

As shown in the top view of fig. 12A and the cross-sectional view of fig. 12B along line A-A' of fig. 12A, the method for manufacturing the light emitting element 3 or 4 includes a mesa formation step including providing a substrate 11B; and forming a semiconductor stack 10b on the substrate 11b, wherein the semiconductor stack 10b includes a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b disposed between the first semiconductor layer 101b and the second semiconductor layer 102 b. The semiconductor stack 10b may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102b and the active layer 103b, thereby forming one or more semiconductor structures 1000b; and a surrounding portion 111b surrounds one or more of the semiconductor structures 1000b. The surrounding portion 111b exposes a first surface 1011b of the first semiconductor layer 101 b. The one or more semiconductor structures 1000b each include a plurality of first outer sidewalls 1003b, a second outer sidewall 1001b, and a plurality of inner sidewalls 1002b, wherein the first outer sidewalls 1003b are sidewalls of the first semiconductor layer 101b, the second outer sidewalls 1001b are sidewalls of the active layer 103b and/or the second semiconductor layer 102b, one end of the second outer sidewalls 1001b is connected to a surface 102s of the second semiconductor layer 102b, and the other end of the second outer sidewalls 1001b is connected to the first surface 1011b of the first semiconductor layer 101 b; one end of the inner sidewall 1002b is connected to the surface 102s of the second semiconductor layer 102b, and the other end of the inner sidewall 1002b is connected to the second surface 1012b of the first semiconductor layer 101 b; the plurality of semiconductor structures 1000b are connected to each other through the first semiconductor layer 101 b. As seen in fig. 12B, the inner sidewall 1002B of the semiconductor structure 1000B has an obtuse angle with the second surface 1012B of the first semiconductor layer 101B, the first outer sidewall 1003B of the semiconductor structure 1000B has an obtuse angle or a straight angle with the surface 11s of the substrate 11B, and the second outer sidewall 1001B of the semiconductor structure 1000B has an obtuse angle with the first surface 1011B of the first semiconductor layer 101B. The surrounding portion 111b surrounds the semiconductor structure 1000b, and the surrounding portion 111b has a rectangular shape or a polygonal shape in a top view of the light emitting element 3 or the light emitting element 4.

In one embodiment of the present invention, the light emitting element 3 or the light emitting element 4 comprises a side length of less than 30mil. When an external current is injected into the light emitting element 3 or the light emitting element 4, the surrounding portion 111b surrounds the semiconductor structure 1000b, so that the light field distribution of the light emitting element 3 or the light emitting element 4 can be homogenized, and the forward voltage of the light emitting element can be reduced.

In one embodiment of the present invention, light emitting element 3 or light emitting element 4 comprises a side length greater than 30 mils. The semiconductor stack 10b may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102b and the active layer 103b, and one or more holes 100b are formed through the second semiconductor layer 102b and the active layer 103b, wherein the one or more holes 100b expose one or more second surfaces 1012b of the first semiconductor layer 101 b. When an external current is injected into the light emitting element 3 or the light emitting element 4, the light field distribution of the light emitting element 3 or the light emitting element 4 can be made uniform and the forward voltage of the light emitting element can be reduced by the distributed arrangement of the surrounding portion 111b and the plurality of hole portions 100 b.

In one embodiment of the present invention, the opening shape of the one or more hole portions 100b includes a circle, an ellipse, a rectangle, a polygon, or any shape. The plurality of hole portions 100b may be arranged in a plurality of rows, and the hole portions 100b in adjacent rows may be aligned or offset from each other.

In one embodiment of the present invention, the substrate 11b may be a growth substrate including gallium arsenide (GaAs) wafer for growing AlGaInP (AlGaInP) or sapphire (Al) wafer for growing InGaN (InGaN) ₂ O ₃ ) Wafers, gallium nitride (GaN) wafers, or silicon carbide (SiC) wafers. The organic metal chemical gas can be used on the substrate 11bThe semiconductor stack 10b having photoelectric characteristics, such as a light-emitting (light-emitting) stack, is formed by a phase deposition Method (MOCVD), a Molecular Beam Epitaxy (MBE), a hydride vapor deposition method (HVPE), an evaporation method, or an ion plating method.

In an embodiment of the present invention, the first semiconductor layer 101b and the second semiconductor layer 102b are, for example, a cladding layer (cladding layer) or a confinement layer (confinement layer), both of which have different conductivity types, electrical properties, polarities, or may be doped with elements to provide electrons or holes, for example, the first semiconductor layer 101b is an n-type electrical semiconductor, and the second semiconductor layer 102b is a p-type electrical semiconductor. The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b, and electrons and holes are recombined in the active layer 103b under a current drive to convert electric energy into light energy, thereby emitting a light. The wavelength of light emitted by the light emitting element 3 or the light emitting element 4 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 10 b. The material of the semiconductor stack 10b comprises a III-V semiconductor material, such as Al _x In _y Ga _(1-x-y) N or Al _x In _y Ga _(1-x-y) P, wherein 0 is less than or equal to x and y is less than or equal to 1; (x+y) +.1. Depending on the material of the active layer 103b, red light with a wavelength between 610nm and 650nm and green light with a wavelength between 530nm and 570nm may be emitted when the semiconductor stack 10b material is an AlInGaP-based material, blue light with a wavelength between 450nm and 490nm may be emitted when the semiconductor stack 10b material is an InGaN-based material, or ultraviolet light with a wavelength between 400nm and 250nm may be emitted when the semiconductor stack 10b material is an AlGaN-based material. The active layer 103b may be a single heterostructure (single heterostructure, SH), a double heterostructure (double heterostructure, DH), a double-sided double heterostructure (DDH), a multi-quantum well (MQW) structure. The material of the active layer 103b may be a neutral, p-type or n-type electrical semiconductor.

As shown in the top view of fig. 13A and the cross-sectional view of fig. 13B along line A-A' of fig. 13A, the method for manufacturing the light emitting element 3 or 4 includes a first insulating layer forming step. A first insulating layer20b may be formed on the semiconductor structure 1000b by evaporation or deposition, and then patterned by photolithography and etching to cover the first surface 1011b of the surrounding portion 111b and the second surface 1012b of the hole portion 100b, and to cover the second semiconductor layer 102b of the semiconductor structure 1000b, the second outer sidewall 1001b of the active layer 103b, and the inner sidewall 1002b, wherein the first insulating layer 20b includes a first insulating layer surrounding region 200b to cover the surrounding portion 111b, such that the first surface 1011b of the first semiconductor layer 101b located in the surrounding portion 111b is covered by the first insulating layer surrounding region 200 b; a first group of first insulating layer coverage areas 201b to cover the hole portions 100b such that the second surfaces 1012b of the first semiconductor layers 101b located in the hole portions 100b are covered by the first group of first insulating layer coverage areas 201 b; and a second group of first insulating layer openings 202b exposing the surface 102s of the second semiconductor layer 102 b. The first insulating layer coverage areas 201b of the first group are separated from each other and correspond to the plurality of hole portions 100b, respectively. The first insulating layer 20b may be of a single-layer or multi-layer construction. When the first insulating layer 20b is a single-layer film, the first insulating layer 20b can protect the sidewalls of the semiconductor structure 1000b from being damaged by the subsequent manufacturing process. When the first insulating layer 20b is a multi-layered film, the first insulating layer 20b may include two or more materials having different refractive indices alternately stacked to form a Bragg reflector (DBR) structure, selectively reflecting light of a specific wavelength. The first insulating layer 20b is made of a non-conductive material and includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy Resin (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), or an inorganic material such as silica gel (Silicone), glass (Glass), or a dielectric material such as alumina (Al) ₂ O ₃ ) Silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Titanium oxide (TiO) _x ) Or magnesium fluoride (MgF) _x )。

In one embodiment of the present invention, the first insulating layer forming step is continued, and as shown in the top view of fig. 14A and the cross-sectional view of fig. 14B along the line A-A' of fig. 14A, the manufacturing method of the light emitting element 3 or the light emitting element 4 includes a transparent conductive layer forming step. A transparent conductive layer 30b may be formed on the semiconductor structure 1000b by evaporation or deposition, and is in contact with the second semiconductor layer 102, where the transparent conductive layer 30b does not cover the hole portion 100b. The transparent conductive layer 30b is formed on substantially the entire surface of the second semiconductor layer 102b in a top view of the light emitting element 3 or the light emitting element 4. Specifically, the transparent conductive layer 30b may be formed in the first insulating layer openings 202b of the second group by evaporation or deposition, wherein the outer edge 301b of the transparent conductive layer 30b is spaced apart from the first insulating layer 20b to expose the surface 102s of the second semiconductor layer 102 b. The transparent conductive layer 30b includes one or more transparent conductive layer openings 300b corresponding to one or more holes 100b and/or corresponding to the first insulating layer coverage areas 201b of the first group, respectively, wherein an outer edge 301b of the transparent conductive layer opening 300b is spaced apart from an inner sidewall 1002b of the semiconductor structure 1000b and/or an outer edge of the hole 100b, and the outer edge of the transparent conductive layer opening 300b surrounds the outer edge of the hole 100b or surrounds the first insulating layer coverage areas 201b of the first group. The material of the transparent conductive layer 30b includes a material transparent to light emitted from the active layer 103b, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In one embodiment of the present invention, the transparent conductive layer is formed by following the step of forming the transparent conductive layer, and as shown in the top view of fig. 15A and the cross-sectional view of fig. 15B along the line A-A' of fig. 15A, the method for manufacturing the light emitting device 3 or the light emitting device 4 includes a step of forming the reflective structure. The reflective structure includes a reflective layer 40b and/or a barrier layer 41b, which can be directly formed on the transparent conductive layer 30b by evaporation or deposition, wherein the reflective layer 40b is located between the transparent conductive layer 30b and the barrier layer 41 b. In a top view of the light emitting element 3 or the light emitting element 4, the reflective layer 40b and/or the barrier layer 41b is formed over substantially the entire surface of the second semiconductor layer 102 b. The outer edge 401b of the reflective layer 40b can be disposed inside, outside, or in overlapping alignment with the outer edge 301b of the transparent conductive layer 30b, and the outer edge 411b of the barrier layer 41b can be disposed inside, outside, or in overlapping alignment with the outer edge 401b of the reflective layer 40b, the outer edge 301b of the reflective layer 40 b. The reflective layer 40b includes one or more reflective layer openings 400b corresponding to the one or more apertures 100b, respectively, and the barrier layer 41b includes one or more barrier layer openings 410b corresponding to the one or more apertures 100b, respectively. Transparent conductive layer opening 300b, reflective layer opening 400b, and barrier layer opening 410b overlap each other. The outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b is spaced apart from the outer edge of the hole portion 100b, and the outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b surrounds the outer edge of the hole portion 100b.

In another embodiment of the present invention, the transparent conductive layer forming step may be omitted, and the reflective structure forming step is directly performed after the mesa forming step or the first insulating layer forming step, for example, the reflective layer 40b and/or the barrier layer 41b are directly formed on the second semiconductor layer 102b, and the reflective layer 40b is located between the second semiconductor layer 102b and the barrier layer 41 b. The reflective layer 40b may be one or more layers of structure, such as a Bragg reflective structure. The material of the reflective layer 40b includes a metal material having a high reflectance, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy of the above materials. The term "high reflectance" as used herein means a reflectance of 80% or more with respect to the wavelength of light emitted from the light emitting element 3. In an embodiment of the present invention, the barrier layer 41b wraps the reflective layer 40b to prevent the reflective layer 40b from being oxidized on the surface of the reflective layer 40b to deteriorate the reflectivity of the reflective layer 40 b. The material of the barrier layer 41b includes a metal material such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. The barrier layer 41b may be one or more layers, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In one embodiment of the present invention, the barrier layer 41b includes a titanium (Ti)/aluminum (Al) stack on a side near the reflective layer 40b, and a titanium (Ti)/tungsten (W) stack on a side far from the reflective layer 40 b. In an embodiment of the present invention, the material of the reflective layer 40b and the barrier layer 41b preferably comprises a metal material other than gold (Au) or copper (Cu).

In one embodiment of the present invention, the following reflective structure forming step, as shown in the top view of fig. 16A and the cross-sectional view of fig. 16B along the line A-A' of fig. 16A, is performed in a method for manufacturing the light emitting device 3 or the light emitting device 4, which includes a second insulating layer forming step. A second insulating layer 50b may be formed on the semiconductor stack 10b by evaporation or deposition, and then patterned by photolithography and etching to form a first group of second insulating layer openings 501b exposing the first semiconductor layer 101b and a second group of second insulating layer openings 502b exposing the reflective layer 40b or the barrier layer 41b, wherein during the patterning of the second insulating layer 50b, the first insulating layer surrounding region 200b covering the surrounding portion 111b and the first group of first insulating layer covering regions 201b covering the hole portion 100b are etched and removed to expose the first semiconductor layer 101b, and the first group of first insulating layer openings 203b are formed on the hole portion 100b to expose the first semiconductor layer 101b. In an embodiment of the present invention, as shown in fig. 16A, the second insulating layer openings 501b of the first group are separated from each other and respectively correspond to the plurality of holes 100b, and the second insulating layer openings 502b of the second group are all near one side of the substrate 11b, for example, the left side or the right side of the center line of the substrate 11b, in an embodiment, the number of the second insulating layer openings 502b of the second group includes one or more, in this embodiment, the second insulating layer openings 502b of the second group are connected to each other to form a ring-shaped opening 5020b together, and the ring-shaped opening 5020b can be comb-shaped, rectangular, elliptic, circular, or polygonal in the upper view of the light emitting element 3. In an embodiment of the present invention, the second insulating layer 50b may be a single-layer or multi-layer structure. When the second insulating layer 50b is a multi-layered film, the second insulating layer 50b may include two or more materials having different refractive indices alternately stacked to form a Bragg reflector (DBR) structure, selectively reflecting light of a specific wavelength. The second insulating layer 50b is made of a non-conductive material and comprises an organic material Such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy Resin (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), or inorganic materials such as silica gel (Silicone), glass (Glass), or dielectric materials such as alumina (Al) ₂ O ₃ ) Silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Titanium oxide (TiO) _x ) Or magnesium fluoride (MgF) _x )。

Following the second insulating layer formation step, in an embodiment of the present invention, as shown in the top view of fig. 17A and the cross-sectional view of fig. 17B, the method for manufacturing the light emitting element 3 or the light emitting element 4 includes a contact layer formation step. A contact layer 60b may be deposited on the semiconductor stack 10b by evaporation or deposition, and patterned by photolithography or etching to form a first contact layer 601b and a second contact layer 602b. The first contact layer 601b covers all the first group of second insulating layer openings 501b, fills in one or more holes 100b to contact the first semiconductor layer 101b, and extends to cover the second insulating layer 50b and the second semiconductor layer 102b, wherein the first contact layer 601b is insulated from the second semiconductor layer 102b by the second insulating layer 50 b. The second contact layer 602b is formed in the annular opening 5020b of the second insulating layer 50b to contact the reflective layer 40b and/or the barrier layer 41b, wherein the sidewall 6021b of the second contact layer 602b is spaced apart from the sidewall 5021b of the annular opening 5020 b. The sidewall 6011b of the first contact layer 601b is spaced apart from the sidewall 6021b of the second contact layer 602b by a distance such that the first contact layer 60b is not connected to the second contact layer 602b, and the first contact layer 601b is electrically isolated from the second contact layer 602b by a portion of the second insulating layer 50 b. In the upper view, the first contact layer 601b covers the surrounding portion 111b of the semiconductor stack 10b, so that the first contact layer 601b surrounds the second contact layer 602b. In the top view of fig. 17A, the second contact layer 602b is near one side of the substrate 11b, for example, the left or right side of the center line of the substrate 11 b. Contact layer 60b defines a pin region 600b at the geometric center on semiconductor stack 10 b. The thimble region 600b is not connected to the first contact layer 601b and the second contact layer 602b, and is electrically isolated from each other, and the thimble region 600b comprises the same material as the first contact layer 601b and/or the second contact layer 602b. The thimble region 600b serves as a structure for protecting the epitaxial layer from damage by the probe during subsequent fabrication processes, such as die separation, die testing, and packaging. The contact layer 60b may be one or more layers. In order to reduce the resistance of contact with the first semiconductor layer 101b, the material of the contact layer 60b includes a metal material such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. In an embodiment of the present invention, the material of the contact layer 60b preferably includes a metal material other than gold (Au) or copper (Cu). In an embodiment of the present invention, the material of the contact layer 60b preferably comprises a metal having high reflectivity, such as aluminum (Al), platinum (Pt). In an embodiment of the present invention, the side of the contact layer 60b in contact with the first semiconductor layer 101b preferably includes chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101 b.

In an embodiment of the present invention, following the contact layer forming step shown in fig. 17A and 17B, the manufacturing method of the light emitting device 3 or the light emitting device 4 includes a third insulating layer forming step, as shown in the top view of fig. 18A and the cross-sectional view of fig. 18B along the line A-A' of fig. 18A, a third insulating layer 70B may be formed on the semiconductor stack 10B by evaporation or deposition, and the like, and then patterned by photolithography and etching, forming a third insulating layer opening 701B on the first contact layer 601B to expose the first contact layer 601B shown in fig. 17A, and forming another third insulating layer opening 702B on the second contact layer 602B to expose the second contact layer 602B shown in fig. 17A, wherein the first contact layer 601B partially located on the second semiconductor layer 102B is sandwiched between the second insulating layer 50B and the third insulating layer 70B. In this embodiment, as shown in fig. 18A, the third insulating layer opening 701b and another third insulating layer opening 702b bypass one or more hole portions 100b. In this embodiment, the third insulating layer opening 701b and/or the other third insulating layer opening 702b is an annular opening, which can be seen in a top viewIs comb-shaped, rectangular, elliptic, circular, or polygonal. In the top view of fig. 18A, a third insulating layer opening 701b is near one side, e.g., the right side, of the center line of the substrate 11b, and another third insulating layer opening 702b is near the other side, e.g., the left side, of the center line of the substrate 11 b. In the cross-sectional view, the third insulating layer opening 701b includes a width larger than that of the other third insulating layer opening 702 b. The third insulating layer 70b may be of a single-layer or multi-layer construction. When the third insulating layer 70b is a multi-layered film, the third insulating layer 70b may include two or more materials having different refractive indices alternately stacked to form a Bragg reflector (DBR) structure, selectively reflecting light of a specific wavelength. The third insulating layer 70b is made of a non-conductive material and contains an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy Resin (Epoxy), acrylic Resin (Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), or an inorganic material such as silica gel (Silicone), glass (Glass), or a dielectric material such as alumina (Al) ₂ O ₃ ) Silicon nitride (SiN) _x ) Silicon oxide (SiO) _x ) Titanium oxide (TiO) _x ) Or magnesium fluoride (MgF) _x )。

The third insulating layer forming step is followed, and the manufacturing method of the light emitting element 3 or the light emitting element 4 includes a bonding pad forming step. As shown in the top view of fig. 19, a first bonding pad 80b and a second bonding pad 90b may be formed on the semiconductor stack 10b by electroplating, evaporation, deposition, or the like, and then patterned by photolithography and etching. In the top view of fig. 19, the first pads 80b are located near one side, e.g., the right side, of the centerline of the substrate 11b, and the second pads 90b are located near the other side, e.g., the left side, of the centerline of the substrate 11 b. The first pad 80b contacts the first contact layer 601b through the third insulating layer opening 701b and forms an electrical connection with the first semiconductor layer 101b through the first contact layer 601 b. The second bonding pad 90b contacts the reflective layer 40b and/or the barrier layer 41b through another third insulating layer opening 702b, and forms an electrical connection with the second semiconductor layer 102b through the reflective layer 40b and/or the barrier layer 41 b. The first pad 80b has a plurality of first protrusions 801b and a plurality of first recesses 802b alternately connected to each other. The second pad 90b has a plurality of second convex portions 901b and a plurality of second concave portions 902b alternately connected to each other. The positions of the first concave portions 802b of the first pads 80b and the positions of the second concave portions 902b of the second pads 90b substantially correspond to the positions of the hole portions 100 b. In other words, the first and

second pads

801b and 802b do not cover any hole portion 100b, and the first recess 802b of the first pad 80b and the second recess 902b of the second pad 90b are formed around the hole portion 100b and around the hole portion 100b such that the width of the first recess 802b of the first pad 80b or the width of the second recess 902b of the second pad 90b is larger than the diameter of any hole portion 100 b. In one embodiment of the present invention, the first plurality of recesses 802b are substantially aligned with the second plurality of recesses 902b in a top view. In another embodiment of the present invention, the plurality of first recesses 802b are offset from the plurality of second recesses 902b in a top view.

In an embodiment of the present invention, as shown in fig. 19, the first bonding pad 80b covers the third insulating layer opening 701b, and the second bonding pad 90b covers the other third insulating layer opening 702b, and the third insulating layer opening 701b has a maximum width larger than that of the other third insulating layer opening 702b, so that the first bonding pad 80b has a maximum width larger than that of the second bonding pad 90 b. The first bonding pad 80b and the second bonding pad 90b with different sizes can facilitate the identification of the electrical property of the corresponding connection of the bonding pads during package bonding, thereby avoiding the occurrence of bonding to the wrong electrical bonding pad.

In an embodiment of the invention, the third insulating layer opening 701b includes an area larger or smaller than an area of the first pad 80b in a top view of the light emitting device.

In another embodiment of the present invention, the shortest distance between the first convex portion 801b and the second convex portion 901b is smaller than the greatest distance between the first concave portion 802b and the second concave portion 902 b.

In another embodiment of the present invention, the first pad 80b includes a first flat edge 803b opposite to the first convex portion 801b and the first concave portion 802b, and the second pad 90b includes a second flat edge 903b opposite to the second convex portion 901b and the second concave portion 902 b. The first flat edge 803b of the first pad 80b includes a maximum distance between the first protrusion 801b and the first flat edge, which is greater than a minimum distance between the first protrusion 801b and the second protrusion 901 b. The second land 903b of the second pad 90b includes a maximum distance between the second protrusion 901b that is greater than a minimum distance between the first protrusion 801b and the second protrusion 901 b.

In another embodiment of the present invention, one of the plurality of first concave portions 802b of the first pad 80b includes a radius of curvature different from a radius of curvature included in one of the plurality of first convex portions 801b of the first pad 80b, for example, one of the plurality of first concave portions 802b of the first pad 80b includes a radius of curvature greater than or less than a radius of curvature included in one of the plurality of first convex portions 801b of the first pad 80 b. In another embodiment of the present invention, one of the plurality of second concave portions 902b of the second pad 90b comprises a radius of curvature greater than or less than a radius of curvature comprised by one of the plurality of second convex portions 901b of the second pad 90 b.

In another embodiment of the present invention, a radius of curvature of one of the plurality of first protrusions 801b of the first pad 80b is greater than or less than a radius of curvature of one of the plurality of second protrusions 901b of the second pad 90 b.

In another embodiment of the present invention, the plurality of first concave portions 802b of the first bonding pad 80b are opposite to the plurality of second concave portions 902b of the second bonding pad 90b, and one of the plurality of first concave portions 802b comprises a radius of curvature greater than or less than a radius of curvature comprised by one of the plurality of second concave portions 902 b.

In another embodiment of the present invention, the shape of the first bonding pad 80b is different from the shape of the second bonding pad 90b, for example, the shape of the first bonding pad 80b is rectangular, and the shape of the second bonding pad 90b is comb-shaped.

In another embodiment of the present invention, the size of the first bonding pad 80b is different from the size of the second bonding pad 90b, for example, the area of the first bonding pad 80b is larger than the area of the second bonding pad 90 b.

Fig. 20 is a cross-sectional view taken along A-A' of fig. 19. The light emitting device 3 according to the present embodiment is a flip-chip light emitting diode device. The light emitting element 3 includes a substrate 11b; one or more semiconductor structures 1000b are disposed on the substrate 11b, wherein the semiconductor structures 1000b comprise a semiconductor stack 10, the semiconductor stack 101l comprises a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b disposed between the first semiconductor layer 101b and the second semiconductor layer 102b, the plurality of semiconductor structures 1000b being connected to each other by the first semiconductor layer 101 b; a surrounding portion 111b surrounds the one or more semiconductor structures 1000b, wherein the surrounding portion 111b exposes a first surface 1011b of the first semiconductor layer 101 b; and a first pad 80b and a second pad 90b are located on one or more of the semiconductor structures 1000 b. As shown in fig. 19 and 20, the one or more semiconductor structures 1000b each include a plurality of outer sidewalls 1001b and a plurality of inner sidewalls 1002b, wherein one end of the outer sidewalls 1001b is connected to a surface 102s of the second semiconductor layer 102b, and the other end of the outer sidewalls 1001b is connected to a first surface 1011b of the first semiconductor layer 101 b; one end of the inner sidewall 1002b is connected to the surface 102s of the second semiconductor layer 102b, and the other end of the inner sidewall 1002b is connected to the second surface 1012b of the first semiconductor layer 101 b.

In one embodiment of the present invention, when the light emitting element 3 has a side longer than 30mil, the light emitting element 3 further includes one or more holes 100b exposing one or more second surfaces 1012b of the first semiconductor layer 101b through the second semiconductor layer 102b and the active layer 103 b; and a contact layer 60b disposed on a first surface 1011b of the first semiconductor layer 101b to surround the periphery of the one or more semiconductor structures 1000b and contact the first semiconductor layer 101b to form an electrical connection, and formed on one or more second surfaces 1012b of the first semiconductor layer 101b to cover the one or more holes 100b and contact the first semiconductor layer 101b to form an electrical connection, wherein the contact layer 60b comprises a first contact layer 601b and a second contact layer 602b, the first contact layer 601b is disposed on the second semiconductor layer, surrounds a sidewall of the second semiconductor layer, and is connected to the first semiconductor layer, the second contact layer is disposed on the second semiconductor layer and is connected to the second semiconductor layer, the second contact layer 602b is surrounded by the first contact layer 601b, and the first contact layer 601b and the second contact layer 602b do not overlap each other.

In an embodiment of the present invention, when the light emitting element 3 includes a side length of less than 30mil, the light emitting element 3 may not include any hole 100b in order to obtain a larger light emitting area.

In an embodiment of the invention, the total surface area of the contact layer 60b is larger than the total surface area of the active layer 103b in a top view of the light emitting element 3.

In an embodiment of the invention, the total side of the periphery of the contact layer 60b is larger than the total side of the periphery of the active layer 103b in the upper view of the light emitting element 3.

In an embodiment of the present invention, the first contact layer 601b includes an area larger than that of the second contact layer 602b in a top view of the light emitting device 3.

In an embodiment of the present invention, the first bonding pad 80b and the second bonding pad 90b are formed around the hole portion 100b, such that any hole portion 100b is not covered by the first bonding pad 80b or the second bonding pad 90 b.

In an embodiment of the present invention, the first contact layer 601b connected to the first semiconductor layer 101b is not located under the second pad 90b in the cross-sectional view of the light emitting element 3.

In one embodiment of the present invention, the minimum distance between the first pad 80b and the second pad 90b is greater than 50 μm.

In one embodiment of the present invention, the distance between the first pad 80b and the second pad 90b is less than 300 μm.

In one embodiment of the present invention, the first pad 80b and the second pad 90b may be one or more layers of structures including metal materials. The material of the first pad 80b and the second pad 90b includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy thereof. When the first bonding pad 80b and the second bonding pad 90b are of a multi-layered structure, the first bonding pad 80b includes a first lower bonding pad (not shown) and a first upper bonding pad (not shown), and the second bonding pad 90b includes a second lower bonding pad (not shown) and a second upper bonding pad (not shown). The upper layer bonding pad and the lower layer bonding pad have different functions respectively. The function of the upper layer pad is mainly to solder and form a wire, by which the light emitting element 3 can be mounted on a mounting substrate in a flip chip form using a solder or AuSn eutectic bonding. Specific metal materials of the upper layer pad include high ductility materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os). The upper layer bonding pad can be a single layer, an alloy or a multi-layer film of the materials. In one embodiment of the present invention, the material of the upper layer pad preferably comprises nickel (Ni) and/or gold (Au), and the upper layer pad is a single layer or multiple layers. The function of the lower bonding pad forms a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b, for example, to increase the bonding strength of the interface of the first lower bonding pad and the contact layer 60b, or to increase the bonding strength of the interface of the second lower bonding pad and the reflective layer 40b and/or the barrier layer 41 b. Another function of the underlying bond pad is to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure, destroying the reflectivity of the reflective structure. Accordingly, the lower layer pad preferably contains a metal material other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), and the lower layer pad may be a single layer, an alloy, or a multilayer film of the above materials. In one embodiment of the present invention, the lower bonding pad preferably comprises a multilayer film of titanium (Ti), aluminum (Al), or a multilayer film of chromium (Cr), aluminum (Al).

In an embodiment of the present invention, when the light emitting element 3 is mounted on the package substrate in a flip chip form by the solder, the first pad 80b and the second pad 90b may have a height difference H therebetween. As shown in fig. 20, since the second insulating layer 50b under the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second bonding pad 90b includes the second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41b, when the first bonding pad 80b and the second bonding pad 90b are respectively formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, the topmost surface 80s of the first bonding pad 80b is higher than the topmost surface 90s of the second bonding pad 90b, and the topmost surface 80s of the first bonding pad 80b is higher than the topmost surface 90s of the second bonding pad 90 b. In other words, the top surface 80s of the first pad 80b and the top surface 90s of the second pad 90b have a height difference H therebetween, and the height difference H between the first pad 80b and the second pad 90b is substantially the same as the thickness of the second insulating layer 50 b. In one embodiment, the height difference between the first pad 80b and the second pad 90b may be between 0.5 μm and 2.5 μm, for example, 1.5 μm. When the first and

second pads

80b and 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the first pad 80b passes through the third insulating layer opening 701b to be in contact with the first contact layer 601b and extends from the third insulating layer opening 701b to cover a portion of the surface of the third insulating layer 70b, and the second pad 90b passes through the other third insulating layer opening 702b to be in contact with the second contact layer 602b and extends from the other third insulating layer opening 702b to cover a portion of the surface of the third insulating layer 70 b.

Fig. 21 is a top view of a light emitting element 4 disclosed in an embodiment of the present invention. Fig. 22 is a cross-sectional view of the light emitting element 4 disclosed in an embodiment of the present invention. The light emitting element 4 has substantially the same structure as the light emitting element 3 except that the structures of the first bonding pad and the second bonding pad are different from those of the light emitting element 3 in the above embodiment, and elements of the light emitting element 4 and the light emitting element 3 having the same reference numerals are not described here. When the light emitting element 4 is mounted on the package substrate in a flip chip form by AuSn eutectic bonding, the smaller the height difference between the first pad 80b and the second pad 90b is, the better the stability between the pads and the package substrate is increased. As shown in fig. 22, the second insulating layer 50b under the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41b. In this embodiment, in order to reduce the height difference between the topmost surface 80s of the first pad 80b and the topmost surface 90s of the second pad 90b, the third insulating layer opening 701b includes a width larger than that of another third insulating layer opening 702 b. When the first and

second bonding pads

80b and 90b are respectively formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, the entirety of the first bonding pad 80b is formed in the third insulating layer opening 701b to be in contact with the first contact layer 601b, the second bonding pad 90b is formed in the other third insulating layer opening 702b to be in contact with the reflective layer 40b and/or the barrier layer 41b, and the second bonding pad 90b extends from the third insulating layer opening 702b to cover a portion of the surface of the third insulating layer 70 b. In other words, the third insulating layer is not formed under the first pad 80b, but a portion of the third insulating layer is formed under the second pad 90 b. In the present embodiment, the height difference between the first pad 80b and the second pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm.

Fig. 23 is a cross-sectional view of a light-emitting element 5 disclosed in an embodiment of the present invention. The light emitting element 5 has substantially the same structure as the light emitting element 3 and the light emitting element 4 except for the structure of the second bonding pad, compared with the light emitting element 3 and the light emitting element 4 in the above embodiment, and elements of the light emitting element 5, the light emitting element 3 and the light emitting element 4 having the same reference numerals are not described here. When the light emitting element 5 is mounted on the package substrate in a flip chip form by AuSn eutectic bonding, the smaller the height difference between the first pad 80b and the second pad 90b is, the better the stability between the pads and the package substrate is increased. As described above, in addition to forming a portion of the third insulating layer under the second pad 90b, a second buffer 910b may be formed under the second pad 90b to reduce the height difference between the top surface of the first pad 80b and the top surface of the second pad 90 b. As shown in fig. 23, the second insulating layer 50b under the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41b. In the present embodiment, the entirety of the first pad 80b is formed in the third insulating layer opening 701b to be in contact with the first contact layer 601b, and the entirety of the second pad 90b is formed in another third insulating layer opening 702b to be in contact with the second contact layer 602b, in other words, the third insulating layer is not formed under the first pad 80b and under the second pad 90 b. In this embodiment, the second buffer pad 910b is disposed between the second pad 90b and the second contact layer 602b to reduce the height difference between the top surface of the first pad 80b and the top surface of the second pad 90b, wherein the second buffer pad 910b preferably comprises a metal material other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), to prevent tin (Sn) in the AuSn eutectic from diffusing into the light emitting element 5. In the present embodiment, the difference in height between the top surface of the first pad 80b and the top surface of the second pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm. In this embodiment, the second buffer pad 910b has a thickness substantially the same as that of the second insulating layer 50 b.

Fig. 24 is a cross-sectional view of a light-emitting element 6 disclosed in an embodiment of the present invention. The light emitting element 6 has substantially the same structure as the light emitting element 3 and the light emitting element 4 except that the third insulating layer 70b under the first pad 80b is different from the light emitting element 3 and the light emitting element 4 in the above embodiment, and elements of the light emitting element 6, the light emitting element 3 and the light emitting element 4 having the same reference numerals are not described here. As shown in fig. 24, the third insulating layer 70b may be formed on the semiconductor stack 10b by evaporation or deposition, and patterned by photolithography and etching, so as to form a third insulating layer opening 701b on the first contact layer 601b to expose the first contact layer 601b, and form another third insulating layer opening 702b on the second contact layer 602b to expose the second contact layer 602b. The first bonding pad 80b and the second bonding pad 90b may be formed on the semiconductor stack 10b by electroplating, vapor deposition, or the like, and then patterned by photolithography and etching. The first pad 80b contacts the first contact layer 601b through the third insulating layer opening 701b and forms an electrical connection with the first semiconductor layer 101b through the first contact layer 601 b. In order to avoid that the first contact layer 601b under the first pad 80b and the second insulating layer 50b are excessively etched and removed to expose the reflective layer 40b and/or the barrier layer 41b during the etching process for forming the third insulating layer opening 701b when the third insulating layer 70b is etched, the area of the third insulating layer 70b under the first pad 80b etched to form the third insulating layer opening 701b is reduced, the first portion of the third insulating layer 70b is remained between the first pad 80b and the first contact layer 601b and is completely covered by the first pad 80b, the other second portion of the third insulating layer 70b is located around the first pad 80b, and the gap between the first portion and the second portion of the third insulating layer 70b forms the third insulating layer opening 701b. Specifically, the first portion of the third insulating layer 70b completely covered by the first pad 80b includes a width greater than the width of the third insulating layer opening 701b under the pad 80 b. In this embodiment, the third insulating layer opening 701b is a ring-shaped opening in a top view of the light emitting device.

Fig. 25 is a schematic view of a light emitting device according to an embodiment of the invention. The semiconductor light emitting element 1, the light emitting element 2, the light emitting element 3, the light emitting element 4, the light emitting element 5, or the light emitting element 6 in the foregoing embodiment are flip-chip mounted on the first pad 511, the second pad 512 of the package substrate 51. The first pad 511 and the second pad 512 are electrically insulated by an insulating portion 53 containing an insulating material. The flip chip mounting is performed with one side of the

growth substrates

11a,11b facing the electrode formation surface as a main light extraction surface. In order to increase the light extraction efficiency of the light emitting device, a reflective structure 54 may be disposed around the semiconductor light emitting element 1, the light emitting element 2, the light emitting element 3, the light emitting element 4, the light emitting element 5, or the light emitting element 6.

Fig. 26 is a schematic diagram of a light emitting device according to an embodiment of the invention. A bulb lamp 600 includes a lamp housing 602, a reflector 604, a light module 610, a lamp base 612, a heat sink 614, a connection 616, and an electrical connection member 618. The light emitting module 610 includes a carrying portion 606, and a plurality of light emitting elements 608 are disposed on the carrying portion 606, wherein the plurality of light emitting elements 608 can be the semiconductor light emitting element 1, the light emitting element 2, the light emitting element 3, the light emitting element 4, the light emitting element 5 or the light emitting element 6 in the foregoing embodiments.

The examples set forth herein are intended to be illustrative of the invention and are not intended to limit the scope of the invention. Any obvious modification or variation of the present invention may be made without departing from the spirit and scope of the present invention.

Claims

1. A light-emitting element, comprising:

a semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer;

a plurality of hole portions penetrating the active layer to expose the second surface of the first semiconductor layer;

a surrounding portion surrounding the semiconductor stack, wherein the surrounding portion exposes the first surface of the first semiconductor layer;

a first contact layer contacting the second surfaces of the plurality of hole portions and the first surface of the surrounding portion and extending to cover the second semiconductor layer;

a third insulating layer including one or more third insulating layer openings on the second semiconductor layer to expose the first contact layer and offset from the plurality of holes;

a first bonding pad on the semiconductor stack layer covering the one or more third insulating layer openings to contact the first contact layer; and

a second bonding pad on the semiconductor layer stack and spaced apart from the first bonding pad, defining a region on the semiconductor layer stack between the first bonding pad and the second bonding pad,

Wherein in a top view of the light emitting device, the plurality of holes are located in the region, one of the first bonding pad and the second bonding pad does not cover the plurality of holes, and the one of the first bonding pad and the second bonding pad comprises two first concave portions and a first convex portion located at one side of the one of the first bonding pad and the second bonding pad in the top view, and the first convex portion is located between the two first concave portions, the positions of the two first concave portions respectively correspond to two of the plurality of holes and are formed around the two of the plurality of holes so that the width of the first concave portion of the first bonding pad or the second bonding pad is larger than the diameter of any hole of the plurality of holes.

2. The light emitting device of claim 1, further comprising a second contact layer on the second semiconductor layer, wherein the first contact layer and the second contact layer do not overlap each other in the top view of the light emitting device, the first contact layer comprises an area greater than an area of the second contact layer, and the second contact layer is surrounded by the first contact layer.

3. The light emitting device of claim 2, further comprising a second insulating layer comprising one or more second insulating layer first openings exposing the first semiconductor layer and one or more second insulating layer second openings on the second semiconductor layer, wherein the one or more second insulating layer first openings are separated from each other and correspond to the plurality of holes, respectively, and the second contact layer covers the one or more second insulating layer second openings.

4. The light emitting device of claim 2, wherein the third insulating layer comprises one or more third insulating layer openings to expose the second contact layer, and the second bonding pad passes through the one or more third insulating layer openings to contact the second contact layer.

5. The light-emitting device according to claim 1, wherein the one or more third insulating layer openings are offset from the plurality of holes and do not overlap each other.

6. The light emitting device of claim 1, wherein one of the first and second pads does not cover the plurality of holes.

7. The light emitting device of claim 6, wherein the other of the first and second bonding pads comprises two second recesses and a second protrusion on the top view on one side of the other of the first and second bonding pads.

8. The light-emitting device according to claim 7, wherein the second protruding portion is located between the two second recessed portions, and positions of the two second recessed portions correspond to and are formed around another two of the plurality of hole portions, respectively.

9. The light-emitting device according to claim 7, wherein a width of the two first recesses and/or the two second recesses is larger than a diameter of any one of the plurality of holes.

10. A light emitting device comprising the light emitting element of any one of claims 1 to 8, further comprising a package substrate, a first pad and a second pad, wherein the light emitting element is flip-chip mounted on the first pad and the second pad of the package substrate.