CN111987211A

CN111987211A - Light emitting element

Info

Publication number: CN111987211A
Application number: CN202010788559.0A
Authority: CN
Inventors: 陈昭兴; 王佳琨; 曾咨耀; 胡柏均; 蒋宗勋; 庄文宏; 李冠亿; 林昱伶; 沈建赋; 柯淙凯
Original assignee: Epistar Corp
Current assignee: Epistar Corp
Priority date: 2015-11-18
Filing date: 2015-11-18
Publication date: 2020-11-24
Anticipated expiration: 2035-11-18
Also published as: CN106711316A; CN106711316B; CN111987211B; CN111987208B; CN111987209A; CN111987208A; CN111987210A

Abstract

The invention discloses a light-emitting element, which comprises a semiconductor lamination layer, a first semiconductor layer, a second semiconductor layer and an active layer, wherein the active layer is positioned between the first semiconductor layer and the second semiconductor layer; a first bonding pad on the semiconductor stack; a second bonding pad located on the semiconductor lamination layer and spaced from the first bonding pad by a certain distance, and defining a region located between the first bonding pad and the second bonding pad on the semiconductor lamination layer; and a plurality of holes penetrate through the active layer to expose the first semiconductor layer, wherein the first bonding pad and the second bonding pad are formed in the region outside the holes on the top view of the light-emitting element.

Description

Light emitting element

The application is a divisional application of Chinese invention patent application (application number: 201510794248.4, application date: 2015, 11/18 th, invention name: light-emitting element).

Technical Field

The present invention relates to a light emitting device, and more particularly, to a light emitting device including a semiconductor stack and a bonding pad on the semiconductor stack.

Background

Light-Emitting diodes (LEDs) are solid-state semiconductor Light-Emitting elements that have the advantages of low power consumption, low heat generation, long operating life, shock resistance, small size, fast response speed, and good optoelectronic properties, such as stable emission wavelength. Therefore, the light emitting diode is widely applied to household appliances, equipment indicator lamps, photoelectric products and the like.

Disclosure of Invention

The light-emitting element comprises a semiconductor lamination layer which is provided with a first semiconductor layer, a second semiconductor layer and an active layer positioned between the first semiconductor layer and the second semiconductor layer; a first bonding pad on the semiconductor stack; a second bonding pad on the semiconductor laminate, wherein the first bonding pad and the second bonding pad are separated by a distance, and a region defined on the semiconductor laminate is located between the first bonding pad and the second bonding pad; and a plurality of holes penetrate through the active layer to expose the first semiconductor layer, wherein the first bonding pad and the second bonding pad are formed in the region outside the positions of the holes on the top view of the light-emitting element.

The light-emitting element comprises a semiconductor lamination layer which is provided with a first semiconductor layer, a second semiconductor layer and an active layer positioned between the first semiconductor layer and the second semiconductor layer; a first contact layer located on the second semiconductor layer, surrounding a sidewall of the second semiconductor layer, and connected to the first semiconductor layer; a second contact layer located on the second semiconductor layer and connected with the second semiconductor layer; a first bonding pad on the semiconductor stack layer and connected to the first contact layer; and a second bonding pad on the semiconductor laminate and connected with the second contact layer, wherein the first bonding pad is spaced from the second bonding pad by a distance, and an area is defined on the semiconductor laminate and located between the first bonding pad and the second bonding pad, and the first contact layer on the second semiconductor layer surrounds the second contact layer in a top view of the light-emitting device.

Drawings

Fig. 1A to 7C are schematic diagrams illustrating a method for manufacturing a light-emitting device 1 or a light-emitting device 2 according to an embodiment of the present invention;

fig. 8 is a top view of the light emitting device 1 according to an embodiment of the present invention;

fig. 9A is a cross-sectional view of a light-emitting device 1 according to an embodiment of the present invention;

fig. 9B is a cross-sectional view of the light-emitting device 1 according to the embodiment of the present invention;

fig. 10 is a top view of the light emitting device 2 according to an embodiment of the present invention;

fig. 11A is a cross-sectional view of a light emitting device 2 according to an embodiment of the present invention;

fig. 11B is a cross-sectional view of the light emitting device 2 according to the embodiment of the present invention;

fig. 12A to 18B are schematic diagrams illustrating a method for manufacturing the light-emitting device 3 or the light-emitting device 4 according to an embodiment of the present invention;

FIG. 19 is a top view of the light emitting device 3 according to one embodiment of the present invention;

fig. 20 is a sectional view of a light emitting device 3 according to an embodiment of the present invention;

FIG. 21 is a top view of the light emitting device 4 according to one embodiment of the present invention;

FIG. 22 is a cross-sectional view of a light emitting device 4 according to an embodiment of the present invention;

fig. 23 is a cross-sectional view of a light emitting device 5 according to an embodiment of the present invention;

FIG. 24 is a cross-sectional view of a light emitting device 6 according to an embodiment of the present invention;

FIG. 25 is a schematic structural diagram of a light-emitting device according to an embodiment of the invention;

fig. 26 is a schematic structural diagram of a light-emitting device according to an embodiment of the invention.

Description of the symbols

1, 2, 3, 4, 5, 6 light emitting element

11a, 11b substrate

10a, 10b semiconductor stack

101a, 101b first semiconductor layer

102a, 102b second semiconductor layer

103a, 103b active layer

100a, 100b hole parts

102s surface

1011a, 1011b first surface

1012a, 1012b second surface

110a fourth insulating layer

111a, 111b surround

20a, 20b first insulating layer

200a, 200b first insulating layer surrounding region

201a, 201b first insulating layer footprint

202a, 202b first insulating layer opening

203a, 203b first insulating layer opening

30a, 30b transparent conductive layer

300b transparent conductive layer opening

301a, 301b transparent conductive layer outer edge

40a, 40b reflective layer

400b reflective layer opening

401a, 401b reflective layer outer edge

41a, 41b barrier layer

410b barrier layer opening

411a, 411b outer edge of barrier layer

50a, 50b second insulating layer

501a, 501b second insulating layer opening

502a, 502b second insulating layer opening

5020b Ring opening

5021b side wall

60a, 60b contact layer

600a, 600b thimble region

602a contact layer opening

601b first contact layer

6011b first contact layer sidewall

602b second contact layer

6021b second contact layer sidewall

70a, 70b third insulating layer

701a, 702a third insulating layer opening

701b, 702b third insulating layer opening

80a, 80b first pads

90a, 90b second pad

800a first pad opening

801b first projection

802a first side edge

802b first recess

803b first flat edge

804a first recess

805a first upper layer pad

807a first lower layer pad

810a first cushion

900a second pad opening

901b second projection

902a second side edge

902b second recess

903b second Flat edge

904a second recess

905a second Upper layer pad

907a second lower layer bonding pad

910a, 910b second cushion

1000a, 1000b semiconductor structure

1001a, 1001b second outer side wall

1002a, 1002b inner side wall

1003a, 1003b first outer side wall

51 packaging substrate

511 first gasket

512 second gasket

53 insulating part

54 reflective structure

600 bulb lamp

602 lampshade

604 reflecting mirror

606 bearing part

608 luminous element

610 luminous module

612 lamp holder

614 Heat sink

616 connection part

618 electric connection element

Detailed Description

For a more complete and complete description of the present invention, reference is now made to the following description of the embodiments, taken in conjunction with the accompanying drawings. However, the following examples are provided to illustrate the light-emitting element of the present invention, and the present invention is not limited to the following examples. The dimensions, materials, shapes, relative arrangements and the like of the constituent elements described in the embodiments of the present invention are not limited to the above description, and the scope of the present invention is not limited to these, but is merely illustrative. The sizes and positional relationships of the components shown in the drawings may be exaggerated for clarity. In the following description, the same or similar members are denoted by the same names and symbols for the sake of appropriately omitting detailed description.

Fig. 1A to 11B illustrate a method for manufacturing a light emitting device 1 or a light emitting device 2 according to an embodiment of the present invention.

As shown in the top view of fig. 1A and the cross-sectional view of fig. 1B along line a-a' of fig. 1A, the method for manufacturing the

light emitting device

1 or 2 includes a step of forming a platform, which includes providing a substrate 11A; and forming a semiconductor stack 10a on the substrate 11a, wherein the semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a between the first semiconductor layer 101a and the second semiconductor layer 102 a. The semiconductor stack 10a may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102a and the active layer 103a, thereby forming one or more semiconductor structures 1000 a; and a surrounding portion 111a surrounding the one or more semiconductor structures 1000 a. The surrounding portion 111a exposes a first surface 1011a of the first semiconductor layer 101 a. The one or more semiconductor structures 1000a each comprise a plurality of first outer sidewalls 1003a, second outer sidewalls 1001a, and a plurality of inner sidewalls 1002a, wherein the first outer sidewalls 1003a are sidewalls of the first semiconductor layer 101a, the second outer sidewalls 1001a are sidewalls of the active layer 103a and/or the second semiconductor layer 102a, one end of the second outer sidewalls 1001a is connected to a surface 102s of the second semiconductor layer 102a, and the other end of the second outer sidewalls 1001a is connected to the first surface 1011a of the first semiconductor layer 101 a; one end of the inner sidewall 1002a is connected to the surface 102s of the second semiconductor layer 102a, and the other end of the inner sidewall 1002a is connected to the second surface 1012a of the first semiconductor layer 101 a; the plurality of semiconductor structures 1000a are connected to each other through the first semiconductor layer 101 a. As seen in fig. 1B, an obtuse angle is formed between the inner sidewall 1002a of the semiconductor structure 1000a and the second surface 1012a of the first semiconductor layer 101a, an obtuse angle or a right angle is formed between the first outer sidewall 1003a of the semiconductor structure 1000a and the surface 11s of the substrate 11a, and an obtuse angle is formed between the second outer sidewall 1001a of the semiconductor structure 1000a and the first surface 1011a of the first semiconductor layer 101 a. The surrounding portion 111a surrounds the semiconductor structure 1000a, and the surrounding portion 111a is rectangular or polygonal in a top view of the light emitting device 1 or the light emitting device 2.

In an embodiment of the present invention, the light emitting device 1 or the light emitting device 2 includes a side length less than 30 mils. When an external current is injected into the light-emitting device 1 or the light-emitting device 2, the surrounding portion 111a surrounds the periphery of the semiconductor structure 1000a, so that the optical field distribution of the light-emitting device 1 or the light-emitting device 2 can be uniformized, and the forward voltage of the light-emitting device can be reduced.

In an embodiment of the present invention, the light emitting device 1 or the light emitting device 2 includes a side length greater than 30 mils. The semiconductor stack 10a may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102a and the active layer 103a, and form one or more holes 100a through the second semiconductor layer 102a and the active layer 103a, wherein the one or more holes 100a expose one or more second surfaces 1012a of the first semiconductor layer 101 a. When an external current is injected into light-emitting element 1 or light-emitting element 2, the light field distribution of light-emitting element 1 or light-emitting element 2 can be uniformized and the forward voltage of light-emitting element can be reduced by the distributed arrangement of surrounding portion 111a and plurality of holes 100 a.

In an embodiment of the invention, the light emitting device 1 or the light emitting device 2 includes a side length less than 30 mils, and the light emitting device 1 or the light emitting device 2 may not include one or more holes 100 a.

In an embodiment of the invention, the opening shape of the one or more hole portions 100a includes a circle, an ellipse, a rectangle, a polygon, or an arbitrary shape. The plurality of hole portions 100a may be arranged in a plurality of rows, and the hole portions 100a in two adjacent rows may be aligned with or offset from each other.

In one embodiment of the present invention, the substrate 11a may be a growth substrate including a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP) or sapphire (Al) wafer for growing indium gallium nitride (InGaN)₂O₃) A wafer, a gallium nitride (GaN) wafer, or a silicon carbide (SiC) wafer. A semiconductor stack 10a having electro-optical characteristics, such as a light-emitting (light-emitting) stack, may be formed on the substrate 11a by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), hydride vapor deposition (HVPE), evaporation, or ion plating.

In an embodiment of the invention, the first semiconductor layer 101a and the second semiconductor layer 102a are, for example, a cladding layer (cladding layer) or a confining layer (confining layer), and both of themHave different conductivity types, electrical properties, polarities, or may be doped with elements to provide electrons or holes, for example, the first semiconductor layer 101a is an n-type conductivity semiconductor and the second semiconductor layer 102a is a p-type conductivity semiconductor. The active layer 103a is formed between the first semiconductor layer 101a and the second semiconductor layer 102a, and electrons and holes are recombined in the active layer 103a under a current driving, so that electric energy is converted into light energy to emit light. The wavelength of light emitted from the light-emitting element 1 or the light-emitting element 2 is adjusted by changing the physical and chemical composition of one or more layers of the stacked semiconductor layers 10 a. The material of the semiconductor stack 10a includes a group III-V semiconductor material, such as Al_xIn_yGa_(1-x-y)N or Al_xIn_yGa_(1-x-y)P, wherein 0 ≦ x, y ≦ 1; (x + y) ≦ 1. According to the material of the active layer 103a, when the semiconductor stack 10a is an AlInGaP series material, the semiconductor stack can emit red light with a wavelength between 610nm and 650nm, green light with a wavelength between 530nm and 570nm, when the semiconductor stack 10a is an InGaN series material, the semiconductor stack can emit blue light with a wavelength between 450nm and 490nm, or when the semiconductor stack 10a is an AlGaN series material, the semiconductor stack can emit ultraviolet light with a wavelength between 400nm and 250 nm. The active layer 103a may be a Single Heterostructure (SH), a Double Heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MQW). The material of the active layer 103a may be a neutral, p-type or n-type conductivity semiconductor.

Following the step of forming the mesa, as shown in the top view of fig. 2A and the cross-sectional view of fig. 2B along the line a-a' of fig. 2A, the method of manufacturing the

light emitting device

1 or 2 includes a step of forming a first insulating layer. A first insulating layer 20a may be formed on the semiconductor structure 1000a by evaporation or deposition, and patterned by photolithography and etching to cover the first surface 1011a of the surrounding portion 111a and the second surface 1012a of the hole portion 100a, and to cover the second semiconductor layer 102a of the semiconductor structure 1000a, the second outer sidewall 1001a of the active layer 103a, and the inner sidewall 1002a, wherein the first insulating layer 20a includes a first insulating layer surrounding region 200a to cover the first insulating layer surrounding region 200aThe surrounding portion 111a is such that the first surface 1011a of the first semiconductor layer 101a located at the surrounding portion 111a is covered by the surrounding region 200a of the first insulating layer; a first group of first insulation layer covering regions 201a for covering the hole 100a, such that the second surface 1012a of the first semiconductor layer 101a located in the hole 100a is covered by the first group of first insulation layer covering regions 201 a; and a second group of first insulating layer openings 202a to expose the surface 102s of the second semiconductor layer 102 a. The first insulating layer covering regions 201a of the first group are separated from each other and respectively correspond to the plurality of hole portions 100 a. The first insulating layer 20a may be of a single-layer or multi-layer construction. When the first insulating layer 20a is a single layer film, the first insulating layer 20a can protect sidewalls of the semiconductor structure 1000a to prevent the active layer 103a from being damaged by a subsequent manufacturing process. When the first insulating layer 20a is a multilayer film, the first insulating layer 20a may include more than two materials having different refractive indexes alternately stacked to form a bragg reflector (DBR) structure selectively reflecting light of a specific wavelength. The first insulating layer 20a is made of a non-conductive material, and includes an organic material, such as Su8, benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Epoxy (Epoxy), Acrylic Resin (Acrylic Resin), cyclic olefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (polyethylimide), Fluorocarbon Polymer (Fluorocarbon Polymer), or an inorganic material, such as silicon gel (Silicone), Glass (Glass), or a dielectric material, such as aluminum oxide (Al)₂O₃) Silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or magnesium fluoride (MgF)_x)。

In an embodiment of the invention, following the first insulating layer forming step, as shown in the top view of fig. 3A and the cross-sectional view along the line a-a' of fig. 3B, the method for manufacturing the

light emitting device

1 or 2 includes a transparent conductive layer forming step. A transparent conductive layer 30a can be formed in the first insulating layer openings 202a of the second group by evaporation or deposition, wherein an outer edge 301a of the transparent conductive layer 30a is spaced apart from the first insulating layer 20a to expose the surface 102s of the second semiconductor layer 102 a. Since the transparent conductive layer 30a is formed over substantially the entire surface of the second semiconductor layer 102a and is in contact with the second semiconductor layer 102a, the transparent conductive layer 30a can uniformly diffuse a current to the entire second semiconductor layer 102 a. The material of the transparent conductive layer 30a includes a material transparent to light emitted from the active layer 103a, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In another embodiment of the present invention, after the step of forming the mesa, a step of forming a transparent conductive layer may be performed, and then a step of forming a first insulating layer may be performed.

In another embodiment of the present invention, after the step of forming the mesa, the step of forming the first insulating layer may be omitted and the step of forming the transparent conductive layer may be directly performed.

In an embodiment of the invention, following the transparent conductive layer forming step, as shown in the top view of fig. 4A and the cross-sectional view of fig. 4B along the line a-a' of fig. 4A, the method for manufacturing the light emitting device 1 or the light emitting device 2 includes a reflective structure forming step. The reflective structure includes a reflective layer 40a and/or a barrier layer 41a, which can be directly formed on the transparent conductive layer 30a by evaporation or deposition, wherein the reflective layer 40a is located between the transparent conductive layer 30a and the barrier layer 41 a. In a top view of the light-emitting device 1 or the light-emitting device 2, the outer edge 401a of the reflective layer 40a may be disposed inside, outside, or in coincident alignment with the outer edge 301a of the transparent conductive layer 30a, and the outer edge 411a of the barrier layer 41a may be disposed inside, outside, or in coincident alignment with the outer edge 401a of the reflective layer 40 a.

In another embodiment of the present invention, the formation of the transparent conductive layer can be omitted, and after the step of forming the mesa or the step of forming the first insulating layer, the step of forming the reflective structure is directly performed, for example, the reflective layer 40a and/or the barrier layer 41a are directly formed on the second semiconductor layer 102a, and the reflective layer 40a is located between the second semiconductor layer 102a and the barrier layer 41 a.

The reflective layer 40a may be one or more layers, such as a bragg reflector. The material of the reflective layer 40a includes a metal material having a high reflectance, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy of the above materials. The term "have a high reflectance" as used herein means that the reflectance is 80% or more with respect to the wavelength of light emitted from the light-emitting element 1 or the light-emitting element 2. In an embodiment of the present invention, the barrier layer 41a covers the reflective layer 40a to prevent the surface of the reflective layer 40a from being oxidized to deteriorate the reflectivity of the reflective layer 40 a. The material of the barrier layer 41a includes a metal material, for example, a metal such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. The barrier layer 41a may have one or more layers, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In one embodiment of the present invention, the barrier layer 41a includes a titanium (Ti)/aluminum (Al) stack structure on a side away from the reflective layer 40a, and a titanium (Ti)/tungsten (W) stack structure on a side close to the reflective layer 40 a. In an embodiment of the present invention, the materials of the reflective layer 40a and the barrier layer 41a preferably include a metal material other than gold (Au) or copper (Cu).

In an embodiment of the invention, following the step of forming the reflective structure, as shown in the top view of fig. 5A, fig. 5B is a cross-sectional view of fig. 5A taken along a-a ', and fig. 5C is a cross-sectional view taken along a line B-B' of fig. 5A, the method of manufacturing the

light emitting device

1 or 2 includes a step of forming a second insulating layer. A second insulating layer 50a may be formed on the semiconductor structure 1000a by evaporation or deposition, and patterned by photolithography and etching to form a first group of second insulating layer openings 501a to expose the first semiconductor layer 101a, and a second group of second insulating layer openings 502a to expose the reflective layer 40a or the barrier layer 41a, wherein during the patterning of the second insulating layer 50a, the first insulating layer surrounding region 200a of the surrounding portion 111a and the first insulating layer covering region 201a of the first group in the hole portion 100a in the first insulating layer forming step are partially etched away to expose the first semiconductor layer 101 a; a first group of first insulating layer openings 203a is formed in the hole portion 100a to expose the first semiconductor layer 101 a. In the present embodiment, in the cross-sectional view of the light emitting device 1 or the light emitting device 2, as shown in fig. 5B, the first group of the second insulating layer openings 501a and the second group of the second insulating layer openings 502a haveDifferent width, number. The opening shapes of the first group of second insulating layer openings 501a and the second group of second insulating layer openings 502a include a circle, an ellipse, a rectangle, a polygon, or an arbitrary shape. In the present embodiment, as shown in fig. 5A, the first group of second insulating layer openings 501a are separated from each other and arranged in a plurality of rows, and respectively correspond to the plurality of hole portions 100a and the first group of first insulating layer openings 203a, the second group of second insulating layer openings 502a are close to one side of the substrate 11a, for example, the left side or the right side of the center line of the substrate 11a, and the second group of second insulating layer openings 502a are separated from each other and located between the adjacent two rows of first group of second insulating layer openings 501 a. The second insulating layer 50a may be of a single-layer or multi-layer construction. When the second insulating layer 50a is a single layer film, the second insulating layer 50a can protect sidewalls of the semiconductor structure 1000a to prevent the active layer 103a from being damaged by a subsequent manufacturing process. When the second insulating layer 50a is a multilayer film, the second insulating layer 50a may include more than two materials having different refractive indexes alternately stacked to form a bragg reflector (DBR) structure selectively reflecting light of a specific wavelength. The second insulating layer 50a is made of a non-conductive material, and includes an organic material, such as Su8, benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Epoxy (Epoxy), Acrylic Resin (Acrylic Resin), cyclic olefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (polyethylimide), Fluorocarbon Polymer (Fluorocarbon Polymer), or an inorganic material, such as silicon gel (Silicone), Glass (Glass), or a dielectric material, such as aluminum oxide (Al)₂O₃) Silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or magnesium fluoride (MgF)_x)。

In an embodiment of the invention, as shown in the top view of fig. 6A, the sectional view of fig. 6B along the line a-a 'of fig. 6A, and the sectional view of fig. 6C along the line B-B' of fig. 6A, the method for manufacturing the light emitting device 1 or the light emitting device 2 includes a contact layer forming step. A contact layer 60a may be formed on the first semiconductor layer 101a and the second semiconductor layer 102a by evaporation or deposition, and patterned by photolithography and etching, and one or more contact layer openings 602a are formed on the second group of second insulating layer openings 502a to expose the reflective layer 40a or the barrier layer 41a, and define a tip region 600a at the geometric center of the light emitting device 1 or the light emitting device 2. In the cross-sectional view of the light emitting device 1 or the light emitting device 2, the contact layer opening 602a includes a width greater than that of any one of the second insulating layer openings 502a of the second group. In the top view of the light emitting element 1 or the light emitting element 2, the plurality of contact layer openings 602a are all close to one side of the substrate 11a, for example, the left side or the right side of the center line of the substrate 11 a. The contact layer 60a may have a structure of one or more layers. In order to reduce the resistance In contact with the first semiconductor layer 101a, the material of the contact layer 60a includes a metal material, for example, chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. In an embodiment of the present invention, the material of the contact layer 60a preferably includes a metal material other than gold (Au) or copper (Cu). In an embodiment of the present invention, the material of the contact layer 60a preferably includes a metal with high reflectivity, such as aluminum (Al), platinum (Pt). In an embodiment of the present invention, a side of the contact layer 60a contacting the first semiconductor layer 101a preferably includes chromium (Cr) or titanium (Ti) to increase bonding strength with the first semiconductor layer 101 a.

In an embodiment of the invention, the contact layer 60a covers all the holes 100a and extends over the second semiconductor layer 102a, wherein the contact layer 60a is insulated from the second semiconductor layer 102a by the second insulating layer 50a, and the contact layer 60a contacts the first semiconductor layer 101a through the holes 100 a. When an external current is injected into the light emitting element 1 or the light emitting element 2, the current is conducted to the first semiconductor layer 101a through the plurality of hole portions 100 a. In this embodiment, a first shortest distance is included between two adjacent hole portions 100a located on the same row, and a second shortest distance is included between any one of the hole portions 100a adjacent to the edge of the light emitting device and the first outer sidewall 1003a of the first semiconductor layer 101a, where the first shortest distance is greater than the second shortest distance.

In another embodiment of the present invention, the contact layer 60a covers the surrounding portion 111a and the hole portion 100a, and extends to cover the second semiconductor layer 102a, wherein the contact layer 60a is insulated from the second semiconductor layer 102a by the second insulating layer 50a, and the contact layer 60a contacts the first semiconductor layer 101a through the surrounding portion 111a and the hole portion 100 a. When an external current is injected into the light emitting element 1 or the light emitting element 2, a part of the current is conducted to the first semiconductor layer 101a through the surrounding portion 111a, and another part of the current is conducted to the first semiconductor layer 101a through the plurality of hole portions 100 a. In this embodiment, a first shortest distance is included between two adjacent hole portions 100a located on the same row, and a second shortest distance is included between any one of the hole portions 100a adjacent to the edge of the light emitting device and the first outer sidewall 1003a of the first semiconductor layer 101a, wherein the first shortest distance is less than or equal to the second shortest distance.

In another embodiment of the present invention, the plurality of hole portions 100a may be arranged in a first row and a second row, two adjacent hole portions 100a in the same row include a first shortest distance therebetween, and the hole portions 100a in the first row and the hole portions 100a in the second row include a second shortest distance therebetween, wherein the first shortest distance is greater than or less than the second shortest distance.

In an embodiment of the invention, the plurality of hole portions 100a may be arranged in a first row, a second row and a third row, a first shortest distance is included between the hole portions 100a on the first row and the hole portions 100a on the second row, and a second shortest distance is included between the hole portions 100a on the second row and the hole portions 100a on the third row, wherein the first shortest distance is smaller than the second shortest distance.

In an embodiment of the invention, following the contact layer forming steps shown in fig. 6A, 6B and 6C, the method for manufacturing the

light emitting device

1 or 2 includes a third insulating layer forming step, as shown in the top view of fig. 7A, the cross-sectional view of fig. 7B along the line a-a 'of fig. 7A and the cross-sectional view of fig. 7C along the line B-B' of fig. 7A, a third insulating layer 70a may be formed on the semiconductor structure 1000a by evaporation or deposition, and patterned by photolithography and etching, a first group of third insulating layer openings 701a may be formed on the contact layer 60a to expose the contact layer 60a shown in fig. 6A, and one or more contact layer openings may be formed on the contact layer 60aA second group of third insulating layer openings 702a is formed on the contact layer openings 602a to expose the reflective layer 40a or the barrier layer 41a shown in fig. 6A, wherein the contact layer 60a on the second semiconductor layer 102a is sandwiched between the second insulating layer 50a and the third insulating layer 70a, and the first group of third insulating layer openings 701a and the first group of second insulating layer openings 501a are staggered and do not overlap with each other. The pin-top region 600a is surrounded and encapsulated by a third insulating layer. In the present embodiment, as shown in fig. 7A, the third insulating layer openings 701a of the first group are separated from each other and are staggered from the plurality of hole portions 100 a. The second group of third insulating layer openings 702a are separated from each other and respectively correspond to the plurality of contact layer openings 602 a. In the top view of fig. 7A, the first group of third insulating layer openings 701a is near one side, e.g., the right side, of the substrate 11a, and the second group of third insulating layer openings 702a is near the other side, e.g., the left side, of the centerline of the substrate 11a, of the substrate 11 a. In the cross-sectional view of the light emitting device 1 or the light emitting device 2, the third insulating layer opening 702a of any one of the second groups includes a width smaller than that of any one of the contact layer openings 602a, and the third insulating layer 70a conforms to the contact layer opening 602a and fills in the sidewall covering the contact layer opening 602a to expose the reflective layer 40a or the barrier layer 41a, thereby forming the third insulating layer opening 702a of the second group. The third insulating layer 70a may be of a single-layer or multi-layer construction. When the third insulating layer 70a is a multilayer film, the third insulating layer 70a may include more than two materials having different refractive indexes alternately stacked to form a bragg reflector (DBR) structure selectively reflecting light of a specific wavelength. The third insulating layer 70a is made of a non-conductive material, and includes an organic material, such as Su8, benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Epoxy (Epoxy), Acrylic Resin (Acrylic Resin), cyclic olefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (polyethylimide), Fluorocarbon Polymer (Fluorocarbon Polymer), or an inorganic material, such as silicon gel (Silicone), Glass (Glass), or a dielectric material, such as aluminum oxide (Al)₂O₃) Silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or magnesium fluoride (MgF)_x)。

Following the third insulating layer forming step, the method for manufacturing the light emitting device 1 or the light emitting device 2 includes a pad forming step. As shown in the top view of fig. 8, a first bonding pad 80a and a second bonding pad 90a may be formed on the one or more semiconductor structures 1000a by plating, evaporation, or deposition, and then patterned by photolithography and etching. In the top view of fig. 8, the first pad 80a is near one side, e.g., the right side, of the centerline of the substrate 11a, and the second pad 90a is near the other side, e.g., the left side, of the centerline of the substrate 11 a. The first pad 80a covers all the first group of the third insulating layer openings 701a to contact the contact layer 60a, and is electrically connected to the first semiconductor layer 101a through the contact layer 60a and the hole portion 100 a. The second pad 90a covers all the second group of the third insulating layer openings 702a, contacts the reflective layer 40a or the barrier layer 41a, and is electrically connected to the second semiconductor layer 102a through the reflective layer 40a or the barrier layer 41 a. The first pad 80a has one or more first pad openings 800 a; and a first side 802a and a plurality of first recesses 804a extend from the first side 802a in a direction away from the second pad 90 a. The second pad 90a has one or more second pad openings 900 a; and a second side 902a and a plurality of second recesses 904a extend from the second side 902a in a direction away from the first pad 80 a. The positions of the first pad opening 800a and the second pad opening 900a substantially correspond to the position of the hole portion 100a, and the positions of the first concave portion 804a and the second concave portion 904a substantially correspond to the position of the hole portion 100 a. In other words, the first pad 80a and the second pad 90a do not cover any hole 100a, the first pad 80a and the second pad 90a are formed around the hole 100a, such that the first pad opening 800a or the second pad opening 900a includes a diameter greater than that of any hole 100a, and the first recess 804a or the second recess 904a includes a diameter greater than that of any hole 100 a. In an embodiment of the invention, the plurality of first recesses 804a are substantially aligned with the plurality of second recesses 904a in a top view. In another embodiment of the present invention, the plurality of first recesses 804a are offset from the plurality of second recesses 904a in a top view. In an embodiment of the invention, the shape of the first pad 80a is the same as or different from the shape of the second pad 90a in the top view of the light emitting device 1 or the light emitting device 2.

Fig. 9A is a sectional view taken along line a-a 'of fig. 8, and fig. 9B is a sectional view taken along line B-B' of fig. 8. The light emitting device 1 according to the present embodiment is a flip-chip light emitting diode device. The light-emitting element 1 includes a substrate 11 a; one or more semiconductor structures 1000a are located on the substrate 11 a; the surrounding portion 111a surrounds the one or more semiconductor structures 1000 a; and the first pad 80a and the second pad 90a are located on the semiconductor stack 10 a. The one or more semiconductor structures 1000a each comprise a semiconductor stack 10a, the semiconductor stack 10a comprising a first semiconductor layer 101a, a second semiconductor layer 102a, and an active layer 103a between the first semiconductor layer 101a and the second semiconductor layer 102 a. The plurality of semiconductor structures 1000a are connected to each other through the first semiconductor layer 101 a. As shown in fig. 8, fig. 9A and fig. 9B, the second semiconductor layer 102a and the active layer 103a around the one or more semiconductor structures 1000a are removed to expose the first surface 1011a of the first semiconductor layer 101a, in other words, the surrounding portion 111a includes the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000 a.

The light emitting device 1 further comprises one or more holes 100a through the second semiconductor layer 102a and the active layer 103a to expose one or more second surfaces 1012a of the first semiconductor layer 101 a; and a contact layer 60a formed on the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a and to contact the first semiconductor layer 101a for electrical connection, and formed on the one or more second surfaces 1012a of the first semiconductor layer 101a to cover the one or more holes 100a and to contact the first semiconductor layer 101a for electrical connection. In the present embodiment, in the top view of the light emitting element 1, the contact layer 60a includes a total surface area larger than a total surface area of the active layer 103a, or the contact layer 60a includes a peripheral side length larger than a peripheral side length of the active layer 103 a.

In an embodiment of the present invention, the first pad 80a and/or the second pad 90a covers the plurality of semiconductor structures 1000 a.

In one embodiment of the present invention, the first pad 80a has one or more first pad openings 800a, and the second pad 90a has one or more second pad openings 900 a. The formation positions of the first pad 80a and the second pad 90a are formed around the formation position of the hole portion 100a, so that the formation positions of the first pad opening 800a and the second pad opening 900a overlap the formation position of the hole portion 100 a.

In an embodiment of the invention, in a top view of the light emitting device 1, the shape of the first pad 80a is the same as that of the second pad 90a, for example, the first pad 80a and the second pad 90a are comb-shaped, as shown in fig. 8, a curvature radius of the first pad opening 800a of the first pad 80a and a curvature radius of the first recess 804a are respectively larger than a curvature radius of the hole 100a, so that the first pad 80a is formed in an area except for the positions of the holes 100 a. A radius of curvature of the second pad opening 900a and a radius of curvature of the second recess 904a of the second pad 90a are respectively greater than a radius of curvature of the hole 100a, so that the second pad 90a is formed in a region other than the positions of the holes 100 a.

In an embodiment of the invention, in a top view of the light emitting device 1, when the shape of the first pad 80a is different from the shape of the second pad 90a, for example, the shape of the first pad 80a is rectangular, and the shape of the second pad 90a is comb-shaped, the first pad 80a includes the first pad opening 800a so that the first pad 80a is formed in a region other than the plurality of holes 100a, and the second pad 90a includes the second recess 904a or both the second recess 904a and the second pad opening 900a so that the second pad 90a is formed in a region other than the plurality of holes 100 a.

In an embodiment of the invention, the size of the first pad 80a is different from the size of the second pad 90a, for example, the area of the first pad 80a is larger than the area of the second pad 90 a. The first bonding pad 80a and the second bonding pad 90a may be one or more layers of structures including a metal material. The material of the first and

second pads

80a and 90a includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy thereof. When the first bonding pad 80a and the second bonding pad 90a are multi-layered, the first bonding pad 80a includes a first upper layer bonding pad 805a and a first lower layer bonding pad 807a, and the second bonding pad 90a includes a second upper layer bonding pad 905a and a second lower layer bonding pad 907 a. The upper layer bonding pad and the lower layer bonding pad have different functions respectively. The function of the upper layer bonding pad is mainly used for welding and forming a lead. The light emitting element 1 can be mounted on a package substrate in a flip chip manner by upper layer bonding pads using solder or AuSn eutectic bonding. Specific metal materials of the upper pad include highly ductile materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os). The upper layer bonding pad can be a single layer, an alloy or a multilayer film of the above materials. In an embodiment of the present invention, the material of the upper layer bonding pad preferably comprises nickel (Ni) and/or gold (Au), and the upper layer bonding pad is a single layer or multiple layers. The lower pad functions to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, to increase the interface bonding strength between the first lower pad 807a and the contact layer 60a, or between the second lower pad 907a and the reflective layer 40a or the barrier layer 41 a. Another function of the lower bonding pad is to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure, destroying the reflectivity of the reflective structure. Therefore, the lower pad preferably includes a metal material other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), and may be a single layer, an alloy, or a multi-layer film of the above materials. In one embodiment of the present invention, the lower layer pad preferably includes a multilayer film of titanium (Ti), aluminum (Al), or chromium (Cr), aluminum (Al).

In an embodiment of the invention, in a cross-sectional view of the light emitting device 1, a portion of the contact layer 60a connected to the first semiconductor layer 101a is located below the second pad 90 a.

In an embodiment of the invention, in a cross-sectional view of the light emitting device 1, a portion of the contact layer 60a connected to the first semiconductor layer 101a is located above the reflective layer 40a and/or the barrier layer 41 a.

In an embodiment of the invention, in a top view of the light emitting device 1, the hole portion 100a includes a maximum width smaller than a maximum width of the first pad opening 800 a; and/or the aperture portion 100a includes a maximum width that is less than a maximum width of the second pad opening 900 a.

In an embodiment of the invention, in a top view of the light emitting device 1, the holes 100a are respectively located in the first recesses 804a of the first pad 80a and the second recesses 904a of the second pad 90 a.

Fig. 10 is a sectional view of the light emitting element 2 disclosed in an embodiment of the present invention. Compared with the light emitting device 1 in the above embodiment, the light emitting device 2 further includes a first buffer pad 810a and a second buffer pad 910a respectively located below the first pad 80a and the second pad 90a, except that the light emitting device 2 and the light emitting device 1 have substantially the same structure, so that the light emitting device 2 in fig. 10 and the light emitting device 1 in fig. 9A to 9B have the same name and label structure, show the same structure, have the same material, or have the same function, and description thereof will be omitted or repeated description thereof will be omitted. In the present embodiment, the light emitting device 2 includes a first pad 810a located between the first pad 80a and the semiconductor stack 10a, and a second pad 910a located between the second pad 90a and the semiconductor stack 10a, wherein the first pad 810a and the second pad 910a cover part or all of the hole 100 a; in the present embodiment, since the

pads

80a, 90a and the semiconductor stack 10a include multiple insulating layers, the stress generated when the

pads

80a, 90a of the light emitting device 2 are eutectic bonded with the solder or AuSn causes cracks to be generated between the

pads

80a, 90a and the insulating layers, so that the

pads

810a, 910a are respectively located between the

pads

80a, 90a and the third insulating layer 70a, the first pad 810a and the second pad 910a cover the whole hole 100a, the first pad 80a and the second pad 90a are formed at positions bypassing the hole 100a, and the stress generated between the pads and the insulating layers is reduced by selecting the material of the pads and reducing the thickness of the pads. In other words, the first and

second pads

80a and 90a do not cover the hole 100 a.

In an embodiment of the invention, as shown in fig. 10, in a top view of the light emitting element 2, the shape of the

cushion pads

810a, 910a is the same as the shape of the

pads

80a, 90a, for example, the shape of the first cushion pad 810a and the first pad 80a are comb-shaped.

In an embodiment of the invention, in a top view of the light emitting device 2 (not shown), the shape of the

pads

810a, 910a is different from the shape of the

pads

80a, 90a, for example, the shape of the first pad 810a is rectangular, and the shape of the first pad 80a is comb-shaped.

In another embodiment of the present invention, the size of the

cushions

810a, 910a is different from the size of the

pads

80a, 90a, for example, the area of the first cushion 810a is larger than the area of the first pad 80a, and the area of the second cushion 910a is larger than the area of the second pad 90 a.

In another embodiment of the present invention, a distance between the first pad 80a and the second pad 90a is greater than a distance between the first cushion 810a and the second cushion 910 a.

In another embodiment of the present invention, the

cushion pads

810a, 910a have a larger area than the

pads

80a, 90a to release the pressure of the

pads

80a, 90a during die bonding. In a cross-sectional view of the light emitting device 2, the first buffer pad 810a includes a width 1.5 to 2.5 times, preferably 2 times, the width of the first pad 80 a.

In another embodiment of the present invention, the

cushion pads

810a, 910a have a larger area than the

pads

80a, 90a to release the pressure of the

pads

80a, 90a during die bonding. In a cross-sectional view of the light emitting element 2, the first cushion pad 810a has an outward expansion distance of 1 time or more, preferably 2 times or more, of its own thickness.

In another embodiment of the present invention, the

bonding pads

80a, 90a have a thickness of 1-100 μm, preferably 2-6 μm, and the

cushion pads

810a, 910a have a thickness greater than 0.5 μm to release the pressure of the

bonding pads

80a, 90a during die bonding.

In another embodiment of the present invention, the first cushion 810a and the second cushion 910a may be one or more layers of structures including metal materials. The first pad 810a and the second pad 910a function to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, the first pad 810a contacts the contact layer 60a, and the second pad 910a contacts the reflective layer 40a or the barrier layer 41 a. The

buffer pads

810a, 910a preferably include a metal material other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os), to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the light emitting element.

In another embodiment of the present invention, the first buffer pad 810a and/or the second buffer pad 910a are a multi-layer structure comprising a metal material, wherein the multi-layer structure comprises a high ductility layer and a low ductility layer to prevent the stress generated when the

bonding pads

80a, 90a are eutectic bonded with the solder or AuSn from causing cracks in the insulating layer between the

bonding pads

80a, 90a and the semiconductor stack 10 a. The high ductility layer and the low ductility layer contain metals having different Young's coefficients (Young's modules).

In another embodiment of the present invention, the high ductility layer of the first and

second cushions

810a and 910a includes a thickness greater than or equal to a thickness of the low ductility layer.

In another embodiment of the present invention, the first buffer pad 810a and the second buffer pad 910a are a multi-layer structure containing metal material, and when the first pad 80a and the second pad 90a are a multi-layer structure containing metal material, the surface of the first buffer pad 810a contacting the first pad 80a contains the same metal material, and the surface of the second buffer pad 910a contacting the second pad 90a contains the same metal material, such as chromium (Cr), nickel (Ni), titanium (Ti), platinum (Pt), to improve the interface bonding strength between the pad and the buffer pad.

As shown in fig. 11A and 11B, a fourth insulating layer 110a may be formed on the first buffer pad 810a and the second buffer pad 910a by evaporation or deposition, and patterned by photolithography and etching, and the first pad 80a and the second pad 90a are formed on the first buffer pad 810a and the second buffer pad 910a respectively by the above-mentioned methods, wherein the fourth insulating layer 110a surrounds sidewalls of the first buffer pad 810a and the second buffer pad 910 a. The fourth insulating layer 110a may have a single-layer or multi-layer configuration. When it is fourthWhen the insulating layer 110a is a multilayer film, the fourth insulating layer 110a may include more than two materials having different refractive indexes alternately stacked to form a bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. The fourth insulating layer 110a is made of a non-conductive material and includes an organic material, such as Su8, benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Epoxy (Epoxy), Acrylic Resin (Acrylic Resin), cyclic olefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (Polyetherimide), Fluorocarbon Polymer (Fluorocarbon Polymer), or an inorganic material, such as silicon (Silicone), Glass (Glass), or a dielectric material, such as aluminum oxide (Al)₂O₃) Silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or magnesium fluoride (MgF)_x)。

In an embodiment of the invention, the manufacturing process of the first pads 80a and the second pads 90a may be directly continued after the manufacturing process of the first buffer pads 810a and the second buffer pads 910 a. In another embodiment of the present invention, after the manufacturing process of the first and

second buffer pads

810a and 910a, the forming process of the fourth insulating layer 110a is performed, and then the manufacturing process of the first and

second pads

80a and 90a is continued.

Fig. 12A to 22 illustrate a method for manufacturing a light emitting device 3 or a light emitting device 4 according to an embodiment of the present invention.

As shown in the top view of fig. 12A and the cross-sectional view of fig. 12B along line a-a' of fig. 12A, the method for manufacturing the light emitting device 3 or 4 includes a step of forming a platform, which includes providing a substrate 11B; and forming a semiconductor stack 10b on the substrate 11b, wherein the semiconductor stack 10b includes a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b between the first semiconductor layer 101b and the second semiconductor layer 102 b. The semiconductor stack 10b may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102b and the active layer 103b, thereby forming one or more semiconductor structures 1000 b; and a surrounding portion 111b surrounding the one or more semiconductor structures 1000 b. The surrounding portion 111b exposes a first surface 1011b of the first semiconductor layer 101 b. The one or more semiconductor structures 1000b each comprise a plurality of first outer sidewalls 1003b, a plurality of second outer sidewalls 1001b, and a plurality of inner sidewalls 1002b, wherein the first outer sidewalls 1003b are sidewalls of the first semiconductor layer 101b, the second outer sidewalls 1001b are sidewalls of the active layer 103b and/or the second semiconductor layer 102b, one end of the second outer sidewalls 1001b is connected to a surface 102s of the second semiconductor layer 102b, and the other end of the second outer sidewalls 1001b is connected to the first surface 1011b of the first semiconductor layer 101 b; one end of the inner sidewall 1002b is connected to the surface 102s of the second semiconductor layer 102b, and the other end of the inner sidewall 1002b is connected to the second surface 1012b of the first semiconductor layer 101 b; the plurality of semiconductor structures 1000b are connected to each other through the first semiconductor layer 101 b. As seen in fig. 12B, an obtuse angle is formed between the inner sidewall 1002B of the semiconductor structure 1000B and the second surface 1012B of the first semiconductor layer 101B, an obtuse angle or a right angle is formed between the first outer sidewall 1003B of the semiconductor structure 1000B and the surface 11s of the substrate 11B, and an obtuse angle is formed between the second outer sidewall 1001B of the semiconductor structure 1000B and the first surface 1011B of the first semiconductor layer 101B. The surrounding portion 111b surrounds the semiconductor structure 1000b, and the surrounding portion 111b is rectangular or polygonal in a top view of the light emitting device 3 or the light emitting device 4.

In an embodiment of the present invention, the light emitting device 3 or the light emitting device 4 includes a side length less than 30 mils. When an external current is injected into the light-emitting element 3 or the light-emitting element 4, the surrounding portion 111b surrounds the periphery of the semiconductor structure 1000b, so that the optical field distribution of the light-emitting element 3 or the light-emitting element 4 can be uniformized, and the forward voltage of the light-emitting element can be reduced.

In an embodiment of the present invention, the light emitting device 3 or the light emitting device 4 includes a side length greater than 30 mils. The semiconductor stack 10b may be patterned by photolithography and etching to remove portions of the second semiconductor layer 102b and the active layer 103b, and one or more holes 100b may be formed through the second semiconductor layer 102b and the active layer 103b, wherein the one or more holes 100b expose one or more second surfaces 1012b of the first semiconductor layer 101 b. When an external current is injected into light-emitting element 3 or light-emitting element 4, the light field distribution of light-emitting element 3 or light-emitting element 4 can be uniformized and the forward voltage of light-emitting element can be reduced by the distributed arrangement of surrounding portion 111b and plurality of holes 100 b.

In an embodiment of the invention, the opening shape of the one or more hole portions 100b includes a circle, an ellipse, a rectangle, a polygon, or an arbitrary shape. The plurality of hole portions 100b may be arranged in a plurality of rows, and the hole portions 100b in two adjacent rows may be aligned with or offset from each other.

In one embodiment of the present invention, the substrate 11b may be a growth substrate including a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP) or sapphire (Al) wafer for growing indium gallium nitride (InGaN)₂O₃) A wafer, a gallium nitride (GaN) wafer, or a silicon carbide (SiC) wafer. On the substrate 11b, a semiconductor stack 10b having electro-optical characteristics, such as a light-emitting (light-emitting) stack, may be formed by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), hydride vapor deposition (HVPE), evaporation, or ion plating.

In an embodiment of the invention, the first semiconductor layer 101b and the second semiconductor layer 102b are, for example, cladding layers (cladding layers) or confinement layers (confining layers), which have different conductivity types, electric properties, polarities, or may be doped with elements to provide electrons or holes, for example, the first semiconductor layer 101b is an n-type semiconductor, and the second semiconductor layer 102b is a p-type semiconductor. The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b, and electrons and holes are recombined in the active layer 103b under a current driving, so that electric energy is converted into light energy to emit light. The wavelength of light emitted from the light-emitting element 3 or the light-emitting element 4 is adjusted by changing the physical and chemical composition of one or more layers of the stacked semiconductor layers 10 b. The material of the semiconductor stack 10b comprises a group III-V semiconductor material, such as Al_xIn_yGa_(1-x-y)N or Al_xIn_yGa_(1-x-y)P, wherein 0 ≦ x, y ≦ 1; (x + y) ≦ 1. Depending on the material of the active layer 103b, when the semiconductor stack 10b is made of AlInGaP series material, it can emit red light with a wavelength between 610nm and 650nm, green light with a wavelength between 530nm and 570nm, and when the semiconductor stack 10b is made of AlInGaP series materialThe material is InGaN series material, which can emit blue light with a wavelength between 450nm and 490nm, or AlGaN series material, which can emit ultraviolet light with a wavelength between 400nm and 250 nm. The active layer 103b may be a Single Heterostructure (SH), a Double Heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MQW). The material of the active layer 103b may be a neutral, p-type or n-type conductivity semiconductor.

Following the step of forming the mesa, as shown in the top view of fig. 13A and the cross-sectional view along line a-a' of fig. 13A in fig. 13B, the method of fabricating the light emitting device 3 or 4 includes a step of forming a first insulating layer. A first insulating layer 20b may be formed on the semiconductor structure 1000b by evaporation or deposition, and patterned by photolithography and etching to cover the first surface 1011b of the surrounding portion 111b and the second surface 1012b of the hole portion 100b, and to cover the second semiconductor layer 102b of the semiconductor structure 1000b, the second outer sidewall 1001b of the active layer 103b, and the inner sidewall 1002b, wherein the first insulating layer 20b includes a first insulating layer surrounding region 200b to cover the surrounding portion 111b, such that the first surface 1011b of the first semiconductor layer 101b at the surrounding portion 111b is covered by the first insulating layer surrounding region 200 b; a first group of first insulation layer covering regions 201b for covering the hole 100b, such that the second surface 1012b of the first semiconductor layer 101b in the hole 100b is covered by the first group of first insulation layer covering regions 201 b; and a second group of first insulating layer openings 202b to expose the surface 102s of the second semiconductor layer 102 b. The first insulating layer covering regions 201b of the first group are separated from each other and respectively correspond to the plurality of hole portions 100 b. The first insulating layer 20b may be of a single-layer or multi-layer construction. When the first insulating layer 20b is a single layer film, the first insulating layer 20b can protect the sidewalls of the semiconductor structure 1000b to prevent the active layer 103b from being damaged by the subsequent manufacturing process. When the first insulating layer 20b is a multilayer film, the first insulating layer 20b may include more than two materials having different refractive indexes alternately stacked to form a bragg reflector (DBR) structure selectively reflecting light of a specific wavelength. First insulationThe layer 20b is made of a non-conductive material, and includes an organic material, such as Su8, benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Epoxy (Epoxy), Acrylic (Acrylic Resin), cyclic olefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (Polyetherimide), Fluorocarbon Polymer (Fluorocarbon Polymer), or an inorganic material, such as silicon (Silicone), Glass (Glass), or a dielectric material, such as aluminum oxide (Al) oxide₂O₃) Silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or magnesium fluoride (MgF)_x)。

In an embodiment of the invention, following the first insulating layer forming step, as shown in the top view of fig. 14A and the cross-sectional view along the line a-a' of fig. 14B, the method for manufacturing the light emitting device 3 or 4 includes a transparent conductive layer forming step. A transparent conductive layer 30b may be formed on the semiconductor structure 1000b by evaporation or deposition, and is in contact with the second semiconductor layer 102, wherein the transparent conductive layer 30b does not cover the hole 100 b. The transparent conductive layer 30b is formed substantially over the entire surface of the second semiconductor layer 102b in a top view of the light-emitting element 3 or the light-emitting element 4. Specifically, the transparent conductive layer 30b may be formed in the first insulating layer openings 202b of the second group by evaporation or deposition, wherein an outer edge 301b of the transparent conductive layer 30b is spaced apart from the first insulating layer 20b to expose the surface 102s of the second semiconductor layer 102 b. The transparent conductive layer 30b includes one or more transparent conductive layer openings 300b corresponding to the one or more hole portions 100b, respectively, and/or corresponding to the first insulating layer covering regions 201b of the first group, respectively, wherein an outer edge 301b of the transparent conductive layer opening 300b is spaced apart from an inner sidewall 1002b of the semiconductor structure 1000b and/or an outer edge of the hole portion 100b, and an outer edge of the transparent conductive layer opening 300b surrounds the outer edge of the hole portion 100b or surrounds the first insulating layer covering region 201b of the first group. The material of the transparent conductive layer 30b includes a material transparent to light emitted from the active layer 103b, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In an embodiment of the invention, following the transparent conductive layer forming step, as shown in the top view of fig. 15A and the cross-sectional view along the line a-a' of fig. 15B, the method for manufacturing the light emitting device 3 or the light emitting device 4 includes a reflective structure forming step. The reflective structure includes a reflective layer 40b and/or a barrier layer 41b, which can be directly formed on the transparent conductive layer 30b by evaporation or deposition, wherein the reflective layer 40b is located between the transparent conductive layer 30b and the barrier layer 41 b. The reflective layer 40b and/or the barrier layer 41b are formed substantially over the entire surface of the second semiconductor layer 102b in a top view of the light-emitting element 3 or the light-emitting element 4. The outer edge 401b of the reflective layer 40b can be disposed inside, outside, or in coincident alignment with the outer edge 301b of the transparent conductive layer 30b, and the outer edge 411b of the barrier layer 41b can be disposed inside, outside, or in coincident alignment with the outer edge 401b of the reflective layer 40 b. The reflective layer 40b includes one or more reflective layer openings 400b corresponding to the one or more apertures 100b, respectively, and the barrier layer 41b includes one or more barrier layer openings 410b corresponding to the one or more apertures 100b, respectively. The transparent conductive layer opening 300b, the reflective layer opening 400b, and the barrier layer opening 410b overlap each other. The outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b are spaced apart from the outer edge of the hole 100b, and the outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b surround the outer edge of the hole 100 b.

In another embodiment of the present invention, the formation of the transparent conductive layer can be omitted, and after the mesa formation step or the first insulating layer formation step, the reflective structure formation step is performed directly, for example, the reflective layer 40b and/or the barrier layer 41b are formed directly on the second semiconductor layer 102b, and the reflective layer 40b is located between the second semiconductor layer 102b and the barrier layer 41 b. The reflective layer 40b may be one or more layers, such as a bragg reflector. The material of the reflective layer 40b includes a metal material having a high reflectance, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy of the above materials. The term "have a high reflectance" as used herein means that the reflectance is 80% or more with respect to the wavelength of light emitted from the light emitting element 3. In an embodiment of the present invention, the barrier layer 41b covers the reflective layer 40b to prevent the surface of the reflective layer 40b from being oxidized to deteriorate the reflectivity of the reflective layer 40 b. The material of the barrier layer 41b includes a metal material, for example, a metal such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt), or an alloy of the above materials. The barrier layer 41b may have one or more layers, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W). In one embodiment of the present invention, the barrier layer 41b includes a titanium (Ti)/aluminum (Al) stack structure on a side close to the reflective layer 40b, and a titanium (Ti)/tungsten (W) stack structure on a side far from the reflective layer 40 b. In an embodiment of the present invention, the materials of the reflective layer 40b and the barrier layer 41b preferably include a metal material other than gold (Au) or copper (Cu).

In an embodiment of the invention, following the step of forming the reflective structure, as shown in the top view of fig. 16A and the cross-sectional view of fig. 16B along the line a-a' of fig. 16A, the method of manufacturing the light emitting device 3 or 4 includes a step of forming a second insulating layer. A second insulating layer 50b may be formed on the semiconductor stacked layer 10b by evaporation or deposition, and patterned by photolithography and etching to form a first group of second insulating layer openings 501b to expose the first semiconductor layer 101b and a second group of second insulating layer openings 502b to expose the reflective layer 40b or the barrier layer 41b, wherein in the process of patterning the second insulating layer 50b, the first group of first insulating layer covering regions 200b of the surrounding portion 111b and the hole portion 100b in the first insulating layer forming step are etched and removed to expose the first semiconductor layer 101b, and the first group of first insulating layer openings 203b are formed on the hole portion 100b to expose the first semiconductor layer 101 b. In an embodiment of the invention, as shown in fig. 16A, the first group of second insulating layer openings 501b are separated from each other and respectively correspond to the plurality of hole portions 100b, and the second group of second insulating layer openings 502b are all close to the substrateOne side of the plate 11b, for example, the left side or the right side of the center line of the substrate 11b, in one embodiment, the number of the second group of the second insulating layer openings 502b includes one or more, in this embodiment, the second group of the second insulating layer openings 502b are connected to form a ring-shaped opening 5020b, and the ring-shaped opening 5020b may be comb-shaped, rectangular, oval, circular, or polygonal in a top view of the light emitting device 3. In an embodiment of the present invention, the second insulating layer 50b may have a single-layer or multi-layer structure. When the second insulating layer 50b is a multilayer film, the second insulating layer 50b may include more than two materials having different refractive indexes alternately stacked to form a bragg reflector (DBR) structure selectively reflecting light of a specific wavelength. The second insulating layer 50b is made of a non-conductive material, and includes an organic material, such as Su8, benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Epoxy (Epoxy), Acrylic Resin (Acrylic Resin), cyclic olefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (polyethylimide), Fluorocarbon Polymer (Fluorocarbon Polymer), or an inorganic material, such as silicon gel (Silicone), Glass (Glass), or a dielectric material, such as aluminum oxide (Al)₂O₃) Silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or magnesium fluoride (MgF)_x)。

Following the second insulating layer forming step, in an embodiment of the present invention, as shown in the top view of fig. 17A and the cross-sectional view of fig. 17B, the method for manufacturing the light emitting device 3 or the light emitting device 4 includes a contact layer forming step. A contact layer 60b may be deposited or evaporated on the semiconductor stack 10b, and then patterned by photolithography and etching to form a first contact layer 601b and a second contact layer 602 b. The first contact layer 601b covers all the second insulating layer openings 501b of the first group, fills in the one or more holes 100b to contact the first semiconductor layer 101b, and extends over the second insulating layer 50b and the second semiconductor layer 102b, wherein the first contact layer 601b is insulated from the second semiconductor layer 102b by the second insulating layer 50 b. The second contact layer 602b is formed in the annular opening 5020b of the second insulating layer 50b to contact the reflective layer 40b and/or the barrier layer 41b, wherein the sidewall 6021b of the second contact layer 602b is spaced apart from the sidewall 5021b of the annular opening 5020b by a distance. The sidewall 6011b of the first contact layer 601b is separated from the sidewall 6021b of the second contact layer 602b by a distance such that the first contact layer 601b is not connected to the second contact layer 602b and the first contact layer 601b is electrically isolated from the second contact layer 602b by a portion of the second insulating layer 50 b. In the top view, the first contact layer 601b covers the surrounding portion 111b of the stack of semiconductor layers 10b, so that the first contact layer 601b surrounds the second contact layer 602 b. In the top view of fig. 17A, the second contact layer 602b is close to one side of the substrate 11b, for example, the left or right side of the center line of the substrate 11 b. The contact layer 60b defines a pin region 600b at a geometric center of the stack of semiconductor layers 10 b. The thimble region 600b is not contiguous with the first contact layer 601b and the second contact layer 602b and is electrically isolated from each other, and the thimble region 600b comprises the same material as the first contact layer 601b and/or the second contact layer 602 b. The tip region 600b serves as a structure for protecting the epitaxial layer from being damaged by the probe in the subsequent manufacturing processes of the epitaxial layer, such as die separation, die testing, and packaging. The contact layer 60b may be a one or more layer structure. In order to reduce the resistance In contact with the first semiconductor layer 101b, the material of the contact layer 60b includes a metal material, for example, chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. In an embodiment of the present invention, the material of the contact layer 60b preferably includes a metal material other than gold (Au) or copper (Cu). In an embodiment of the present invention, the material of the contact layer 60b preferably contains a metal with high reflectivity, such as aluminum (Al), platinum (Pt). In an embodiment of the present invention, a side of the contact layer 60b contacting the first semiconductor layer 101b preferably includes chromium (Cr) or titanium (Ti) to increase bonding strength with the first semiconductor layer 101 b.

In an embodiment of the invention, following the contact layer forming step shown in fig. 17A and 17B, the method for manufacturing the light emitting element 3 or 4 includes a third insulating layer forming step, as shown in the top view of fig. 18A and the cross-sectional view of fig. 18B along the line a-a' of fig. 18A, of forming a third insulating layerThe layer 70b may be formed on the semiconductor stacked layer 10b by evaporation or deposition, and patterned by photolithography and etching, so as to form a third insulating layer opening 701b on the first contact layer 601b to expose the first contact layer 601b shown in fig. 17A, and form another third insulating layer opening 702b on the second contact layer 602b to expose the second contact layer 602b shown in fig. 17A, wherein a portion of the first contact layer 601b on the second semiconductor layer 102b is sandwiched between the second insulating layer 50b and the third insulating layer 70 b. In the present embodiment, as shown in fig. 18A, the third insulating layer opening 701b and the another third insulating layer opening 702b bypass one or more hole portions 100 b. In the present embodiment, the third insulating layer opening 701b and/or the another third insulating layer opening 702b is an annular opening, which may be comb-shaped, rectangular, oval, circular, or polygonal in a top view. In the top view of fig. 18A, a third insulating layer opening 701b is close to one side, for example, the right side, of the center line of the substrate 11b, and another third insulating layer opening 702b is close to the other side, for example, the left side, of the center line of the substrate 11 b. In the cross-sectional view, the third insulating layer opening 701b includes a width greater than that of another third insulating layer opening 702 b. The third insulating layer 70b may be of a single-layer or multi-layer construction. When the third insulating layer 70b is a multilayer film, the third insulating layer 70b may include more than two materials having different refractive indexes alternately stacked to form a bragg reflector (DBR) structure selectively reflecting light of a specific wavelength. The third insulating layer 70b is made of a non-conductive material, and includes an organic material, such as Su8, benzocyclobutene (BCB), Perfluorocyclobutane (PFCB), Epoxy (Epoxy), Acrylic Resin (Acrylic Resin), cyclic olefin Polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide (polyethylimide), Fluorocarbon Polymer (Fluorocarbon Polymer), or an inorganic material, such as silicon gel (Silicone), Glass (Glass), or a dielectric material, such as aluminum oxide (Al)₂O₃) Silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Titanium oxide (TiO)_x) Or magnesium fluoride (MgF)_x)。

Following the third insulating layer forming step, the method for manufacturing the light emitting device 3 or the light emitting device 4 includes a pad forming step. As shown in the top view of fig. 19, a first bonding pad 80b and a second bonding pad 90b may be formed on the semiconductor stack 10b by plating, evaporation, or deposition, and then patterned by photolithography and etching. In the top view of fig. 19, the first pad 80b is close to one side, e.g., the right side, of the center line of the substrate 11b, and the second pad 90b is close to the other side, e.g., the left side, of the center line of the substrate 11 b. The first pad 80b contacts the first contact layer 601b through the third insulating layer opening 701b, and forms an electrical connection with the first semiconductor layer 101b through the first contact layer 601 b. The second pad 90b contacts the reflective layer 40b and/or the barrier layer 41b through another third insulating layer opening 702b, and is electrically connected to the second semiconductor layer 102b through the reflective layer 40b and/or the barrier layer 41 b. The first pad 80b has a plurality of first protrusions 801b and a plurality of first recesses 802b alternately connected to each other. The second pad 90b has a plurality of second protrusions 901b and a plurality of second recesses 902b alternately connected to each other. The positions of the first concave portion 802b of the first pad 80b and the second concave portion 902b of the second pad 90b substantially correspond to the positions of the hole portions 100 b. In other words, the first pad 801b and the second pad 802b do not cover any hole 100b, and the first concave portion 802b of the first pad 80b and the second concave portion 902b of the second pad 90b bypass the hole 100b and are formed around the hole 100b, so that the width of the first concave portion 802b of the first pad 80b or the width of the second concave portion 902b of the second pad 90b is greater than the diameter of any hole 100 b. In an embodiment of the present invention, the plurality of first recesses 802b are substantially aligned with the plurality of second recesses 902b in a top view. In another embodiment of the present invention, the plurality of first recesses 802b are offset from the plurality of second recesses 902b in a top view.

In an embodiment of the invention, as shown in fig. 19, the first bonding pad 80b covers the third insulating layer opening 701b, and the second bonding pad 90b covers another third insulating layer opening 702b, since the third insulating layer opening 701b includes a maximum width greater than that of another third insulating layer opening 702b, the first bonding pad 80b includes a maximum width greater than that of the second bonding pad 90 b. The first pads 80b and the second pads 90b with different sizes can facilitate the identification of the electrical property corresponding to the connection of the pads during the package soldering process, thereby avoiding the occurrence of soldering to the wrong electrical pad.

In an embodiment of the invention, the third insulating layer opening 701b includes an area larger or smaller than an area of the first pad 80b in a top view of the light emitting device.

In another embodiment of the present invention, the shortest distance between the first convex portion 801b and the second convex portion 901b is smaller than the largest distance between the first concave portion 802b and the second concave portion 902 b.

In another embodiment of the present invention, the first pad 80b includes a first flat edge 803b opposite to the first protrusion 801b and the first recess 802b, and the second pad 90b includes a second flat edge 903b opposite to the second protrusion 901b and the second recess 902 b. A maximum distance between the first flat edge 803b of the first pad 80b and the first protrusion 801b is greater than a minimum distance between the first protrusion 801b and the second protrusion 901 b. A maximum distance between the second flat side 903b of the second pad 90b and the second protrusion 901b is greater than a minimum distance between the first protrusion 801b and the second protrusion 901 b.

In another embodiment of the present invention, one of the first recesses 802b of the first pad 80b includes a radius of curvature different from a radius of curvature included in one of the first protrusions 801b of the first pad 80b, for example, one of the first recesses 802b of the first pad 80b includes a radius of curvature greater than or less than a radius of curvature included in one of the first protrusions 801b of the first pad 80 b. In another embodiment of the present invention, one of the second concave portions 902b of the second pad 90b includes a radius of curvature greater than or less than a radius of curvature included in one of the second convex portions 901b of the second pad 90 b.

In another embodiment of the present invention, one of the first convex portions 801b of the first pad 80b has a radius of curvature greater than or less than a radius of curvature of one of the second convex portions 901b of the second pad 90 b.

In another embodiment of the present invention, the plurality of first recesses 802b of the first pad 80b are opposite to the plurality of second recesses 902b of the second pad 90b, and one of the plurality of first recesses 802b has a radius of curvature greater than or less than a radius of curvature of one of the plurality of second recesses 902 b.

In another embodiment of the present invention, the shape of the first pad 80b is different from the shape of the second pad 90b, for example, the shape of the first pad 80b is rectangular, and the shape of the second pad 90b is comb-shaped.

In another embodiment of the present invention, the size of the first pad 80b is different from the size of the second pad 90b, for example, the area of the first pad 80b is larger than the area of the second pad 90 b.

Fig. 20 is a cross-sectional view taken along a-a' of fig. 19. The light emitting device 3 according to the present embodiment is a flip-chip light emitting diode device. The light-emitting device 3 includes a substrate 11 b; one or more semiconductor structures 1000b are disposed on the substrate 11b, wherein the semiconductor structure 1000b comprises a semiconductor stack 10, the semiconductor stack 101l comprises a first semiconductor layer 101b, a second semiconductor layer 102b, and an active layer 103b disposed between the first semiconductor layer 101b and the second semiconductor layer 102b, and the plurality of semiconductor structures 1000b are connected to each other through the first semiconductor layer 101 b; a surrounding portion 111b surrounding the one or more semiconductor structures 1000b, wherein the surrounding portion 111b exposes a first surface 1011b of the first semiconductor layer 101 b; and a first pad 80b and a second pad 90b are located on the one or more semiconductor structures 1000 b. As shown in fig. 19 and 20, each of the one or more semiconductor structures 1000b includes a plurality of outer sidewalls 1001b and a plurality of inner sidewalls 1002b, wherein one end of the outer sidewall 1001b is connected to a surface 102s of the second semiconductor layer 102b, and the other end of the outer sidewall 1001b is connected to the first surface 1011b of the first semiconductor layer 101 b; one end of the inner sidewall 1002b is connected to the surface 102s of the second semiconductor layer 102b, and the other end of the inner sidewall 1002b is connected to the second surface 1012b of the first semiconductor layer 101 b.

In an embodiment of the invention, when the light emitting device 3 includes a side length greater than 30mil, the light emitting device 3 further includes one or more holes 100b passing through the second semiconductor layer 102b and the active layer 103b to expose one or more second surfaces 1012b of the first semiconductor layer 101 b; and a contact layer 60b disposed on a first surface 1011b of the first semiconductor layer 101b to surround the one or more semiconductor structures 1000b and contact the first semiconductor layer 101b to form an electrical connection, and formed on one or more second surfaces 1012b of the first semiconductor layer 101b to cover the one or more holes 100b and contact the first semiconductor layer 101b to form an electrical connection, wherein the contact layer 60b includes a first contact layer 601b and a second contact layer 602b, the first contact layer 601b is disposed on the second semiconductor layer, surrounds a sidewall of the second semiconductor layer, and is connected to the first semiconductor layer, the second contact layer is disposed on the second semiconductor layer and is connected to the second semiconductor layer, the second contact layer 602b is surrounded by the first contact layer 601b, and the first contact layer 601b and the second contact layer 602b are not overlapped with each other.

In an embodiment of the invention, when the light emitting element 3 includes a side less than 30mil, the light emitting element 3 may not include any hole portion 100b in order to obtain a larger light emitting area.

In an embodiment of the present invention, the total surface area of the contact layer 60b is larger than the total surface area of the active layer 103b in the top view of the light emitting element 3.

In an embodiment of the present invention, the total side length of the periphery of the contact layer 60b is larger than the total side length of the periphery of the active layer 103b in the top view of the light emitting element 3.

In an embodiment of the invention, the first contact layer 601b includes an area larger than an area of the second contact layer 602b in a top view of the light emitting device 3.

In an embodiment of the invention, the first pad 80b and the second pad 90b are formed at positions around the opening 100b, so that any opening 100b is not covered by the first pad 80b or the second pad 90 b.

In an embodiment of the invention, in a cross-sectional view of the light emitting device 3, the first contact layer 601b connected to the first semiconductor layer 101b is not located below the second pad 90 b.

In one embodiment of the present invention, the minimum distance between the first pad 80b and the second pad 90b is greater than 50 μm.

In an embodiment of the present invention, the distance between the first pad 80b and the second pad 90b is less than 300 μm.

In one embodiment of the present invention, the first bonding pad 80b and the second bonding pad 90b may be one or more layers including a metal material. The material of the first and

second pads

80b and 90b includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy thereof. When the first pads 80b and the second pads 90b are multi-layered, the first pads 80b include first lower pads (not shown) and first upper pads (not shown), and the second pads 90b include second lower pads (not shown) and second upper pads (not shown). The upper layer bonding pad and the lower layer bonding pad have different functions respectively. The function of the upper layer pad is mainly for soldering and forming a lead, and the light emitting element 3 can be mounted on a mounting substrate in a flip chip manner by using solder or AuSn eutectic bonding through the upper layer pad. Specific metal materials of the upper pad include highly ductile materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os). The upper layer bonding pad can be a single layer, an alloy or a multilayer film of the above materials. In an embodiment of the present invention, the material of the upper layer bonding pad preferably comprises nickel (Ni) and/or gold (Au), and the upper layer bonding pad is a single layer or multiple layers. The function of the lower layer pad forms a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b, for example, the bonding strength of the interface of the first lower layer pad with the contact layer 60b is improved, or the bonding strength of the interface of the second lower layer pad with the reflective layer 40b and/or the barrier layer 41b is improved. Another function of the lower bonding pad is to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure, destroying the reflectivity of the reflective structure. Therefore, the lower pad preferably includes a metal material other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), and may be a single layer, an alloy, or a multi-layer film of the above materials. In one embodiment of the present invention, the lower layer pad preferably includes a multilayer film of titanium (Ti), aluminum (Al), or chromium (Cr), aluminum (Al).

In an embodiment of the invention, when the light emitting element 3 is flip-chip mounted on the package substrate by the solder, the first pad 80b and the second pad 90b may have a height difference H therebetween. As shown in fig. 20, since the second insulating layer 50b under the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second pad 90b includes the second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41b, when the first pad 80b and the second pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the topmost surface 80s of the first pad 80b is higher than the topmost surface 90s of the second pad 90b than the topmost surface 80s of the first pad 80 b. In other words, a height difference H exists between the topmost surface 80s of the first pad 80b and the topmost surface 90s of the second pad 90b, and the height difference H between the first pad 80b and the second pad 90b is substantially the same as the thickness of the second insulating layer 50 b. In one embodiment, the height difference between the first pad 80b and the second pad 90b may be between 0.5 μm and 2.5 μm, such as 1.5 μm. When the first pad 80b and the second pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the first pad 80b passes through the third insulating layer opening 701b to contact the first contact layer 601b, and extends from the third insulating layer opening 701b to cover a portion of the surface of the third insulating layer 70b, and the second pad 90b passes through the other third insulating layer opening 702b to contact the second contact layer 602b, and extends from the other third insulating layer opening 702b to cover a portion of the surface of the third insulating layer 70 b.

Fig. 21 is a top view of the light emitting element 4 disclosed in an embodiment of the present invention. Fig. 22 is a sectional view of the light emitting element 4 disclosed in one embodiment of the present invention. Compared with the light emitting device 3 in the above embodiment, the light emitting device 4 has substantially the same structure as the light emitting device 3 except that the structure of the first bonding pad and the second bonding pad are different, and the light emitting device 4 and the light emitting device 3 having the same reference numerals are not described herein again. When the light emitting element 4 is mounted on the package substrate in a flip chip manner by AuSn eutectic bonding, the smaller the height difference between the first and

second pads

80b and 90b is, the better to increase the stability between the pads and the package substrate. As shown in fig. 22, the second insulating layer 50b under the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41 b. In the present embodiment, in order to reduce the height difference between the topmost surface 80s of the first pad 80b and the topmost surface 90s of the second pad 90b, the third insulating layer opening 701b includes a width greater than that of another third insulating layer opening 702 b. When the first pad 80b and the second pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the whole of the first pad 80b is formed in the third insulating layer opening 701b to contact the first contact layer 601b, the second pad 90b is formed in the other third insulating layer opening 702b to contact the reflective layer 40b and/or the barrier layer 41b, and the second pad 90b extends from the third insulating layer opening 702b to cover a portion of the surface of the third insulating layer 70 b. In other words, the third insulating layer is not formed under the first pad 80b, but a portion of the third insulating layer is formed under the second pad 90 b. In the present embodiment, the height difference between the first pad 80b and the second pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm.

Fig. 23 is a sectional view of the light emitting element 5 disclosed in one embodiment of the present invention. Compared with the light emitting elements 3 and 4 in the above embodiments, the light emitting element 5 has substantially the same structure as the light emitting elements 3 and 4 except for the structure of the second bonding pad, and the elements with the same reference numerals as the light emitting elements 3 and 4 in the light emitting element 5 are not described herein again. When the light emitting element 5 is mounted on the package substrate in a flip chip manner by AuSn eutectic bonding, the smaller the height difference between the first and

second pads

80b and 90b is, the better to increase the stability between the pads and the package substrate. As described above, in addition to forming a portion of the third insulating layer under the second pad 90b, a second buffer 910b may be formed under the second pad 90b to reduce the height difference between the top surface of the first pad 80b and the top surface of the second pad 90 b. As shown in fig. 23, the second insulating layer 50b under the first pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second pad 90b includes a second insulating layer opening 502b to expose the reflective layer 40b or the barrier layer 41 b. In the present embodiment, the whole of the first pad 80b is formed in the third insulating layer opening 701b to contact the first contact layer 601b, and the whole of the second pad 90b is formed in the other third insulating layer opening 702b to contact the second contact layer 602b, in other words, the third insulating layer is not formed under the first pad 80b and under the second pad 90 b. In the present embodiment, the height difference between the top surface of the first pad 80b and the top surface of the second pad 90b is reduced by the second buffer pad 910b located between the second pad 90b and the second contact layer 602b, wherein the second buffer pad 910b preferably comprises a metal material other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os), so as to prevent tin (Sn) in AuSn eutectic from diffusing into the light emitting element 5. In the present embodiment, the height difference between the top surface of the first pad 80b and the top surface of the second pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm. In the present embodiment, the second cushion 910b includes a thickness substantially the same as the thickness of the second insulating layer 50 b.

Fig. 24 is a sectional view of the light emitting element 6 disclosed in an embodiment of the present invention. Compared with the light emitting elements 3 and 4 in the above embodiments, the light emitting element 6 has substantially the same structure as the light emitting elements 3 and 4 except that the structure of the third insulating layer 70b under the first bonding pad 80b is different, and the light emitting elements 6, the light emitting elements 3 and 4 having the same reference numerals are not repeated herein. As shown in fig. 24, the third insulating layer 70b may be formed on the semiconductor stacked layer 10b by evaporation or deposition, and then patterned by photolithography and etching, so as to form a third insulating layer opening 701b on the first contact layer 601b to expose the first contact layer 601b, and form another third insulating layer opening 702b on the second contact layer 602b to expose the second contact layer 602 b. The first bonding pad 80b and the second bonding pad 90b may be formed on the semiconductor stack 10b by plating, evaporation, deposition, or the like, and then patterned by photolithography and etching. The first pad 80b contacts the first contact layer 601b through the third insulating layer opening 701b, and forms an electrical connection with the first semiconductor layer 101b through the first contact layer 601 b. In order to avoid that the first contact layer 601b and the second insulating layer 50b under the first pad 80b are excessively etched and removed to expose the reflective layer 40b and/or the barrier layer 41b when the third insulating layer 70b is etched in the etching process for forming the third insulating layer opening 701b, the area of the third insulating layer 70b under the first pad 80b that is etched to form the third insulating layer opening 701b is reduced, a first portion of the third insulating layer 70b is remained between the first pad 80b and the first contact layer 601b and is completely covered by the first pad 80b, another second portion of the third insulating layer 70b is remained around the first pad 80b, and a gap between the first portion and the second portion of the third insulating layer 70b constitutes the third insulating layer opening 701 b. Specifically, the first portion of the third insulating layer 70b completely covered by the first pad 80b includes a width greater than that of the third insulating layer opening 701b under the pad 80 b. In the present embodiment, the third insulating layer opening 701b is an annular opening in a top view of the light emitting device.

Fig. 25 is a schematic view of a light-emitting device according to an embodiment of the invention. The semiconductor light emitting element 1, the light emitting element 2, the light emitting element 3, the light emitting element 4, the light emitting element 5, or the light emitting element 6 in the foregoing embodiments is flip-chip mounted on the first pad 511 and the second pad 512 of the package substrate 51. The first pad 511 and the second pad 512 are electrically insulated by an insulating portion 53 made of an insulating material. Flip chip mounting is performed by setting one side of the

growth substrates

11a and 11b facing the electrode formation surface as a main light extraction surface. In order to increase the light extraction efficiency of the light emitting device, a reflective structure 54 may be disposed around the semiconductor light emitting element 1, the light emitting element 2, the light emitting element 3, the light emitting element 4, the light emitting element 5, or the light emitting element 6.

Fig. 26 is a schematic view of a light-emitting device according to an embodiment of the invention. A bulb lamp 600 includes a lamp housing 602, a reflector 604, a light emitting module 610, a lamp base 612, a heat sink 614, a connecting portion 616 and an electrical connecting element 618. The light emitting module 610 includes a supporting portion 606, and a plurality of light emitting devices 608 located on the supporting portion 606, wherein the plurality of light emitting devices 608 may be the semiconductor light emitting device 1, the light emitting device 2, the light emitting device 3, the light emitting device 4, the light emitting device 5, or the light emitting device 6 in the foregoing embodiments.

The examples are given solely for the purpose of illustration and are not intended to limit the scope of the invention. Any obvious modifications or variations can be made to the present invention without departing from the spirit or scope of the present invention.

Claims

1. A light-emitting element, comprising:

a substrate having a centerline;

a semiconductor structure on the substrate, the semiconductor structure having a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer;

a surrounding portion surrounding the semiconductor structure and exposing the first semiconductor layer of the semiconductor structure;

a first contact layer on the surrounding portion;

a second contact layer on the second semiconductor layer of the semiconductor structure, wherein the first contact layer and the second contact layer do not overlap with each other;

a first bonding pad located on the semiconductor structure and contacting the first contact layer to form an electrical connection with the first semiconductor layer; and

and a second bonding pad on the semiconductor structure to contact the second contact layer and electrically connected with the second semiconductor layer, wherein the first bonding pad is arranged on one side of the center line of the substrate, the second bonding pad is arranged on the other side of the center line of the substrate, the light-emitting element has a side length less than 30mil, and the minimum distance between the first bonding pad and the second bonding pad is less than 300 μm.

2. The light-emitting device according to claim 1, wherein a portion of the first contact layer located over the second semiconductor layer surrounds the second contact layer in the top view of the light-emitting device.

3. The light emitting device of claim 1, wherein the first contact layer is connected to the first semiconductor layer, the first contact layer not being under the second pad.

4. The light-emitting device according to claim 1, further comprising a reflective layer and/or a barrier layer between the second semiconductor layer and the second contact layer.

5. The light-emitting device according to claim 1, further comprising a second insulating layer on the first semiconductor layer and the second semiconductor layer, wherein the second insulating layer comprises a second insulating layer opening on the first semiconductor layer and another second insulating layer opening on the second semiconductor layer.

6. The light emitting device of claim 1 or 5, further comprising a third insulating layer comprising a Bragg reflector (DBR) structure, the third insulating layer comprising a third insulating layer opening to expose the first contact layer and another third insulating layer opening to expose the second contact layer, wherein the first pad covers the third insulating layer opening and the second pad covers the another third insulating layer opening.

7. The light-emitting element according to claim 1, wherein a side of the first contact layer which is in contact with the first semiconductor layer contains chromium (Cr) or titanium (Ti).

8. A light-emitting element, comprising:

a substrate having a centerline;

a transparent conductive layer on the second semiconductor layer;

a first insulating layer covering the semiconductor structure and the surrounding portion, wherein the first insulating layer comprises a first insulating layer opening located on the surrounding portion and another first insulating layer opening located on the second semiconductor layer;

a first bonding pad located on the semiconductor structure and electrically connected to the first semiconductor layer; and

and a second bonding pad on the semiconductor structure and electrically connected with the second semiconductor layer, wherein the first bonding pad is arranged on one side of the center line of the substrate, the second bonding pad is arranged on the other side of the center line of the substrate, the light-emitting element comprises a side length less than 30mil, and the minimum distance between the first bonding pad and the second bonding pad is less than 300 μm.

9. The light-emitting device according to claim 1 or 8, wherein a first outer sidewall of the first semiconductor layer has a right angle with a surface of the substrate, and a second outer sidewall of the second semiconductor layer has an obtuse angle with the surface of the first semiconductor layer.

10. The light-emitting element according to claim 8, wherein the first insulating layer includes a bragg reflector (DBR) structure.

11. The light-emitting device according to claim 1 or 8, wherein the semiconductor structure comprises a thimble region at a geometric center of the light-emitting device, the thimble region is not connected to the first contact layer and the second contact layer, and is electrically isolated from each other.